JP2644115B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a buffer circuit having an N-channel transistor as a load-side transistor and a driver-side transistor as an output.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional semiconductor device having an input / output buffer. In the figure, reference numeral 103 denotes an I / O line for inputting / outputting data, and an output buffer 100 is provided at a subsequent stage. And an input buffer 101 are connected in parallel.
2 are connected.

The load-side Tr ₂ and the driver-side Tr ₃ constituting the output buffer 100 are n-type MOS transistors, respectively, and are connected in series between a power supply V _CC and a ground V _SS . The source and drain of the n-type MOS transistor Tr ₁ are respectively "H" signal [psi _H and the gate of the transistor Tr ₂ to output the data is connected, the delay circuit 2 and an inverter receiving the signal [psi _H to the gate 1 of the output node N ₂ is connected also to the node N ₁ to be connected to the gate of the transistor Tr ₂ output of the booster circuit 3 for receiving the signal [psi _H is connected. On the other hand, the signal for outputting the "L" data to the gate of the transistor Tr ₃ [psi _L is connected. Note that R
Represents wiring resistance, L represents inductance of wiring or wiring, and C represents stray capacitance or wiring capacitance.

Next, the operation will be described with reference to FIG.
Here, a semiconductor memory device (for example, a dynamic random access memory: DRAM) is used as an example, and ext /
RAS, ext / CAS indicates an external control signal, and Add
r represents an external address. Normally, when the control signals ext / RAS and ext / CAS are Low, the DRAM is in an active state, and data corresponding to each address is output each time the address is switched. here,
"H" data from the address (X, Y ₁ ), "L" data from the address (X, Y ₂ ), and address (X, Y ₁ )
₃ ) shows a case where "H" data is output.

[0005] First, when "H" data is output, when the signal に な る_H goes high, the node N _{1 which} has been low until now goes high. Thereafter, the node N ₂ through the delay circuit 2 and the inverter 1 is turned off and the gate of the "L" next to the transistor Tr _1, the booster circuit 3
There signal [psi _H is boosted operating, the node N ₁ becomes a higher level of (V _CC + α) potential. Normally, this boosting operation is performed when the voltage applied to the input / output pins in the DRAM is (V _CC +
1.5) Since the potential up to V is guaranteed, p-type MOS
The transistor cannot be used, and the n-type MOS transistor T
use the r ₂ as a load transistor. However, since the threshold voltage V _th amount corresponding output level of the load transistor decreases, low V _CC by boosting the level of the gate-level as described above (V _CC + alpha) that is (V _CC + V _th or more) However, the "H" level of the output can be guaranteed.

Then, following the above operation, the transistor Tr
₂ is turned on in response to the potential of the node N _1, V from the power supply
The potential of the _CC level is applied, and "H" data is output to the I / O line 103.

[0007] Then when outputting "L" data, the signal [psi _H is Low level, and the signal [psi _L is next High, the transistor Tr ₂ potential is lowered at the node N ₁ is turned off. On the other hand, when the transistor Tr ₃ is turned on,
It is pulled to the ground and becomes the potential of the V _SS level, and the I / O line 10
3, "L" data is output. During the output operation, the timing of the input buffer 101 and the like is controlled so that the output of the output buffer 100 is not transmitted to the internal circuit 102.

[0008]

Since the conventional semiconductor device is configured as described above, the gate level of the output load transistor must be (V _CC + V _th or more, that is, V _CC) regardless of the power supply V _CC level. + Α). However, actually, the I / O line 103 and the output buffer 1
Since there are components such as a resistance R, an inductance L, a capacitance C, and the like between 00 and 00, when Low data is output to the output of the I / O line 103, ringing occurs due to these components, as shown in FIG. L data rises float only V _OL level.

In a DRAM, the standard of Low data is very strict, usually 0.4 V. Therefore, when a V _CC higher than the output “H” level is used, the degree of floating (V _OL ) is further increased. , Low data is no longer margined. To avoid this, it seems that boosting should not be performed. However, if boosting is not performed, there is a problem that the output “H” level at low V _CC has no margin with respect to the standard. Therefore, there is a problem that it is difficult to secure a sufficient margin for the output level standard while performing the boosting operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to suppress the floating due to the ringing of the output Low data when a high V _CC is used, and to use a low V _CC . It is an object of the present invention to provide a semiconductor device in which the level of output "H" data can sometimes provide a sufficient margin with respect to the standard.

[0011]

A semiconductor device according to the present invention comprises a booster circuit control means for detecting a potential of a power supply voltage and stopping a boosting operation when the value is larger than a predetermined value.

[0012]

According to the present invention, booster circuit control means for detecting the potential of the power supply voltage and controlling the operation of the booster circuit in accordance with the value is provided. Only when the power supply voltage is high, it is possible to suppress the floating due to the ringing of the output Low data at the time of the high power supply voltage, and to provide a sufficient margin for the output “H” data level with respect to the standard even at the low power supply voltage. be able to.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same reference numerals as those in FIG. 4 denote the same or corresponding parts. Reference numeral 104 denotes an output buffer circuit, and a power supply voltage detection circuit (boost circuit control means) 14 is inserted before the boost circuit 3. FIG. 2 shows an example of the power supply voltage detection circuit 14. In FIG.
The signal ψ _H and the node N ₁₂ , and the node N ₁₂ and the ground potential V _SS
Between the n-type MOS transistor Tr ₂₁ and the p-type MO transistor.
S transistor Tr ₂₂ and n-type MOS transistor T
A transmission type gate composed of r ₂₆ and a p-type MOS transistor Tr ₂₇ is inserted. Also,
Between the power supply voltage V _CC and the ground potential V _SS , a p-type MOS transistor T connected in series in n stages and having the same threshold value
r ₂₃ , Tr ₂₄ , an n-type MOS transistor Tr ₂₅ to which a signal / CS for controlling chip selection / non-selection is input to the gate via an inverter 23, and a high resistance element R ₂ are connected in series.

[0014] node N ₁₃ between the transistor Tr ₂₅ and the high-resistance element R ₂ are connected to the inverter 22,
The output of the inverter 22 is connected to one transistor T of each of the two transmission type gates.
The other transistors Tr ₂₂ and Tr ₂₆ which are input to the gates of r ₂₁ and Tr ₂₇ and constitute the transmission type gate via the inverter 21.
It is connected to the. Also, the inverter 25 functions as a latch.

Next, the operation will be described with reference to FIG.
The chip selection / non-selection control signal / CS is set to be low when the signals / RAS and / CAS are in the low state, that is, in the output enabled state. As shown in FIG. 2, to input the signal / CS to the power supply voltage detection circuit, when no output, i.e. / RAS, / CAS is a resistor R ₂ from the power supply potential V _CC during standby "H" This is to eliminate a through current flowing through the device. When the signal / CS becomes low, the inverter 2 constituting the power supply voltage detection circuit 14
3, the signal is inverted to a high level, and the transistor Tr ₂₅ is turned on. Since the potential of where the node N ₁₃ flows the power supply potential V _CC via a p-type MOS transistor Tr _23, Tr ₂₄ which is connected to n stages, also the resistance R ₂ is a high-resistance, (V _CC -n | V _th |) V. Here, V _th is the threshold voltage of the transistors Tr ₂₃ and Tr ₂₄ . That is, the node N ₁₃ becomes the potential of the potential of the n-stage partial threshold V _th is subtracted supply potential V _CC from the transistor Tr _23, Tr ₂₄ appears.

[0016] Then by setting the number of stages n of the transistors arbitrarily, it is possible to change the level appearing at node N _13. For example, the number of transistor stages n = 6,
The threshold voltage of each p-type MOS transistor | V _th | =
When 0.5V, the level of the node N ₁₃ is the power supply voltage V _CC
When is the 5V, 5-6 × 0.5 (V) = 2 (V) becomes also becomes 1.5V when the V _CC = 4.5V. Also it is possible to select a node by the threshold setting of the inverter 22 which receives the level of the N _13, "H" of the output of the inverter 22 by the level of the node N _13, "L".
If the threshold value of the inverter 22 is set to 1.7 V, when the power supply potential V _CC = 4.5 V, the potential of the node N ₁₃ becomes 1.5 V and the output of the inverter 22 becomes “H”.
The transmission gate formed of the transistors Tr ₂₁ and Tr ₂₂ is turned on, the signal ψ _H and the node N ₁₂ have the same potential, the boosting circuit 3 connected to the subsequent stage is activated, and therefore the node N ₁ is also boosted, and the I / O is performed. A waveform shown by a broken line in FIG.

On the other hand, when the power supply voltage V _cc = 5 V, the potential of the node N ₁₃ becomes 2 V, the output of which exceeds the threshold voltage 1.7 V of the inverter 22 and becomes a low level, and the transistors Tr ₂₆ and Tr ₂₇ output from the transistors Tr ₂₆ and Tr _27. node N ₁₂ transmission gate is turned on made is connected to the ground potential V _SS,
The subsequent booster circuit 3 does not operate. Therefore, the boosting operation is not performed, and the waveform shown by the broken line in FIG. 3 appears on the I / O line 103.

As described above, according to the present embodiment, the booster circuit 3
The power supply voltage detection circuit 14 provided in front of, by adjusting the transistor stages of the transistor series circuit of the circuit 14 determines the level of the magnitude of the supply voltage V _CC, than the power supply voltage V _CC is a predetermined value performs a boosting operation by driving the booster circuit 3 are connected to signal [psi _H to node N ₁₂ when small, when the power supply voltage V _CC is greater than a predetermined value by connecting the node N ₁₂ to the ground potential V _SS boost Since the circuit 3 is not driven, the floating due to ringing can be suppressed when the output level changes from H to L even when a high power supply voltage is used (V _OL ′ <V _OL ), and a low power supply voltage is used. In this case, the level of the output "H" data can have a sufficient margin with respect to the standard.

[0019]

As described above, according to the semiconductor device of the present invention, the booster circuit control means for detecting the potential of the power supply voltage and controlling the operation of the booster circuit according to the value is provided. time without boosting, it is so arranged to boost only when at a low power supply voltage, it is possible to reduce the raised data by ringing when becomes low data from high at high V _CC, also lower V H at _CC
There is an effect that the level of the high data can provide a sufficient margin with respect to the standard.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a power supply voltage detection circuit of a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a timing chart showing a circuit operation of the semiconductor device according to one embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional semiconductor device.

FIG. 5 is a timing chart showing the operation of a conventional semiconductor device.

[Explanation of symbols]

14 power supply voltage detection circuit (step-up circuit control means) 100 Output buffer 103 I / O line R the resistance component R ₂ the resistance component C capacitance component L inductance component Tr ₁ n-type MOS transistor Tr ₂ n-type MOS transistor (load-side transistors) Tr ₃ n-type MOS transistor (driver-side transistor) Tr ₂₁ n-type MOS transistor Tr ₂₅ n-type MOS transistor Tr ₂₆ n-type MOS transistor Tr ₂₂ p-type MOS transistor Tr ₂₃ p-type MOS transistor Tr ₂₄ p-type MOS transistor Tr ₂₇ p-type MOS transistor

Claims (1)

(57) [Claims] A load-side transistor having a source and a drain connected between a power supply voltage source and an output terminal;
A semiconductor device comprising: a driver-side transistor whose source and drain are connected between a ground potential source and the output terminal; and a booster circuit that boosts a voltage applied to a gate voltage of the load-side transistor. A semiconductor device comprising a booster circuit control means for detecting a potential of a power supply voltage source and stopping a boosting operation of the booster circuit when the potential is larger than a predetermined value.