JP2641975B2 - Superconducting element and fabrication method - Google Patents
Superconducting element and fabrication methodInfo
- Publication number
- JP2641975B2 JP2641975B2 JP2270070A JP27007090A JP2641975B2 JP 2641975 B2 JP2641975 B2 JP 2641975B2 JP 2270070 A JP2270070 A JP 2270070A JP 27007090 A JP27007090 A JP 27007090A JP 2641975 B2 JP2641975 B2 JP 2641975B2
- Authority
- JP
- Japan
- Prior art keywords
- superconducting
- thin film
- channel
- substrate
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims description 38
- 239000010409 thin film Substances 0.000 claims description 34
- 239000010408 film Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000013078 crystal Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000002887 superconductor Substances 0.000 description 28
- 238000004544 sputter deposition Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 229910002480 Cu-O Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910015901 Bi-Sr-Ca-Cu-O Inorganic materials 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 210000003754 fetus Anatomy 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 229910020068 MgAl Inorganic materials 0.000 description 1
- 229910009203 Y-Ba-Cu-O Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、超電導素子およびその作製方法に関する。
より詳細には、新規な構成の超電導素子およびその作製
方法に関する。Description: TECHNICAL FIELD The present invention relates to a superconducting element and a method for manufacturing the same.
More specifically, the present invention relates to a superconducting element having a novel configuration and a method for manufacturing the same.
従来の技術 超電導を使用した代表的な素子に、ジョセフソン素子
がある。ジョセフソン素子は、一対の超電導体をトンネ
ル障壁を介して結合した構成であり、高速スイッチング
動作が可能である。しかしながら、ジョセフソン素子は
２端子の素子であり、論理回路を実現するためには複雑
な回路構成になってしまう。2. Description of the Related Art A typical element using superconductivity is a Josephson element. The Josephson element has a configuration in which a pair of superconductors are coupled via a tunnel barrier, and can perform high-speed switching operation. However, the Josephson element is a two-terminal element, and requires a complicated circuit configuration to realize a logic circuit.
一方、超電導を利用した３端子素子としては、超電導
ベーストランジスタ、超電導FET等がある。第３図に、
超電導ベーストランジスタの概念図を示す。第３図の超
電導ベーストランジスタは、超電導体または常電導体で
構成されたエミッタ21、絶縁体で構成されたトンネル障
壁22、超電導体で構成されたベース23、半導体アイソレ
ータ24および常電導体で構成されたコレクタ25を積層し
た構成になっている。この超電導ベーストランジスタ
は、トンネル障壁22を通過した高速電子を利用した低電
力消費、高速動作の素子である。On the other hand, examples of a three-terminal element utilizing superconductivity include a superconducting base transistor and a superconducting FET. In FIG.
1 shows a conceptual diagram of a superconducting base transistor. The superconducting base transistor shown in FIG. 3 comprises an emitter 21 composed of a superconductor or a normal conductor, a tunnel barrier 22 composed of an insulator, a base 23 composed of a superconductor, a semiconductor isolator 24, and a normal conductor. The collector 25 is stacked. This superconducting base transistor is an element of low power consumption and high speed operation utilizing high speed electrons passing through the tunnel barrier 22.
第４図に、超電導FETの概念図を示す。第４図の超電
導FETは、超電導体で構成されている超電導ソース電極4
1および超電導ドレイン電極42が、半導体層43上に互い
に近接して配置されている。超電導ソース電極41および
超電導ドレイン電極42の間の部分の半導体層43は、下側
が大きく削られ厚さが薄くなっている。また、半導体層
43の下側表面にはゲート絶縁膜46が形成され、ゲート絶
縁膜46上にゲート電極44が設けられている。FIG. 4 shows a conceptual diagram of a superconducting FET. The superconducting FET shown in FIG. 4 has a superconducting source electrode 4 composed of a superconductor.
1 and the superconducting drain electrode 42 are arranged on the semiconductor layer 43 close to each other. The lower portion of the semiconductor layer 43 between the superconducting source electrode 41 and the superconducting drain electrode 42 is largely shaved and thin. Also, the semiconductor layer
A gate insulating film 46 is formed on the lower surface of 43, and a gate electrode 44 is provided on the gate insulating film 46.
超電導FETは、超電導近接効果で超電導ソース電極41
および超電導ドレイン電極42間の半導体層43を流れる超
電導電流を、ゲート電圧で制御する低電力消費、高速動
作の素子である。The superconducting FET has a superconducting source electrode 41 due to the superconducting proximity effect.
Further, the superconducting current flowing in the semiconductor layer 43 between the superconducting drain electrodes 42 is controlled by a gate voltage, and is a low power consumption and high speed operation element.
さらに、ソース電極、ドレイン電極間に超電導体でチ
ャネルを形成し、この超電導チャネルを流れる電流をゲ
ート電極に印加する電圧で制御する３端子の超電導素子
も発表されている。Further, a three-terminal superconducting element in which a channel is formed by a superconductor between a source electrode and a drain electrode and a current flowing through the superconducting channel is controlled by a voltage applied to a gate electrode has been disclosed.
発明が解決しようとする課題 上記の超電導ベーストランジスタおよび超電導FET
は、いずれも半導体層と超電導体層とが積層された部分
を有する。ところが、近年研究が進んでいる酸化物超電
導体を使用して、半導体層と超電導体層との積層構造を
作製することは困難である。また、この構造が作製でき
ても半導体層と超電導体層の間の界面の制御が難しく、
素子として満足な動作をしなかった。PROBLEM TO BE SOLVED BY THE INVENTION Superconducting base transistor and superconducting FET described above
Have a portion where a semiconductor layer and a superconductor layer are laminated. However, it is difficult to produce a stacked structure of a semiconductor layer and a superconductor layer using an oxide superconductor that has been studied in recent years. In addition, even if this structure can be manufactured, it is difficult to control the interface between the semiconductor layer and the superconductor layer,
The device did not operate satisfactorily.
また、超電導FETは、超電導近接効果を利用するた
め、超電導ソース電極41および超電導ドレイン電極42
を、それぞれを構成する超電導体のコヒーレンス長の数
倍程度以内に近接させて作製しなければならない。特に
酸化物超電導体は、コヒーレンス長が短いので、酸化物
超電導体を使用した場合には、超電導ソース電極41およ
び超電導ドレイン電極42間の距離は、数10nm以下にしな
ければならない。このような微細加工は非常に困難であ
り、従来は酸化物超電導体を使用した超電導FETを再現
性よく作製できなかった。In addition, the superconducting FET uses the superconducting proximity effect, so that the superconducting source electrode 41 and the superconducting drain electrode 42
Must be made close to each other within about several times the coherence length of the superconductor constituting each. In particular, since the oxide superconductor has a short coherence length, when an oxide superconductor is used, the distance between the superconducting source electrode 41 and the superconducting drain electrode 42 must be several tens nm or less. Such microfabrication is very difficult, and conventionally, a superconducting FET using an oxide superconductor could not be produced with good reproducibility.
さらに、従来の超電導チャネルを有する超電導素子
は、変調動作は確認されたが、キャリア密度が高いた
め、完全なオン／オフ動作ができなかった。酸化物超電
導体は、キャリア密度が低いので、超電導チャネルに使
用することにより、完全なオン／オフ動作を行う上記の
素子の実現の可能性が期待されている。しかしながら、
超電導チャネルは5nm以下の厚さにしなければならず、
そのような構成の実現することは困難であった。Further, in the conventional superconducting element having a superconducting channel, a modulation operation was confirmed, but complete on / off operation could not be performed due to a high carrier density. Since the oxide superconductor has a low carrier density, the possibility of realizing the above-mentioned element which performs a complete on / off operation by using it for a superconducting channel is expected. However,
The superconducting channel must be less than 5nm thick,
It has been difficult to realize such a configuration.
そこで本発明の目的は、上記従来技術の問題点を解決
した、新規な構成の超電導素子およびその作製方法を提
供することにある。Therefore, an object of the present invention is to provide a superconducting element having a novel configuration and a method of manufacturing the superconducting element, which has solved the above-mentioned problems of the related art.
課題を解決するための手段 本発明に従うと、基板上に成膜された酸化物超電導薄
膜に形成された超電導チャネルと、該超電導チャネルの
両端近傍に配置されて該超電導チャネルに電流を流すソ
ース電極およびドレイン電極と、前記超電導チャネル上
に配置されて該超電導チャネルに流れる電流を制御する
ゲート電極を具備する超電導素子において、前記基板が
突出部を有し、前記酸化物超電導薄膜がｃ軸配向の酸化
物超電導体結晶で構成され、且つ前記突出部上の部分が
薄くされており、前記酸化物超電導薄膜の前記薄い部分
が、前記超電導チャネルであり、前記ソース電極および
前記ドレイン電極がａ軸配向の酸化物超電導体結晶で構
成されていることを特徴とする超電導素子が提供され
る。Means for Solving the Problems According to the present invention, a superconducting channel formed on an oxide superconducting thin film formed on a substrate, and a source electrode disposed near both ends of the superconducting channel and flowing a current through the superconducting channel And a drain electrode, a superconducting element comprising a gate electrode disposed on the superconducting channel and controlling a current flowing through the superconducting channel, wherein the substrate has a protrusion, and the oxide superconducting thin film has a c-axis orientation. The thin film of the oxide superconducting thin film is the superconducting channel, and the source electrode and the drain electrode are a-axis oriented. A superconducting element characterized by comprising an oxide superconducting crystal of the present invention.
また、本発明では、上記の超電導素子を作製する方法
として、突出部が形成された絶縁体基板上または突出部
が形成され、且つ絶縁膜を表面に有する半導体基板上
に、前記突出部上の厚さが5nm以下のｃ軸配向の酸化物
超電導薄膜を形成し、該ｃ軸配向の酸化物超電導薄膜の
前記突出部上の両側の部分を10nm以上エッチングし、該
エッチング部上にａ軸配向の酸化物薄膜を形成する工程
を含むことを特徴とする超電導素子の作製方法が提供さ
れる。Further, in the present invention, as a method of manufacturing the above-described superconducting element, on the insulating substrate on which the protruding portion is formed or on a semiconductor substrate on which the protruding portion is formed and the insulating film is provided on the surface of the protruding portion, A c-axis oriented oxide superconducting thin film having a thickness of 5 nm or less is formed, and both sides of the c-axis oriented oxide superconducting thin film on the protruding portions are etched by 10 nm or more. And a method of manufacturing a superconducting element, comprising the step of forming an oxide thin film of (a).
作用 本発明の超電導素子は、ｃ軸配向の酸化物超電導薄膜
による超電導チャネルと、超電導チャネルの両側に配置
されたａ軸配向の酸化物超電導薄膜による超電導ソース
電極および超電導ドレイン電極と、超電導チャネルを流
れる電流を制御するゲート電極とを具備する。The superconducting element of the present invention comprises a superconducting channel formed by a c-axis oriented oxide superconducting thin film, a superconducting source electrode and a superconducting drain electrode formed by an a-axis oriented oxide superconducting thin film disposed on both sides of the superconducting channel, and a superconducting channel. A gate electrode for controlling a flowing current.
従来の超電導FETが、超電導近接効果を利用して半導
体中に超電導電流を流すのに対し、本発明の超電導素子
では、主電流は超電導体中を流れる。従って、従来の超
電導FETを作製するときに必要な微細加工技術の制限が
緩和される。While a conventional superconducting FET uses a superconducting proximity effect to flow a superconducting current through a semiconductor, in the superconducting element of the present invention, a main current flows through the superconductor. Therefore, the limitation of the fine processing technology required when manufacturing the conventional superconducting FET is eased.
超電導チャネルは、ゲート電極に印加された電圧で開
閉させるために、ゲート電流により発生される電界の方
向で、厚さが5nm以下でなければならない。本発明の超
電導素子では、突出部を設けた基板上に形成されたｃ軸
配向の酸化物超電導薄膜の、基板の突出部により薄くな
った部分を超電導チャネルとする。The superconducting channel must be less than 5 nm thick in the direction of the electric field generated by the gate current in order to open and close with the voltage applied to the gate electrode. In the superconducting element of the present invention, a portion of the c-axis-oriented oxide superconducting thin film formed on the substrate provided with the protrusion, which is thinned by the protrusion of the substrate is defined as a superconducting channel.
突出部を設けた基板上に単に酸化物超電導薄膜を成長
させただけでは、突出部上にも同じ厚さの薄膜が形成さ
れるので、本発明の方法では薄膜を形成後薄膜表面を平
坦にし、薄膜の基板突出部上の部分を薄くする。Simply growing an oxide superconducting thin film on the substrate provided with the protrusions also forms a thin film of the same thickness on the protrusions, so the method of the present invention flattens the thin film surface after forming the thin film. Then, the portion of the thin film on the substrate protrusion is thinned.
酸化物超電導体は、一般に結晶方向により超電導特性
が異なり、特に臨界電流密度は結晶のｃ軸に垂直な方向
が大きい。この結果、従来のソース電極、ドレイン電極
の構造では、極薄の超電導チャネルに均一に電流を流す
ことは難しい。本発明の超電導素子では、超電導ソース
電極および超電導ドレイン電極はａ軸配向の酸化物超電
導薄膜を使用しているので、主電流が基板に垂直な方向
に流れ、超電導チャネルはｃ軸配向の酸化物超電導薄膜
を使用しているので、基板に平行な方向に流れる。即
ち、本発明の超電導素子は、超電導ソース電極、超電導
ドレイン電極および超電導チャネルのいずれもが酸化物
超電導体の臨界電流密度の大きい方向に主電流が流れる
ように構成されている。Oxide superconductors generally have different superconducting characteristics depending on the crystal direction. Particularly, the critical current density is large in the direction perpendicular to the c-axis of the crystal. As a result, it is difficult for the conventional structure of the source electrode and the drain electrode to uniformly supply current to the ultra-thin superconducting channel. In the superconducting element of the present invention, since the superconducting source electrode and the superconducting drain electrode use an a-axis oriented oxide superconducting thin film, the main current flows in a direction perpendicular to the substrate, and the superconducting channel is c-axis oriented oxide. Since a superconducting thin film is used, it flows in a direction parallel to the substrate. That is, the superconducting element of the present invention is configured such that the main current flows in the direction in which the critical current density of the oxide superconductor increases in all of the superconducting source electrode, the superconducting drain electrode, and the superconducting channel.
本発明の方法では、超電導チャネルのｃ軸配向の酸化
物超電導薄膜を成膜するのに、基板温度を約700℃とす
る。また、ソース電極およびドレイン電極のａ軸配向の
酸化物超電導薄膜は、成膜時の基板温度を約650℃以下
として成膜する。どちらの場合も成膜法としては、スパ
ッタリング法、MBE（分子ビームエピタキシ）法、真空
蒸着法等が使用できる。In the method of the present invention, the substrate temperature is set to about 700 ° C. to form a c-axis oriented oxide superconducting thin film of the superconducting channel. The a-axis oriented oxide superconducting thin film of the source electrode and the drain electrode is formed at a substrate temperature of about 650 ° C. or lower during film formation. In either case, as a film forming method, a sputtering method, an MBE (molecular beam epitaxy) method, a vacuum evaporation method, or the like can be used.
本発明の超電導素子において、絶縁体基板には、Mg
O、SrTiO3等の酸化物単結晶基板が使用可能である。こ
れらの基板上には、配向性の高い酸化物超電導体結晶か
らなる酸化物超電導薄膜を成長させることが可能である
ので好ましい。また、表面に絶縁層を有する半導体基板
を使用することもできる。In the superconducting device of the present invention, the insulator substrate is made of Mg.
O, SrTiO 3 and other oxide single crystal substrates can be used. On these substrates, an oxide superconducting thin film made of an oxide superconducting crystal having high orientation can be grown, which is preferable. Alternatively, a semiconductor substrate having an insulating layer on the surface can be used.
本発明の超電導素子には、Ｙ−Ba−Cu−Ｏ系酸化物超
電導体、Bi−Sr−Ca−Cu−Ｏ系酸化物超電導体、Tl−Ba
−Ca−Cu−Ｏ系酸化物超電導体等任意の酸化物超電導体
を使用することができる。The superconducting element of the present invention includes a Y-Ba-Cu-O-based oxide superconductor, a Bi-Sr-Ca-Cu-O-based oxide superconductor, a Tl-Ba
Any oxide superconductor such as -Ca-Cu-O-based oxide superconductor can be used.
以下、本発明を実施例により、さらに詳しく説明する
が、以下の開示は本発明の単なる実施例に過ぎず、本発
明の技術的範囲をなんら制限するものではない。Hereinafter, the present invention will be described in more detail with reference to examples. However, the following disclosure is merely an example of the present invention, and does not limit the technical scope of the present invention.
実施例 第１図に、本発明の超電導素子の断面図を示す。第１
図の超電導素子は、突出部50を有する基板５上に形成さ
れた超電導層１を有する。超電導層１は、ｃ軸配向の酸
化物超電導薄膜で構成され、超電導層１の基板５の突出
部50の上の部分は、厚さ5nm以下になっており超電導チ
ャネル10になっている。また、超電導層１の超電導チャ
ネル10の両側は、10nm程度低くなっており、ａ軸配向の
酸化物超電導薄膜で構成されたソース電極２およびドレ
イン電極３が配置されている。さらに、超電導チャネル
10の上には絶縁膜６を介してゲート電極４が配置されて
いる。Embodiment FIG. 1 shows a sectional view of a superconducting element of the present invention. First
The superconducting element shown has a superconducting layer 1 formed on a substrate 5 having a protrusion 50. The superconducting layer 1 is composed of a c-axis oriented oxide superconducting thin film, and the portion of the superconducting layer 1 above the protrusion 50 of the substrate 5 has a thickness of 5 nm or less and forms a superconducting channel 10. Further, both sides of the superconducting channel 10 of the superconducting layer 1 are lower by about 10 nm, and the source electrode 2 and the drain electrode 3 composed of the oxide superconducting thin film having the a-axis orientation are arranged. In addition, the superconducting channel
The gate electrode 4 is arranged on the insulating film 6 via the insulating film 6.
第２図を参照して、本発明の超電導素子を本発明の方
法で作製する手順を説明する。まず、第２図（ａ）に示
すような基板５に突出部50を形成する。基板５として
は、MgO（100）基板、SrTiO3（100）基板等の絶縁体基
板、または表面に絶縁膜を有するSi（100）等の半導体
基板が好ましい。ただし、半導体基板を使用する場合に
は、後述するよう突出部50を形成後、表面に絶縁膜を形
成する。With reference to FIG. 2, a procedure for manufacturing the superconducting element of the present invention by the method of the present invention will be described. First, the protrusion 50 is formed on the substrate 5 as shown in FIG. The substrate 5 is preferably an insulator substrate such as a MgO (100) substrate, a SrTiO 3 (100) substrate, or a semiconductor substrate such as Si (100) having an insulating film on the surface. However, when a semiconductor substrate is used, an insulating film is formed on the surface after forming the protrusion 50 as described later.
次に、第２図（ｂ）に示すよう、基板５の一部をフォ
トレジスト８で被覆し、Arイオンエッチング等のドライ
エッチング法で表面を削り、突出部50を形成する。Next, as shown in FIG. 2 (b), a part of the substrate 5 is covered with a photoresist 8, and the surface is shaved by a dry etching method such as Ar ion etching to form a projection 50.
半導体基板を使用する場合は、結晶方向も重要であ
り、上述のように手順も多少異なる。例えば、Si（10
0）基板を使用する場合、Si（100）面に対し、ゲート長
手方向、即ち、チャネルの電流の流れる方向に向かって
垂直方向が（110）面になるようフォトレジスト８を形
成する。このSi基板をKOHまたはAPW等のエッチング液を
使用してエッチングし、突出部50を形成する。この基板
の表面に、例えばCVD法でMgAl2O4層およびスパッタリン
グ法でBaTiO3層を連続して積層する。When a semiconductor substrate is used, the crystal direction is also important, and the procedure is slightly different as described above. For example, Si (10
0) When a substrate is used, the photoresist 8 is formed so that the (110) plane is oriented in the gate longitudinal direction, that is, the direction perpendicular to the direction in which the channel current flows, with respect to the Si (100) plane. The Si substrate is etched using an etchant such as KOH or APW to form the protrusion 50. On the surface of this substrate, for example, a MgAl 2 O 4 layer is continuously laminated by a CVD method and a BaTiO 3 layer is laminated by a sputtering method.
次に、第２図（ｃ）に示すよう加工した基板５上にｃ
軸配向の酸化物超電導薄膜をオフアクシススパッタリン
グ法、反応性蒸着法、MBE法、CVD法等の方法で成膜し、
超電導層１を形成する。酸化物超電導体としては、Ｙ−
Ba−Cu−Ｏ系酸化物超電導体、Bi−Sr−Ca−Cu−Ｏ系酸
化物超電導体、Tl−Ba−Ca−Cu−Ｏ系酸化物超電導体が
好ましい。オフアクシススパッタリング法でY1Ba2Cu3O
7-Xc軸配向の酸化物超電導薄膜を成膜する場合のスパッ
タリング条件を以下に示す。Next, on the substrate 5 processed as shown in FIG.
An axially oriented oxide superconducting thin film is formed by a method such as off-axis sputtering, reactive evaporation, MBE, or CVD,
The superconducting layer 1 is formed. As an oxide superconductor, Y-
Ba-Cu-O-based oxide superconductors, Bi-Sr-Ca-Cu-O-based oxide superconductors, and Tl-Ba-Ca-Cu-O-based oxide superconductors are preferred. Y 1 Ba 2 Cu 3 O by off-axis sputtering
The sputtering conditions for forming a 7-X c-axis oriented oxide superconducting thin film are shown below.
スパッタリングガス Ar:90％ O2:10％ 圧 力 10Pa 基板温度 700℃ 超電導層１の突出部50上の部分の厚さが5nm以下にな
るよう、超電導層１を形成する。次いで第２図（ｄ）に
示すよう、超電導層１上に絶縁膜16を形成する。絶縁膜
16はMgOが好ましいが、他にも酸化物超電導薄膜との界
面で大きな準位を作らない絶縁体を用いることが好まし
い。次いで第２図（ｅ）に示すよう、絶縁膜16上に常電
導体膜17を成膜する。常電導体膜17には、AuまたはTi、
Ｗ等の高融点金属、これらのシリサイドを用いることが
好ましい。界面準位の抑制、汚染の防止および機械的応
力の減少等の観点から、上記の絶縁膜16および常電導体
膜17は超電導層１に連続して形成することが望ましい。Sputtering gas Ar: 90% O 2 : 10% Pressure 10 Pa Substrate temperature 700 ° C. The superconducting layer 1 is formed such that the thickness of the portion of the superconducting layer 1 on the protrusion 50 is 5 nm or less. Next, an insulating film 16 is formed on the superconducting layer 1 as shown in FIG. Insulating film
16 is preferably MgO, but it is also preferable to use an insulator that does not form a large level at the interface with the oxide superconducting thin film. Next, as shown in FIG. 2E, a normal conductor film 17 is formed on the insulating film 16. Au or Ti,
It is preferable to use a high melting point metal such as W, or a silicide thereof. The insulating film 16 and the normal conductor film 17 are desirably formed continuously with the superconducting layer 1 from the viewpoints of suppressing interface states, preventing contamination, and reducing mechanical stress.
次いで、耐熱マスク膜９でゲート電極パターンを形成
し、反応性イオンエッチングまたはArイオンミリング等
で第２図（ｆ）に示すようゲート電極４および絶縁層６
を形成する。耐熱マスク膜９には、例えばMo等の高融点
金属が使用でき、真空蒸着法等で形成することが可能で
ある。必要に応じ、サイドエッチを促進し、ゲート電極
４および絶縁層６の長さを短くする。ゲート電極４およ
び絶縁層６を形成したら、第２図（ｇ）に示すよう、超
電導層１の超電導チャネル10両側の部分12、13をエッチ
ングして10nm以上低くする。Next, a gate electrode pattern is formed with the heat-resistant mask film 9, and the gate electrode 4 and the insulating layer 6 are formed by reactive ion etching or Ar ion milling as shown in FIG.
To form The heat-resistant mask film 9 can be made of, for example, a high-melting-point metal such as Mo, and can be formed by a vacuum evaporation method or the like. If necessary, the side etching is promoted, and the lengths of the gate electrode 4 and the insulating layer 6 are shortened. After the gate electrode 4 and the insulating layer 6 are formed, as shown in FIG. 2 (g), the portions 12, 13 on both sides of the superconducting channel 10 of the superconducting layer 1 are etched to lower the thickness by 10 nm or more.
第２図（ｈ）に示すよう、超電導層１と同じ酸化物超
電導体のａ軸配向の薄膜でソース電極２およびドレイン
電極３を形成する。ソース電極２およびドレイン電極３
は、約200nmの厚さに形成する。成膜方法は、オフアク
シススパッタリング法、反応性蒸着法、MBE法、CVD法等
任意の方法が選択できる。オフアクシススパッタリング
法でY1Ba2Cu3O7-Xa軸配向の酸化物超電導薄膜を成膜す
る場合のスパッタリング条件を以下に示す。As shown in FIG. 2 (h), the source electrode 2 and the drain electrode 3 are formed of an a-axis oriented thin film of the same oxide superconductor as the superconducting layer 1. Source electrode 2 and drain electrode 3
Is formed to a thickness of about 200 nm. An arbitrary method such as an off-axis sputtering method, a reactive evaporation method, an MBE method, and a CVD method can be selected as a film forming method. The sputtering conditions for forming an oxide superconducting thin film of Y 1 Ba 2 Cu 3 O 7-X a-axis orientation by off-axis sputtering are shown below.
スパッタリングガス Ar:90％ O2:10％ 圧 力 10Pa 基板温度 640℃ 同時に耐熱マスク膜９上にもａ軸配向の酸化物超電導
薄膜19が堆積するが、耐熱マスク膜９としてMoを使用す
れば成膜中に昇華して、第２図（ｉ）に示すように本発
明の超電導素子が完成する。また、耐熱マスク膜９に耐
熱レジストでなく絶縁膜を使用してゲート電極４上に残
したままでもよい。Sputtering gas Ar: 90% O 2 : 10% Pressure 10 Pa Substrate temperature 640 ° C. At the same time, the a-axis oriented oxide superconducting thin film 19 is deposited on the heat-resistant mask film 9. Sublimation occurs during film formation to complete the superconducting element of the present invention as shown in FIG. 2 (i). Alternatively, an insulating film may be used for the heat-resistant mask film 9 instead of a heat-resistant resist, and the heat-resistant mask film 9 may be left on the gate electrode 4.
本発明の超電導素子を本発明の方法で作製すると、超
電導チャネルに一様に電流を流すことができ、超電導FE
Tの特性を向上させることが可能である。また、超電導F
ETを作製する場合に要求される微細加工技術の制限が緩
和される。さらに、表面が平坦にできるので、後に必要
に応じ配線を形成することが容易になる。従って、作製
が容易であり、素子の性能も安定しており、再現性もよ
い。When the superconducting element of the present invention is manufactured by the method of the present invention, a current can be uniformly applied to the superconducting channel, and the superconducting FE
It is possible to improve the characteristics of T. Also, superconducting F
Restrictions on the fine processing technology required when manufacturing ET are relaxed. Further, since the surface can be flattened, it becomes easy to form wiring later if necessary. Therefore, fabrication is easy, the performance of the element is stable, and reproducibility is good.
発明の効果 以上説明したように、本発明の超電導素子は、超電導
チャネル中を流れる超電導電流をゲート電圧で制御する
構成となっている。従って、従来の超電導FETのよう
に、超電導近接効果を利用していないので微細加工技術
の制限が緩和される。また、超電導体と半導体を積層す
る必要もないので、酸化物超電導体を使用して高性能な
素子が作製できる。Effect of the Invention As described above, the superconducting element of the present invention has a configuration in which the superconducting current flowing in the superconducting channel is controlled by the gate voltage. Therefore, unlike the conventional superconducting FET, since the superconducting proximity effect is not used, the limitation of the fine processing technology is relaxed. Further, since there is no need to stack a superconductor and a semiconductor, a high-performance element can be manufactured using an oxide superconductor.
本発明により、超電導技術の電子デバイスへの応用が
さらに促進される。The present invention further promotes the application of superconducting technology to electronic devices.
第１図は、本発明の超電導素子の概略図であり、 第２図は、本発明の方法により本発明の超電導素子を作
製する場合の工程を示す概略図であり、 第３図は、超電導ベーストランジスタの概略図であり、 第４図は、超電導FETの概略図である。 〔主な参照番号〕 １……超電導層、２……ソース電極、 ３……超電導ドレイン電極、 ４……超電導ゲート電極、５……基板FIG. 1 is a schematic view of a superconducting element of the present invention, FIG. 2 is a schematic view showing a process for producing a superconducting element of the present invention by a method of the present invention, and FIG. FIG. 4 is a schematic diagram of a base transistor, and FIG. 4 is a schematic diagram of a superconducting FET. [Main Reference Numbers] 1 ... Superconducting layer, 2 ... Source electrode, 3 ... Superconducting drain electrode, 4 ... Superconducting gate electrode, 5 ... Substrate
Claims (2)
成された超電導チャネルと、該超電導チャネルの両端近
傍に配置されて該超電導チャネルに電流を流すソース電
極およびドレイン電極と、前記超電導チャネル上に配置
されて該超電導チャネルに流れる電流を制御するゲート
電極を具備する超電導素子において、前記基板が突出部
を有し、前記酸化性超電導薄膜がｃ軸配向の酸化物超電
導体結晶で構成され、且つ前記突出部上の部分が薄くさ
れており、前記酸化物超電導薄膜の前記薄い部分が、前
記超電導チャネルであり、前記ソース電極および前記ド
レイン電極がａ軸配向の酸化物超電導体結晶で構成され
ていることを特徴とする超電導素子。A superconducting channel formed on an oxide superconducting thin film formed on a substrate; a source electrode and a drain electrode disposed near both ends of the superconducting channel to flow a current through the superconducting channel; In a superconducting element including a gate electrode disposed on a channel and controlling a current flowing through the superconducting channel, the substrate has a protrusion, and the oxidizing superconducting thin film is formed of an oxide superconducting crystal having a c-axis orientation. And the portion on the protrusion is thinned, the thin portion of the oxide superconducting thin film is the superconducting channel, and the source electrode and the drain electrode are a-axis oriented oxide superconducting crystals. A superconducting element characterized by being constituted.
法において、突出部が形成された絶縁体基板上または突
出部が形成され、且つ絶縁膜を表面に有する半導体基板
上に、前記突出部上の厚さが5nm以下のｃ軸配向の酸化
物超電導薄膜を形成し、該ｃ軸配向の酸化物超電導薄膜
の前記突出部上の両側の部分を10nm以上エッチングし、
該エッチング部上にａ軸配向の酸化物薄膜を形成する工
程を含むことを特徴とする超電導素子の作製方法。2. The method of manufacturing a superconducting element according to claim 1, wherein the projecting portion is formed on an insulating substrate having a projecting portion formed thereon or on a semiconductor substrate having the projecting portion formed and having an insulating film on the surface. Forming a c-axis oriented oxide superconducting thin film having a thickness on the portion of 5 nm or less, etching both sides of the c-axis oriented oxide superconducting thin film on both sides on the protrusion by 10 nm or more,
A method for manufacturing a superconducting element, comprising a step of forming an a-axis-oriented oxide thin film on the etched portion.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2270070A JP2641975B2 (en) | 1990-10-08 | 1990-10-08 | Superconducting element and fabrication method |
| US07/771,986 US5236896A (en) | 1990-10-08 | 1991-10-08 | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material |
| DE69119022T DE69119022T2 (en) | 1990-10-08 | 1991-10-08 | Superconducting device with ultrathin channel made of oxidic superconducting material and method for its production |
| EP91402677A EP0480814B1 (en) | 1990-10-08 | 1991-10-08 | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same |
| CA002052970A CA2052970C (en) | 1990-10-08 | 1991-10-08 | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same |
| US08/053,401 US5322526A (en) | 1990-10-08 | 1993-04-28 | Method for manufacturing a superconducting device having an extremely thin superconducting channel formed of oxide superconductor material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2270070A JP2641975B2 (en) | 1990-10-08 | 1990-10-08 | Superconducting element and fabrication method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04145672A JPH04145672A (en) | 1992-05-19 |
| JP2641975B2 true JP2641975B2 (en) | 1997-08-20 |
Family
ID=17481107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2270070A Expired - Lifetime JP2641975B2 (en) | 1990-10-08 | 1990-10-08 | Superconducting element and fabrication method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2641975B2 (en) |
-
1990
- 1990-10-08 JP JP2270070A patent/JP2641975B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04145672A (en) | 1992-05-19 |
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