JP2641964B2 - Divider - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider that divides a high-frequency signal to obtain a signal of a predetermined frequency.

[Prior Art] Conventionally, on the basis of the clock CK ₁ of frequency f, at half-cycle timing of the frequency f, may require divided signal switches the High / Low. In this case, once on at that triggered the m = 2 times the multiplied signal mf (referred to as double-precision reduction, mf have the number of pulses of twice within one period of the clock CK _1), multiplied signal mf A frequency-divided signal (m / n) × f is generated by counting n pulses according to a desired frequency.

FIG. 3 is a circuit diagram showing an example of a conventional frequency divider, and FIG. 4 is a timing chart thereof. In FIG. 3, reference numeral 10 denotes a multiplying circuit, and D-FFs 12, 14, and 16 and an inverter.
18, and an OR gate 20 and the like. A counter 22 counts the pulses of the multiplied signal mf and outputs a frequency-divided signal (m / n) × f that switches between High and Low every n pulses. The generation of the multiplied signal mf is required clock CK ₁ higher-frequency clock CK _2, as shown in FIG. 4, the multiplied signal mf is generated in synchronization with the rising and falling timing of the clock CK ₁ You.

Also, as shown in FIG. 6, the circuit of FIG.
A multiplied signal mf can be generated. In other words, by delaying the clock CK ₁ in gate delay circuit 30 or CK delay circuit 32, an exclusive OR of the clock CK ₁ and the delayed signal CK _D by EXOR gate 34, it has occurred the multiplied signal mf.

[Problems to be Solved] However, in the conventional frequency division techniques as described above, as shown in FIGS. 3 and 4, in the case of using a fast clock CK ₂ from the clock CK ₁ to count , it was not possible to multiply the fastest clock is used on the system, for example, the clock CK _2.

Further, as shown in FIGS. 5 and 6, when a delay circuit is used, there is a disadvantage that the duty accuracy after the multiplication becomes unstable.

Then, in the prior art to use a multiplication techniques described above, since essentially doubling the frequency of the clock CK _1, the next stage counter 22, such as operation of the counter element can not keep up with the clock speed, it had problems in processing speed There was a risk of coming.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a frequency divider which can set the frequency division accuracy to double without using a frequency multiplication technique.

[Means for Solving the Problems] To achieve the above object, a frequency divider according to the present invention includes a counter for counting pulses of a clock signal, and every time the count value reaches a predetermined value, a count required time A frequency divider for generating a frequency-divided signal having a pulse width corresponding to a first clock generation circuit that outputs a clock signal in phase with the clock signal in synchronization with the rising and falling timings of the clock signal; A second clock generation circuit for outputting a clock signal having a phase opposite to that of the clock signal in synchronization with the falling and rising timings of the clock signal, and generating the first or second clock when the counter counts up The circuit is turned on / off alternately, and a clock signal input to the counter is a first or second clock signal. A switching circuit that outputs a switching signal for switching to either one of the clock signals, wherein the first clock generation circuit latches the switching signal in synchronization with rising and falling timings of the clock signal, thereby performing the switching. A first clock shaping circuit that converts a signal into a signal that changes in synchronization with rising and falling timings of the clock signal, and the first clock based on a switching signal shaped by the first clock shaping circuit A first selection circuit that outputs a signal to the counter, wherein the second clock generation circuit latches the switching signal in synchronization with rising and falling timings of the clock signal, and outputs the latched signal. By inverting the switching signal, the rising and falling timings of the clock signal A second clock shaping circuit that converts the signal into a signal that changes synchronously; and a second selection circuit that outputs the first clock signal to the counter based on the switching signal shaped by the first clock shaping circuit. And characterized in that:

[Operation] According to the frequency divider of the present invention having the above configuration, every time the phase of the clock signal is switched, a delay corresponding to a half cycle of the clock signal occurs until the first pulse is generated. By counting including the delay, a frequency-divided signal equivalent to the double-precision counting operation can be obtained.

Further, the switching signal is generated by the first and second clock shaping circuits inside the first and second clock generating circuits.
After being synchronized, so to speak, with the clock signal, it is supplied to the first and second selection circuits. Therefore, when switching the clock signal, a hazard or the like does not occur, and a stable operation can be realized.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of a frequency divider according to the present invention, and FIG. 2 is a timing chart thereof.

In FIG. 1, reference numeral 40 denotes a first clock generation circuit, which comprises an inverter 42, D-FFs 44, 46, 48, an AND gate 50, and the like. First clock signal generating circuit 40, as shown in FIG. 2, in synchronization with the rising and falling timing of the clock signal CK _1, generates a clock signal CK _A having the same phase as the clock CK _1.

Reference numeral 52 denotes a second clock signal generation circuit which includes inverters 54 and 5
6, 58, D-FF60, 62, 64, AND gate 66 and the like. Second clock generating circuit 52, as shown in FIG. 2, in synchronization with the falling and rising timings of the clock signal CK _1, generates a clock signal CK _B of the clock signal CK ₁ and opposite phase.

68 is an OR gate, and outputs a composite clock signal CK _C of the clock signal CK _A and CK _B to the counter 22. Counter 2
Reference numeral 2 denotes, for example, a frequency dividing circuit composed of D-FFs 70 and 72, a NAND gate 74, and the like. Note that the counter 22 is an example of a divide-by-3 circuit, but the present invention is not limited to this and can be set arbitrarily according to a desired number of divisions (= n). is there.

76 is a switching circuit, the clock counter 22 outputs a switching signal CK _S to operate / inoperative alternately the first or second clock generation circuit 40, 52 at the time of the count-up, is input to the counter 22 The signal is switched to either the first or second clock signal CA _A or CK _B (ie, the composite signal CK _C ).

In the above configuration, for example, the switching signal CK _S operates the first clock generation circuit 40 when the High, when the Low second
It is assumed that the clock generation circuit 52 operates. In FIG. 2, a first clock signal CA _A (composite clock signal C
When K _C ) is input to the counter 22, the counter 22 counts the pulses as shown by →→. Division number n = 3
, A pulse is counted, and a count-up signal Cout is output. Then, the count-up signal Cout
Switching signal in the switching circuit 76 in synchronization with the falling edge of
CK _S goes Low, the second clock generating circuit 50 is turned ON in place of the first clock generation circuit 40. From the second clock generating circuit 52, the second clock signal CK _B is generated,
This clock signal CK _B (composite clock signal CK _C ) is counted by the counter 22 in the same manner as described above. When the counter 22 counts up, the switching operation of the first and second clock generation circuits 40 and 52 is repeated.

Incidentally, as it is clear from the count duration of the pulse ,, of Figure 2, the the switching operation is performed, after switching, the time required to count the first pulse, the clock signal CK ₁ of a half A delay time corresponding to a cycle (= T / 2) is included. That is, counting three pulses by the counter 22 is substantially equivalent to counting 3.5 pulses. Thus, in double precision (precision of half period of the clock signal CK _1), it is possible to define the pulse width of the divided signal.

In the above embodiment, the counter 22 outputs a one-pulse count-up signal Cout.
The frequency-divided signal may be directly output from the counter 22. In this case, the switching circuit 76 is included in the counter 22. That is, the switching circuit 76 described in the present embodiment is used.
Switching signal CK _S of is not being relevant to the division signal of the present invention having a desired pulse width.

Thus, according to the present invention, a double-precision frequency division signal is obtained for the clock signal CK ₁ without using the multiplication technique.

[Effects of the Invention] As described above, according to the frequency divider of the present invention, by switching between the first and second clock generation circuits, the time required for counting the first pulse can be reduced by a half period of the clock signal. , And the pulse width of the frequency-divided signal can be defined in double precision, that is, in units of a half cycle of the clock signal.

Further, since the multiplication technique is not required and the pulse width of the clock signal input to the counter is the same as the pulse width of the original clock signal, it is not necessary to particularly consider the processing speed of the counter stage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a frequency divider according to the present invention, FIGS. 2 (a) to (h) are timing charts showing the operation of FIG. 1, and FIG. 3 is a conventional frequency divider. 4 (a) and 4 (b) are timing charts showing the operation of FIG. 3, FIG. 5 is a circuit diagram showing another example of the conventional multiplying circuit, FIG. 6 ( 5A to 5C are timing charts showing the operation of FIG. 22 counter 40 first clock generation circuit 52 second clock generation circuit 76 switching circuit

Claims (1)

(57) [Claims] 1. A frequency divider that includes a counter that counts pulses of a clock signal and that generates a frequency-divided signal having a pulse width corresponding to a count required time every time the count value reaches a predetermined value. A first clock generation circuit for outputting a clock signal having the same phase as the clock signal in synchronization with the rising and falling timings of the signal, and an opposite phase to the clock signal in synchronization with the falling and rising timings of the clock signal A second clock generation circuit that outputs a clock signal of the first and second clock generation circuits. When the counter counts up, the first or second clock generation circuit is turned on / off alternately, and the clock signal input to the counter is changed to a second A switching circuit that outputs a switching signal for switching to one of the first and second clock signals, Serial first clock generation circuit, by latching in synchronization with the switching signal to the rise and fall timing of the clock signal,
A first clock shaping circuit that converts the switching signal into a signal that changes in synchronization with the rising and falling timings of the clock signal; A first selection circuit that outputs the clock signal to the counter, wherein the second clock generation circuit latches and latches the switching signal in synchronization with rising and falling timings of the clock signal. A second clock shaping circuit that inverts the signal to convert the switching signal into a signal that changes in synchronization with the rising and falling timings of the clock signal; and a switching shaping circuit formed by the first clock shaping circuit. A second selection circuit that outputs the first clock signal to the counter based on a signal; Divider, which comprises.