JP2532831B2 - Memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline of the Invention] In an SRAM that writes and reads a large amount of random data at high speed, it is possible to use bipolar transistors in a data input circuit, a write control circuit, and a bit line signal level conversion circuit. The purpose is to write to the memory cell,
MOS transistors on the same substrate aiming to form a high-speed static RAM by reading with a small amplitude signal and by using a bipolar transistor with a large current driving force in a circuit that drives a large load capacitance. MOS with integrated bipolar transistor
ECL compatible SRAM using bipolar composite circuit.

[Conventional technology]

FIG. 3 shows an embodiment of a conventional MOS SRAM for writing and reading data at high speed in memory cells arranged in a matrix. The MOS SRAM shown in FIG. 3 includes an address buffer / decoder circuit 1, a memory cell array 2, a bit line pull-up circuit 3, a write control circuit 4, and a bit line signal level shift circuit.
5, the data line pull-up circuit 6, the data input circuit 7, the sense amplifier 8, and the output buffer circuit 9 are integrated on the same substrate. Power supply voltage is high potential power supply V _CC = 0V, low potential power supply V _EE
= 5.2V. The address buffer / decoder circuit 1 is
ECL input signal (high level -0.8 V, the low level -1.6V) A ₁ ~A _K
To a MOS level (high level V, low level −5.2V) to generate row selection signals (word line selection signals) WL _{1 to} WL _n and column selection signals (bit line selection signals) C _{1 to} C _m Then, it is a circuit for designating the address of the memory cell. Memory cell array 2
, The memory cells are arranged in a matrix (n rows and m columns), and the input data is held in the memory cells designated by the address buffer / decoder circuit 1. The memory cell is
As shown in FIG. 4, it is composed of a flip-flop circuit composed of two loads 41 and 42 and four MOS transistors T ₁₀ , T ₁₁ , T ₁₂ and T _{13. The} loads 41 and 42 may be resistors or gates. Is a p-channel MOS transistor connected to the gates of the drive transistors on the same side. The bit line pull-up circuit 3 is a circuit that determines the output level of the memory cell at the time of reading data, and the MOS transistors T ₁ , T ₂
(The first column will be described here.),
Its source is connected to the high potential power supply V _CC , its drain is connected to each bit line pair, and its gate is connected to the low potential power supply V _EE . The write control circuit 4 is a circuit that selects a bit line row and writes input data to a memory cell, and is composed of a transfer gate of a MOS transistor. The MOS transistors T ₃ and T ₄ are transistor gates, and the drains of the MOS transistors T ₃ and T ₄ are
Each of them is connected to a bit line pair, its source is connected to a data input pair Din, ▲ ▼, and each gate receives a write control signal WE _{1 which} is an AND logic of a column select signal and an external write control signal. It The bit line signal level shift circuit 5 and the data line pull-up circuit 6 are circuits that shift the level of the bit line signal in order to operate the sense amplifier circuit 8 in the subsequent stage at high speed when reading data. The bit line signal level shift circuit 5 includes a MOS transistor T
_5, is composed of T _6, T _7, the drain of the MOS transistor T _5, T ₆ are respectively connected to the data line pair, MOS transistors T
The gates of ₅ and T ₆ are connected to bit line pairs, and
The sources of the transistors T ₅ and T ₆ are connected to the drain of the MOS transistor T ₇ . Further, the source of the MOS transistor T ₇ is connected to the low potential power supply V _EE , and the column selection signal C ₁ is input to its gate. The data line pull-up circuit 6 is composed of MOS transistors T ₈ and T ₉ , each source is connected to the high potential power supply V _CC , and each drain is a data line pair D,
And each gate is connected to a low potential power supply V _EE . The data input circuit 7 is a circuit for converting the external data input D _IN at the ECL level into the internal data input D in, ▲ ▼ at the MOS level.

[Problems to be solved by the invention]

As described above, since the conventional SRAM is configured by using MOS transistors, (1) an input data signal of a small amplitude is amplified to a large amplitude by a data input circuit to be a memory cell when writing data. Since the writing is performed, the delay time increases as much as the amplitude is amplified.

(2) Since the transfer gate is used in the write control circuit, the delay time increases depending on the load capacitance of the bit line.

At the time of reading data, (3) the signal level of the bit line is level-shifted by the differential amplifier circuit composed of MOS transistors, so that the delay time increases depending on the load capacitance of the data line.

There were drawbacks such as.

[Means for solving problems]

According to the present invention, in order to eliminate the conventional drawback, each column of the memory circuit is pulled up by a first power source when a column is selected and a bit line is driven by a second power source when a column is not selected. Memory cell, level conversion circuit for level shifting the bit line signal when reading data, read accelerating circuit for level shifting the low level of the bit line signal to the second power supply level when reading data, memory cell by current switching of the bit line And a data input circuit for converting an external data signal into a complementary signal and performing a level shift.

[Work]

According to the present invention, a bipolar transistor is used in the data input circuit, the write control circuit, and the bit line signal level conversion circuit, and writing and reading to and from the memory cell are performed with a small amplitude signal, thereby further driving a large load capacitance. A high-speed static RAM can be constructed by using a bipolar transistor having a large current driving capability in the circuit. This will be described below with reference to the drawings.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which 10 is a bit line pull-up circuit, 11 is a bit line level conversion circuit, 12 is a read acceleration circuit, 13 is a write control circuit, and 14 is a data input circuit. Here, the first column will be described. The bit line pull-up circuit 10 includes MOS transistors T ₁₄ , T ₁₅ , T ₁₆ , T ₁₇
The sources of the MOS transistors T ₁₆ and T ₁₇ are the first
Is connected to the power supply V _C1 (−0.8V) of the MOS transistor T ₁₆ ,
The drain of T ₁₇ is a bit line pair and MOS transistors T ₁₄ , T ₁₅
Connected to the drain of. Also, the MOS transistor T
The sources of ₁₄ and T ₁₅ are connected to the second power supply V _E1 (1.6 V). The column selection signal C ₁ is input to the gates of the MOS transistors T ₁₄ , T ₁₅ , T ₁₆ , T ₁₇ . Level converting circuit 11 of the bit line signal is composed of bipolar transistors Q _1, Q _2, the collector of the bipolar transistor Q _1, Q ₂ are connected to a third power supply V _CC (0V), the base bit line pairs BL, ▲
And the emitter is connected to the data line pair D ,. Reading acceleration circuit 12 is constituted by a bipolar transistor Q _3, Q _4, the collector of the bipolar transistor Q _3, Q ₄ is connected to a third power supply V _CC (0V), the inverted logic of the external write signal to the base The internal read signal RE is input to each emitter, and the bit line pair BL, ▲ ▼ is connected to each emitter. The write control circuit 13 is composed of bipolar transistors Q ₅ and Q ₆ , and is composed of bipolar transistors Q ₅ and Q _6.
The collector of is connected to the bit line pair BL, ▲ ▼, the write signal WE _{1 which} is the AND logic of the column selection signal and the external write signal is input to the base, and the emitter is connected to the data line pair Di.
It is connected to n, ▲ ▼. The data input circuit 14 is
A circuit for converting an external data input D _IN into a complementary signal and level-shifting the signal to generate an internal data input D in, ▲ ▼, which is composed of a complementary signal generating circuit 15 and a level shift circuit. Is a series connection of a bipolar transistor Q ₇ , a series connection of diodes D _{1 to} D ₄ , a resistor R ₃ , and a series connection of a bipolar transistor Q ₈ , a series connection of diodes D _{5 to} D ₈ and a resistor R _4. Composed. The collectors of the bipolar transistors Q ₇ and Q ₈ are the third power source V
Connected to _CC (0V), resistors R ₃ and R ₄ are connected to the fourth power source V _EE (−5.
2V) is connected.

FIG. 2 shows a second embodiment of the pull-up circuit. In order to prevent the saturation of the bipolar transistors Q ₅ and Q ₆ of the write control circuit 13, diodes D _{9 to} D ₁₂ are provided in parallel with the MOS transistors T ₂₀ and T _21. , D _{13 to} D ₁₆ are connected to each other.

 The operation of the present invention will be described with reference to FIG.

 The operation of the first column will be described below.

 First, the write operation will be described.

When the address of the memory cell to write data is determined by the address buffer / decoder circuit 1, the write control circuit
By the write signal WE ₁ (about D _in level) input to 13,
The base voltage of the bipolar transistors Q ₅ and Q ₆ rises. At this time, the base voltage and the emitter voltage of the bipolar transistors Q ₅ and Q ₆ (internal data input Din, ▲ ▼)
Since the potential difference of either one of them becomes higher than the built-in voltage of the bipolar transistor,
One of Q ₅ and Q ₆ becomes conductive to generate a large amplitude signal (high level 0 V, low level about WE ₁ level) on the bit line, and writing to the memory cell becomes possible.

 Next, the read operation will be described.

When the address of the memory cell from which data is read is determined by the address buffer / decoder circuit 1, the read acceleration circuit
Since the read signal RE (-0.8V) is input to 12, the bit line signal level rises to -1.6V. Further, since the column selection signal C ₁ is input to the bit line pull-up circuit 10, the MOS
The pull-up operation by the transistors T ₁₆ and T ₁₇ is started,
Since a current flows through the bit line to the low potential power source of the selected cell, a high level small amplitude signal (high level −0.8V, low level −1.6V or higher) is generated in the bit line. The small-amplitude signal generated on the bit line is level-shifted by the built-in voltage of the bipolar transistors Q ₁ and Q ₂ by the level conversion circuit 11 that shifts the level of the bit line and the resistors R ₁ and R ₂ , and the signal is transferred to the data line. appear. The small amplitude signal generated on the data line is applied to the sense amplifier circuit 8 and the ECL output circuit 9
Through, the ECL level is generated.

At this time, the bit line of the memory cell in the non-selected column is fixed at -1.6V by the bit line pull-up circuit 10, so that only the information of the selected memory cell appears on the data line.

As described above, the SRAM of the present invention enables writing to a memory cell only by level shifting without converting a small-amplitude external data input (ECL level) into a large-amplitude (MOS level) internal data input. Therefore, the input data can be written at high speed. Further, since the bit line and the data line, which increase the load capacitance, are driven by the bipolar transistor, the speed can be increased as compared with the MOS transistor.

〔The invention's effect〕

As described above, in the SRAM of the present invention, an external data signal having a small amplitude (ELC level) can be written to the memory as an input signal having a small amplitude without being amplified to a large amplitude (MOS level). The write operation can be speeded up. Further, since the bit line and the data line having a large load capacitance are driven by the bipolar transistor, there is an advantage that the speed can be increased as compared with the conventional MOS transistor.

[Brief description of drawings]

FIG. 1 shows an embodiment of a MOS SRAM according to the present invention, FIG. 2 shows a second embodiment of a pull-up circuit according to the present invention, FIG. 3 shows a conventional MOS SRAM, and FIG. 4 shows the memory cell type shown in FIG. It is shown. 1: Address buffer / decoder circuit 2: Memory cell array 3: Pull-up circuit (1) 4: Write control circuit (1) 5: Bit line level shift circuit (1) 6: Data line drive circuit (1) 7: Data Input circuit (1) 8: Sense amplifier 9: Output buffer circuit 10: Bit line pull-up circuit (2) 11: Bit line level conversion circuit (2) 12: Read acceleration circuit 13: Write control circuit (2) 14: Data Input circuit (2) 15: Complementary signal generation circuit 16: Pull-up circuit (3) 41,42 Load T _{1 to} T ₂₁ : MOS transistors Q _{1 to} Q ₈ : Bipolar transistors D _{1 to} D ₁₆ : Diodes R _{1 to} R ₄ : Resistor V _CC : 3rd power supply (0V) V _EE : 4th power supply (-5.2V) V _C1 : 1st power supply (-0.8V) V _E1 : 2nd power supply (-1.6V) C _i (i = 1, m): the column selection signal _{WE i (i = 1, m} ): write signal RE: read signals A ₁ to A _K: address input signal D _IN: external data input signal D _in, ▲ ▼: internal data input signals WL ₁ to WL _K: row selection signal BL, ▲ ▼: bit line pair D ,: data line pairs V _SO: a sense amplifier output V _OUT: ECL Output

Claims (4)

(57) [Claims] 1. A memory circuit for writing and reading random data into and from memory cells arranged in a matrix, wherein each column of the memory circuit drives a bit line by a first power source when the column is selected. Then, a bit line pull-up circuit that drives the bit line by the second power source when the column is not selected, a plurality of memory cells arranged in the matrix, and shifts the level of the bit line signal when reading the data. A bit line level conversion circuit; a read accelerating circuit that raises the low level of the bit line signal to the second power supply level when the data is read; and a bit line current when writing data to the memory cell. A write control circuit that switches the current with a large-amplitude signal, and an external data input signal are converted to complementary signals and level-shifted to generate internal data input complementary signals. And a bit line pull-up circuit including first, second, third, and fourth field effect transistors. The source of the effect transistor is connected to a first power supply, the drains of the first and second field effect transistors are connected to the drains of the third and fourth field effect transistors, respectively, and a bit line pair, A source of the fourth field effect transistor is connected to the second power source, and a column selection signal is input to the gates of the first, second, third and fourth field effect transistors, and the bit line Of the first level converter circuit is composed of first and second bipolar transistors, the collectors of the first and second bipolar transistors are connected to a third power supply, and the first and second bipolar transistors are connected. A base connected to the bit line pair of static, first, a memory circuit, characterized in that formed by connecting the emitter of the second bipolar transistor to the data line pair. 2. The read acceleration circuit is composed of third and fourth bipolar transistors, the collectors of the third and fourth bipolar transistors are connected to the third power supply, and the third and fourth bipolar transistors are connected. A read signal having a high level as the second power supply level is input to the base of the bipolar transistor, and the emitters of the third and fourth bipolar transistors are connected to a bit line pair. 2. A memory circuit according to claim 1. 3. The write control circuit is composed of fifth and sixth bipolar transistors, the collectors of the fifth and sixth bipolar transistors are connected to a bit line pair, and the fifth and sixth bipolar transistors are connected. 2. The memory circuit according to claim 1, wherein a write signal is input to the base of the transistor, and a data input pair is connected to the emitters of the fifth and sixth bipolar transistors, respectively. 4. A memory circuit according to any one of claims 1 to 3, wherein a diode string is connected in parallel with each of the third and fourth field effect transistors in the bit line pull-up circuit. .