JP2532447Y2 - Memory backup device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention is applied to various types of electronic devices with exchangeable batteries, and relates to a memory backup device that protects the contents of a memory unit in the device when the batteries are exchanged.

(Prior art)

FIG. 12 shows an example of a conventional memory backup circuit. In the figure, a main circuit 1 including a CPU and the like, and a RAM 2 from which data is read and written based on an instruction from the main circuit 1 are normally supplied with a voltage supplied from a battery 3 of 1.5 V, for example. Being driven. On the other hand, RAM2
, A backup capacitor 4 is connected in parallel, and a backflow preventing diode 5 is connected between the capacitor 4 and the battery 3. The capacitor 4 is normally charged by the battery 3 during normal operation. However, when the battery 3 is replaced, a discharge voltage is supplied to the RAM 2 so that the RA 4
The contents of M2 can be prevented from being erased for a certain period of time.

Further, as another example, for example, a battery of 3 V is used, and the battery voltage is reduced to about 1.5 V and supplied to the main circuit or the RAM, and the capacitor is charged with the reduced voltage. The compensation is made by discharging the capacitor when the battery is replaced.

[Problems of the prior art]

In the above conventional backup method, since the battery voltage is greatly reduced, the charging voltage of the capacitor is extremely low in any of the above cases (for example, 1.2 V).
degree). Therefore, the time that can be compensated for by the charging voltage of the capacitor at the time of battery replacement becomes extremely short, and if the compensation time is to be lengthened, a large-capacity capacitor must be used.

In addition, in the above-described conventional method, there is a disadvantage that the use is continued even though the battery voltage is lowered, and the power consumption is further increased. In such a case, in the past, the battery voltage has been lowered by notifying by a display or the like and prompting the user to replace the battery. However, the user is notified that the voltage drop has been notified but is still operating. As a result, the battery replacement was delayed, and in many cases, the result was that the battery was not replaced until the voltage could not protect the memory.

[Purpose of the invention]

In view of the above-mentioned conventional problems, the present invention can provide a long compensation time without using a large-capacity backup capacitor, and inform that a device can be replaced with a new one. It is an object of the present invention to provide a backup device that can be used.

[Points of the invention]

In order to achieve the above object, the present invention provides a device in which a battery voltage is normally reduced to drive a memory unit and other circuits. A switch that is turned on when a predetermined member is moved to turn off the battery when the predetermined member is returned to its original position after battery replacement is provided. Once the battery is charged, the memory voltage is backed up with the discharge voltage, and the battery is ready to be replaced. The main point is that the notification is stopped when the battery is returned to the position and the switch is turned off, that is, when the battery cannot be replaced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an overall circuit diagram of an electronic wristwatch with a data bank function to which an embodiment of the present invention is applied. First, the configuration and operation of this embodiment will be schematically described with reference to FIG.

In FIG. 1, a replaceable 3V battery (for example, a lithium battery) 11, a step-down circuit (for example, a voltage harbor) 12 for stepping down this battery voltage by half, and receiving this step-down voltage as a power source section, A constant voltage circuit 13 that outputs a voltage (here, −1.25 V), a voltage detection circuit 14 that detects a decrease in battery voltage, and the like are provided. The positive side of the battery 11 is grounded, and this ground level V ₀ (= 0)
And the voltage level on the negative side (that is, the battery voltage) is V ₂ (= −3 V). In addition, the constant voltage circuit 13
Is a constant output voltage level of V ₁ (= −1.25 V).

The voltage V ₁ of the above, the main circuit unit 15 is driven. The main circuit unit 15 is a clock circuit internally including a ROM, a small-capacity RAM, and the like, and has a clock function for counting and displaying time, a computer function alarm function and a step watch function, and further described below. It also has a function of reading and displaying various data (for example, telephone number data and the like) stored in the memory unit 16 to be displayed. The main circuit section 15 is connected in parallel a capacitor C ₀ of the small capacity, if there is a momentary fluctuations and interruptions other by the power supply oscillation, the operation of the main circuit section 15 at a discharge voltage of the capacitor C ₀ Can be compensated for. The specific circuit configuration and operation of the main circuit section 15 will be described later in detail with reference to FIG.

The memory unit 16 has a large capacity for storing various data.
FIG. 2 shows a schematic configuration of the RAM. As shown in the figure, the memory unit 16 includes an item data storage area Xa capable of storing item data such as names and characters for six characters,
Numerical data storage area Xb capable of storing 12 digits of numeric data such as telephone numbers corresponding thereto is provided with, for example, 50 registers X (X ₀ , X ₁ , X ₂ …) and a main circuit at the time of battery replacement. A register Y for temporarily storing data (for example, the number of registers X used) transferred from the unit 15
(Y ₀ , Y ₁ , Y ₂ …). Returning to FIG. 1, the memory unit
The 16, capacitor C ₁ for backup during battery replacement are connected in parallel, the capacitor C ₁ at the time of battery exchange
The contents of the memory section 16 can be compensated for by the discharge voltage.

The voltage control unit 17 includes a voltage Vx supplied to the memory unit 16.
By controlling the a control circuit for protecting the contents of the memory unit 16 together with the capacitor C _1. That is, the voltage control unit 17
Switches between the voltages V ₁ and V ₂ in accordance with the opening and closing of a switch S ₁ described later and the signals a and AC output from the main circuit unit 15, and supplies these to the memory unit 16 as Vx. Also, a chip enable signal CE ₂ that enables the memory unit 16 to operate,
By controlling the read-write signal R ₂ to the memory unit 16 is given at the time of reading and writing data, supplied to the memory unit 16 signals CET, as RT respectively. The specific configuration and operation of the voltage control unit 17 will be described later with reference to FIGS. 5 and 6.

FIG. 1 shows a switch which is turned on when the battery is replaced.
S ₁ , an AC switch S ₂ for initializing each unit (for example, clearing the memory unit 16) or starting operation of the main circuit unit 15 after battery replacement, and data of various functions for the main circuit unit 15, for example. , calculation of the function or numeric, the stopwatch start, stop, or enter data such as the clear, or the operation switch group S ₃ to give a control command is shown. Among these, it is described below based on a specific configuration of the switches S ₁ and S ₂ in FIGS. 10 and 11. Here, FIG. 10 is an enlarged sectional view of the electronic wristwatch to which the present embodiment is applied, and FIGS.
Is an enlarged sectional view of the switch S ₁ in FIG. First, in FIG. 10, a watch glass 22 is mounted on an upper surface of a watch case 21, a watch module 23 is housed inside, and a back cover 24 is mounted on a lower portion.
The timepiece module 23 includes a circuit board 27 on which an LSI (not shown) having various circuits shown in FIG. 1 is mounted between an upper housing 25 and a lower part 26, and which is above the circuit board 27. In this configuration, a display drive signal is supplied to the liquid crystal display panel 28 via an interconnector 28a. While the upper and lower housings 25 and 26 are fixed to each other via a circuit board 27 by a ground plate 29 made of a thin metal plate, the upper and lower housings 25 and 26 are inserted into the watch case 21 via a holding ring 30 separate from the back cover 24. It is installed. Although not shown in FIG. 10, the lower housing of the watch module 23 is not shown.
The battery 11 shown in FIG. 1 is housed in 26, and its plus side is connected to the main plate 29. That is, the ground plane
The voltage level of 29 is V ₀ (ground level).

Now, the switch S ₁ shown in Figure 1 of this embodiment is provided in the lower right corner of the watch module 23 as shown in FIG. 10, the
As shown in FIGS. 11 (a) and (b), it is configured to turn on and off in accordance with opening and closing of the restraining ring 30 at the time of battery replacement. That is, as shown in FIG. 11, first, a stepped through hole 26a is formed in the lower housing 26,
A coil spring 31 having conductivity is arranged therein. The coil spring 31 has a free end 31a formed in a spiral shape larger than the fixed end 31b, the free end 31a is disposed on the large diameter side of the through hole 26a, and the fixed end 31b is disposed on the small diameter side of the through hole 26a. And the fixed end 31b is connected to the circuit board 27.
(The input terminal to the voltage control unit 17 in FIG. 1). A free end 31a of the coil spring 31 is provided with a terminal plate 32 made of a substantially thin disk-shaped conductive metal plate.
While being moved up and down on the large diameter side of the through hole 26a. A contact portion 32a is bent at the periphery of the terminal plate 32 so as to slightly protrude downward therefrom, so that the contact portion 32a comes into contact with the ground plate 29 when the terminal plate 32 moves downward. Has become. Further, a peripheral edge of the terminal plate 32 opposite to the contact portion 32a is extended upward relatively long therefrom, and is hooked outward such that its tip is located above the step 26b in the lower housing 26. When the main plate 29 is removed, the terminal plate 32 and the coil spring 31 are externally locked by locking the position restricting portion 32 to the stepped portion 26b. It is designed to prevent jumping out. Also, a circular hole 29a is formed in the base plate 29 corresponding to the coil spring 31, and a pressing portion 30a is provided on the inner surface of the pressing ring 30 at a position where it can be inserted into the hole 29a. ing.

Switch S ₁ having the above configuration, in a normal state where the battery 11 is ring 30 suppresses housed in a lower housing 26 is attached, the pressing portion of the presser ring 30 as shown in FIG. 11 (a)
30a protrudes inside through the hole 29a of the base plate 29 and presses the terminal plate 32 against the coil spring 31, so that the contact portion of the terminal plate 32
32a (corresponding to the terminal S ₁ b in FIG. ₁ ) is the ground plate 29 (the terminal in FIG. 1).
Spaced apart from the corresponding) to S ₁ a, thus it turned off. On the other hand, if you remove the retaining ring 30 for battery replacement,
As shown in FIG. 11 (b), the terminal plate is
Since the portion 32 is urged downward, the contact portion 32a comes into contact with the main plate 29 and is turned on.

Further, another switch S ₂ is also provided in the lower housing 26 as shown in Figure 10. That is, a through hole 26c is formed in a part of the lower housing 26,
The main circuit part shown in FIG.
An electrode terminal 27a which is an input terminal to the base plate 15 is provided, and a small-diameter hole 2 is provided at a position corresponding to the through hole 26c of the base plate 29.
9b is formed. Further, a hole 30b is formed at a position of the holding ring 30 corresponding to the through hole 26c.
AC switch S ₂ thus configured, the electrode 27a (first
The terminal S ₂ b in the figure and the ground plate 29 (corresponding to the terminal S ₂ a in FIG. 1) are turned on by conducting with a jig or the like (not shown). In other cases, the terminal is turned off.

Next, a specific circuit configuration and operation of the main circuit section 15 will be described with reference to FIG.

The ROM 41 is a fixed memory containing microprograms and data for controlling each function, and includes an address signal A, various data D, an instruction signal I for specifying a program, and a next for specifying the next address. An address signal N is output. The ROM control unit 42 receives the next address signal N from the ROM I, the output of the arithmetic circuit 45, the output of the instruction decoder 44,
The ROM 41 is controlled based on the output of the voltage detection circuit 14 (FIG. 1). The RAM 43 has a smaller capacity than the memory section 16 shown in FIG. 1, and is a memory for storing data that is frequently accessed for reading / writing based on the address signal A of the ROM 41. The RAM 43 is, for example, as shown in FIG.
Display register D for storing display data, time register T for storing time data, alarm time register A for storing alarm time data, stopwatch register S for storing stopwatch data, and other various registers n, i, P ₀ , and a P ₁ and various flags _{M, F 0, F 1,} F 2 and the like. Here, the number of data registers P ₀ is stored in the memory unit 16 (i.e., the second register using the number of X shown in the figure) stores the register P ₁ is the data that is of them currently specified Store the address.

The instruction decoder 44 is a block that decodes the instruction signal I in the ROM 41 and sends a control signal to each block. Arithmetic circuit (ALU) 45 is R
Performs an arithmetic and logic operation on the data sent from the OM 41, the RAM 43, the memory unit 16 and the like, and stores the operation result in the memory unit 16, the RAM 4
3. Send to ROM control unit 42, etc.

The oscillator 46 generates a clock signal having a constant period and outputs the clock signal to the timing generator 47 and the frequency dividing circuit 48. The timing generator 47 divides the frequency of the clock signal to a predetermined frequency, and outputs a timing signal for controlling each block and the voltage detection circuit 14 in time series. In particular, RAM4
3 outputs a chip enable signal CE ₁ and a read / write signal R _1, and outputs a voltage control unit 17 to a memory unit 16.
And outputs a signal a for the chip enable signal CE ₂ and the read-write signal R ₂ and described below voltage switching for. The frequency dividing circuit 48 is a counter that divides the frequency of the clock signal from the oscillator 46, and generates a clock signal with a constant cycle used for clock processing and the like. The key input unit 49 includes a switch S ₁ to S ₃ shown in FIG. 1, various functions are performed on the basis of these key operations. When the AC switch S ₂ (see FIG. 10) is operated, the signal AC is output, and the signal AC starts the oscillation of the oscillator 46 or initializes each part. Or be done.
The signal AC is also sent to the voltage control unit 17.

The liquid crystal display device 50 includes the liquid crystal display panel 28 shown in FIG.
And displays data (for example, normal time data, stopwatch data, or telephone number data transmitted from the memory unit 16) stored in the display register D of the RAM 43 under the control of the display control unit 51. . A specific display example will be described later with reference to FIG.

Next, a specific configuration and operation of the voltage control unit 17 will be described with reference to FIGS. In FIG.
In addition to the voltage control unit 17 surrounded by a dashed line, a memory unit 16 composed of a large-capacity RAM, and a capacitor for backup
C ₁ and the same switch S ₁ shown in FIGS. ₁ and 11 are shown. FIG. 6 shows the signal and voltage waveforms of each part in FIG.

First, in the normal (when other than replacing the battery), the switch S ₁ as shown FIG. 11 (a) is in the off state. In this case, one input of the NOR (NOR) circuit 61a in the latch circuit 61 becomes a low level (= V ₀ ). The output of the other latch circuit 62 is normally low level (= V ₁ > V ₂ ),
This V ₁ is switched to ensure low levels V ₂ by the level shifter 63, the other input of the NOR circuit 61a is also at the low level (= V _2). Therefore, the output of the NOR circuit 61a becomes high level, and accordingly, the output (signal c) of the NOR circuit 61b becomes low level. Note that the level shifter 63 and level shifters 64, 68, 69, and 71 described below are
Both are made of, for example, a CMOS inverter, and output as it is a high-level signal when the input signal is high level (= 0V), whereas, when the input signal is at the low level (= V ₁ or Vx) is than This is a circuit that surely shifts the level to a low level (= V ₂ ) and outputs it.

When the signal c has a low level, the output (signal d) of the inverter circuit 61c goes high and the output (signal e) of the level shifter 64 goes low (= V ₂ ). Therefore, since the transistor 65 is on and the transistor 66 is off (at this time, the transistor 67 is also off), the voltage Vx supplied to the memory unit 16 is as shown in FIG. V ₁ is the output voltage of the constant voltage circuit 13 is selected and output. Also in this case,
One input signal c of the NOR circuit 61d in the latch circuit 61 has the same low level as that of the other input signal.
Chip enable signal CE ₂ from 15 (= V ₀ or V ₁ )
Is obtained through the level shifter 68 (= V ₀ or
V ₂ ). Thus from the NOR circuit 61d outputs an inverted signal of the chip enable signal CE ₂ is, which is given as an actual chip enable signal CET to the memory unit 16. Only when this chip enable signal is applied, the memory section 16 becomes operable. In addition, the main circuit 15
A signal (= V ₀ or V ₂ ) obtained from the read / write signal R ₂ via the level shifter 69 is supplied to the memory unit 16 as an actual read / write signal RT. When the read / write signal RT is at a high level, the main circuit 15
The data output signal O (O _{0 to} O ₃ ) can be read out based on the address signal A (A _{0 to} A ₁₁ ) from the memory, while the data input signal I (I _{0 to} O ₃ ) based on the address signal A at the low level. writing of I ₄₎ is possible.

Next, the time of battery replacement will be described with reference to FIG. First, when removing the battery, the back cover 24 shown in FIG. 10 is opened, and the holding ring 30 inside the back cover 24 is further opened.
Is removed. Then, as shown in FIG. 11 (b),
Switch S ₁ is switched to the ON state (FIG. 6 (a)). When the switch S ₁ is turned on, is stored mainly in the circuit section 15, trouble is erased among the data stored in the RAM43 data, i.e. the register P ₀ content (memory unit 16 shown in FIG. 4 number) and the content of the register P ₁ data (among the data stored in the memory unit 16, an address of data that is currently specified), etc., a register Y ₀ shown in FIG. 2 of the memory unit 16, Transfer to Y ₁ etc.

Incidentally, the NOR circuit 61a by the switch S ₁ is turned on
Becomes high level (= V ₀ ) and its output is switched to low level, but the signal b is still low level until the above-mentioned transfer is completed, and the output of the NOR circuit 61e becomes high level. Therefore, the output (signal c) of the NOR circuit 61b also remains at the low level. That is, the voltage Vx to be supplied to the memory unit 16 remains V ₁ is selected.

When the above data transfer is completed, the main circuit section 15 sets the input signal to the latch circuit 62 (that is, the input signal I ₂ to the memory section 16) to high level and sends it out, and also uses the signal a as a trigger to send the signal to the latch circuit 62. give. Thus the latch circuit 62 becomes an output captures the signal I ₂ is at a high level, thus the signal b is switched to the high level as shown in FIG. 6 (b). Then, since the output of the NOR circuit 61e becomes low level, both inputs of the NOR circuit 61b become low level, and the output (signal c) is switched to high level as shown in FIG. 6 (c). Be replaced.

When the signal c goes high, the main circuit 15
Regardless chip enable signal CE ₂ from the output of the NOR circuit 61d (the actual chip enable signal CET) sixth
As shown in FIG. 4D, the memory section is at a low level.
16 operations become impossible. In this case, the signal d output from the inverter circuit 61c goes low as shown in FIG. 6 (e), and the signal e output from the level shifter 64 becomes as shown in FIG. 6 (f). Since the level is high, the transistor 65 is turned off and the transistor 66 is turned on. As a result, the voltage Vx supplied to the memory unit 16
The, V ₂ is selected is the battery voltage. At this time, Vx
As shown in FIG. 6 (h), it changes from V ₁ to V ₂ along the charging curve of Kodensa C _1. At this time,
By diode 70 is connected between the C ₁ and the battery 11, reverse current is prevented. Note that the signal c is sent to the main circuit unit 15 via the level shifter 71 to reliably switch the low level (= Vx) to a low level (= V ₂ ).

From the above, at the time of battery exchange, prior to detaching the battery 11 (suppressed when opening the ring 30) switch S ₁ is being turned, with subsequent battery voltage V ₂ is supplied to the memory unit 16, the battery voltage V capacitor C ₁ is charged by _2. Note Before removing the battery 11, if to turn on the AC switch S ₂ shown in Fig. 10, even if you were event without not switch transistor 66 is turned on, connected in parallel to this it is possible to turn on the other one of the transistors 67 which are, it is possible to reliably supply the battery voltage V ₂ to the memory unit 16 and a capacitor C _1.

Thereafter, the battery 11 is moved from the lower housing 26 shown in FIG.
When these are removed, both the voltages V ₁ and V ₂ become zero as shown in FIG. In the meantime, as shown in Figure No. 6 (h), the discharge voltage of the capacitor C ₁ is supplied to the memory unit 16. At this time, the voltage charged initially in the capacitor C _1, because it is at least twice near the high voltage V ₂ voltage V _1, the time that can compensate for the memory unit 16 is very long in the discharge voltage. Note that when the battery 11 is removed, since the voltages V ₁ output is eliminated each part of the main circuit section 15 stops operation, the oscillator 46 stops oscillation shown in FIG. 3.

If fitted with new batteries to the lower housing 26, the battery voltage V ₂ is supplied to the memory unit 16 and the capacitor C _1, the electrical Vx is along the charge curve of the capacitor C ₁ as shown in Figure No. 6 (h) It rises to V ₂ Te. At this time, the operation of each unit of the main circuit unit 15 is still stopped. Therefore now made on the AC switch S ₂ as shown in FIG. 6 (g), the oscillator 46 shown in FIG. 3 starts oscillating, the processing with it (e.g., the FIG. 7 to be described later Process) starts.

Then, when attaching the ring 30 is suppressed over the new batteries, it switched to Hof state so that the switch S ₁ is was FIG. 11 (a). When the switch S ₁ is turned off after a certain rise time, the input signal from the main circuit section 15 to the latch circuit 62 (that is, the input signal I ₂ to the memory unit 16) is set to the low level, the signal a is triggered therewith It is provided to a latch circuit 62. As a result, the output of the latch circuit 62 becomes low level (= V ₁ ), so that the output (signal b) of the level shifter 63 surely becomes low level (= V) as shown in FIG.
V ₂ ). Then, since the two inputs of the NOR circuit 61a are both at the low level, the output is switched to the high level, and the output (signal c) of the NOR circuit 61b is also changed to the sixth level.
The state is switched to the low level as shown in FIG.

When the signal c goes low, the output (signal d) of the inverter circuit 61c goes high as shown in FIG. 6 (e), and the output (signal e) of the level shifter 64 goes high as shown in FIG. 6 (f). ), It becomes low level. Therefore, since the transistor 65 is turned on and the transistor 66 is turned off (the transistor 67 is also off unless there is a signal AC), the voltage Vx supplied to the memory unit 16 becomes as shown in FIG. off switched from V ₂ to V ₁ in. Further, the output of the NOR circuit 61d (signal CET), appear inverted level of the chip enable signal CE ₂ from the main circuit section 15 and if the chip enable signal CE ₂ at the low level, the signal C
ET goes high as shown in FIG. 6 (d), and the memory unit 16 becomes operable.

Thereafter, the data transferred from the RAM 43 to the register Y (see FIG. 2) of the memory unit 16 before the battery is removed is returned to the original register of the RAM 43. Then, after an error check and the like are performed on those data,
Normal operation is started. The details of the error check will be described later with reference to FIG. In the case where the AC switch S ₂ is turned on at the normal time, in addition to data stored in the memory unit 16 and RAM43 are all cleared, the initialization of each part is performed.

Next, the overall processing operation of the main circuit unit 15 shown in FIG. 3 will be described with reference to FIG. Incidentally, the flag F ₀ used in FIG. 7, F _1, F ₂ is the same as that shown in FIG. 4, F ₀ is a flag set to "1" when decrease in the battery voltage, F ₁ is "1" when the flag switch S ₁ is to be to have been turned off (i.e. presser ring 30 is opened) during "1", F ₂ is the switch S ₃ key is a no function during battery replacement This is a flag. These flags are
By AC switch S ₂ is turned on, all become "0".

First, in step T _1, for example clock function, calculator function, alarm function relates various functions such as stopwatch function, and data bank function performs normal timer processing and key processing. However, if the flag F ₂ is 1, the above-described key processing is not performed, the data input of each function, control input is not performed. Thereafter, the battery voltage (V _2), it is determined whether the lower than the predetermined level in step T _2, the process proceeds to step T ₃ if the decreased if inform a decrease in the battery voltage by where for example, a display or the like , at the same put the 1 to the flag F ₀ at the same time. The determination of the battery voltage is made based on the output of the voltage detection circuit 14 shown in FIG.

In step T ₄ is followed, whether the switch S ₁ is in the on state (i.e., presser ring shown in FIG. 10 30
A look at whether or not) has been opened, if the switch S ₁ is turned on, see if F ₁ = 0 in step T _5. When the switch S ₁ is on and F ₁ = 0, the state is immediately after the holding ring 30 is opened for battery replacement.
Step T ₆ flag F ₂ whether 1 (i.e., the key is whether it is a no function) watches, F ₂
= The key to no function by 1 unless you add 1 to F ₂ in step T _7. If it is the F ₂ = 1, it is not performed the processing of step T _1, as described above. Proceeding to step T _6, data is transferred to the memory unit 16 from the RAM43 described above, after the completion of step T ₉
Then, the signal a is sent to the voltage controller 17 as a backup process (see FIGS. 5 and 6B). With this signal a,
Supply voltage Vx to the memory unit 16 is switched from V ₁ to V ₂ (FIG. 6 (g) refer) allows backup due to the capacitor C _1.

On the other hand, in step T _4, when the switch S ₁ is in the off state to see if the flag F ₁ = 0 in step T _10. If switch S ₁ is off and F ₁ = 0,
Since battery replacement is a state immediately after the ring 30 restrained ends closed, at step T _11, the memory unit 1 described above
It performed 6 from the data transfer to the RAM43 (the process to restore the data transferred in Step T _8). Then, the process proceeds to step T _12, performs error detection on the data in which the transfer data and memory unit 16. This processing will be described later with reference to FIG. If any errors are found,
Clear all data in step T _15, and by performing the initialization of each part (initialization), to allow for normal processing thereafter.

Further, unless F ₁ = 0 in step T _10, already finished battery replacement (or no battery replacement is still performed), it is a state in which normal processing is continued, the step T After setting ₁ to the flag F1 in step ₁₃ ,
View the presence or absence of the operation of the AC switch S ₂ at _14. When AC switch S ₂ is operated to clear all the data in step T _15, and performs various initialization of.

Will now be described with reference to FIG. 8 error detection process in step T _12.

First, in step U _1, the range of number number data transferred in step T ₁₁ is predetermined (i.e., the maximum number that can be stored in a register X of the memory unit 16 shown in FIG. 2, for example, 50 pieces) Check if it is within the range, and if it is not within this range, it is regarded as “error”. If the number data is within the predetermined number, the register n in Step U ₂
Put 1 in.

Therefore, next, to see if the content of n is less than the above number data in step U _3, add 1 to the register i proceeds to step U ₄ equal to or less than the number data. In step U _5, "A" to the i-th character of the item data included in the n-th data stored in the memory unit 16 letter "Z" and "-" either with (hyphen) Check if there is, and if it is not in this range, it will be regarded as "error". If the range above i-th character of the, 1 is added to the register i in step U _6. And i in step U ₇
A look at whether or not the content is less than 6, which is the maximum number of characters of the item data, the flow returns to step U ₅ if i is still less than or equal to 6.
That is, unless there is an error, a check of step U ₅ for all the characters in item data.

If a i> 6 in step U _7, Step U ₈
And enter 1 in i. Then, in step U _9, seeing whether i-th digit of the numeric data included in the n-th data is either "0" to "9" and "-" (hyphen), this range If there is no error, an "error" is assumed. If the range above i-th digit of said adds 1 to i in step U _10. Then, in step U _11, the contents of i to see whether or not the 12 or less is the maximum number of characters of numeric data,
If i is still 12 or less returns to step U _9. That is,
Unless an error, for all the digit in the data checking in step U _9.

If a i> 12 in step U _11, Step U
After adding 1 to n at _12, n returns to Step U ₃ see whether it is less than the number data. If n is less than the number data, newly by performing the processing of step U ₄ ~U ₁₂ for the n-th data, the error check. In this way, when error checking is completed for all data, such as the number of data,
When n exceeds the number data in U _3, and ends the error detection process.

However, the processing shown in FIGS. 7 and 8 after insertion of the battery so as not to start not to turn on the AC switch S _2. If you turn on the AC switch S _2, the flag F ₀ described above, F _1, F ₂ and register n, the i like 0 is entered.

Although not shown in FIG. 7, a display process is performed at the end of the flow. In this process, the display register D (see FIG. 4) of the RAM 43 is changed by the display control unit 51 in FIG. Is a process for displaying the information. FIG. 9 shows an example of the display. A ninth example is shown. FIG. 7A shows an example of a normal time display. In this example, the current time is "1986
Monday, December 29, 10:58:50 pm ". FIG. 2B shows an example of a data bank display. Item data (contents of the register Xa in FIG. 2) of six characters including names and characters are displayed in an upper display area, and a lower display is shown. In the area, numeric data of 12 characters (contents of the register Xb in FIG. 2) including a telephone number or the like corresponding to the item data are displayed. In the example of FIG.
This indicates that the telephone number of “SIO” is “0425-55-7211”. Further, when the drop in battery voltage is detected to the ninth regular time displayed as shown in Figure (a) (i.e. when one is put into F ₀ in step T ₃ above), for example the "Bat." Is displayed as shown in FIG. 9 (c), so that the user can know that the battery voltage has dropped. Open the back cover 24 to replace the battery, and then
The case was opened (i.e. when the switch S ₁ is in the ON state), for example, as shown in FIG. 9 (d) is "OPEN" is displayed, thereby, is a no function even if operating the key It is informed. Immediately after the battery replacement is completed and the holding ring 30 and the back cover 24 are closed,
₁₂ (U _{1 to} U ₁₂ ), an error is detected. During this error detection, for example, as shown in FIG.
“K” is displayed.

As described above, in this embodiment, when the battery is changed, by switching S ₁ is being turned prior to removal of the battery, the supply voltage is normal constant operating voltage V to the memory unit 16
₁ (for example, V ₁ = 1.25 V) and is switched to a battery voltage V ₂ (for example, V ₂ = 3 V) which is twice as large as that, and the charging voltage of the backup capacitor C ₁ is also changed to the battery voltage V _2.
Rise to a level equal to Therefore, the time that can compensate for the memory section 16 at a discharge voltage of the capacitor C _1, the capacitor
Without using the C ₁ large-capacity ones, considerably longer than conventional. Further, the fact that this operation has been performed is displayed on the display, and it is possible to inform that the key has become a no function.

Although the above embodiment is applied to an electronic wristwatch with a data bank function, the present invention is not limited to such an electronic timepiece, and various electronic devices having various memory units that need to be backed up when replacing a battery. For example, the present invention can be applied to a small electronic calculator, an electronic organizer, an electronic scheduler, an electronic camera, a word processor, and the like.

[Effect of the invention]

The backup device according to the present invention can obtain a long compensation time without using a large-capacity backup capacitor, and when a predetermined member is moved before replacing the battery, the battery voltage of the capacitor is reduced. , The memory unit can be reliably backed up when replacing the battery. In addition, when a predetermined member is moved, the battery can be replaced, and when the backup is started, the fact is notified, so that the user is prompted to remove and attach the battery itself, If the battery can be replaced by mistake, the fact can be reliably notified.

[Brief description of the drawings]

1 is an overall circuit diagram of an electronic wristwatch with a data bank function to which one embodiment of the present invention is applied, FIG. 2 is a schematic configuration diagram of a memory unit 16 in FIG. 1, and FIG. FIG. 4 is a schematic configuration diagram of the RAM 43 in FIG. 3, FIG. 5 is a detailed circuit diagram of the voltage controller 17 and its vicinity in FIG. 1, FIG. FIG timing chart for explaining the main operations of the voltage control unit 17, the flow chart FIG. 7 is showing the overall processing operation of the main circuit unit 15, FIG. 8 is the processing of step T ₁₂ in FIG. 7 ( 9 (a) to 9 (e) are diagrams showing examples of display by the liquid crystal display device in FIG. 3, and FIG. 10 is a diagram showing an example in which an embodiment of the present invention is applied. enlarged sectional view of the electronic wrist watch, FIG. 11 (a) and (b) are turned off and on of the switch S ₁ in FIG. 10 Enlarged sectional view of state, FIG. 12 is a circuit diagram showing an example of a conventional battery backup circuit. 11… Battery, 12… Step-down circuit, 13… Constant voltage circuit, 14…
... voltage detection circuit, 15 ... main circuit section, 16 ... memory section, 17
…… Voltage controller, C ₁ …… Capacitor for backup,
S ₁ …… Switch, S ₂ …… AC switch

Claims (1)

(57) [Scope of request for utility model registration] A step-down unit for stepping down a battery voltage supplied from a convertible battery; a memory unit driven by the step-down voltage of the step-down unit; a capacitor connected in parallel to the memory unit; A switch that is turned on when a predetermined member is moved to make it replaceable, and that is turned off when the predetermined member is returned to its original position after battery replacement; and when this switch is turned on, A backup unit that supplies the battery voltage to the memory unit and the capacitor in place of the step-down voltage to protect the contents of the memory unit; a notification unit that starts notification when the switch is turned on; Means for stopping the operation of the backup means and stopping the notification of the notification means when is turned off. Backup device.