JP2531188B2 - Buffer memory - Google Patents

Description

TECHNICAL FIELD The present invention relates to a so-called first-in first-out buffer memory.

[Outline of Invention]

The present invention relates to a buffer memory, in which two systems of shift registers for flags are provided so that the data transferred in block transfer can be properly buffered.

[Conventional technology]

For example, when performing data transfer between two circuits (processors), a buffer memory of a first-in first-out (FIFO) type is used to facilitate this transfer ("Transistor Technology", March 1984, P324- (See P326, etc.).

That is, FIG. 2 schematically shows the above-mentioned FIFO type buffer memory, which is provided with a memory (1) of a predetermined number of stages (L) corresponding to the number of bits (M) of the data word to be transferred, and at the same time, of the L stages. A shift register (2) is provided.

The data word from a circuit on the transmission side (not shown) is supplied to the data input terminal DI ₁ -DI _M drawings left, supplied data word to the terminal DI ₁ -DI _M includes a memory (1) Writing is performed sequentially from the output end side (right side in the drawing), and read clock from the receiving side circuit (not shown).
SO is supplied, Ru and data word stage of the output end side is written sequentially shifted data word to an output end side to each stage of the further memory are outputted to the data output terminal DO ₁ ~DO _{M (1)} It

Is outputted to the output terminal DO ₁ to DO _M without changing the I connexion input terminal DI ₁ -DI _M-sequence time data words supplied to thereto, during which time the memory number of stages of the time axis (1) Modification is allowed, and data can be transferred according to the states of the transmitting side circuit and the receiving side circuit.

In addition, the shift register (2) has a master clear signal.
When all contents of memory (1) are cleared by MC, a pointer of "1" is provided at one end (right side of drawing).
Depending on the write clock SI from the circuit on the transmitting side and the read clock SO from the circuit on the receiving side, when the write clock SI is supplied When the read clock SO is supplied to the other end side (left side in the drawing) The pointer is shifted to the one end side.

Therefore, in this shift register (2), the memory (1)
A pointer is provided at one end side when the data word is not written in the memory, and a pointer is provided at the other end side when the data word is written in all the stages of the memory (1). . Therefore, the signal of the end stage on one end side of the shift register (2) can be taken out as a read request flag ▲ ▼, and the signal of the end stage on the other end side can be taken out as a write request flag ▲ ▼.

This allows the write request flag ▲ from the circuit on the transmitting side.
▼ is monitored, and when this is “0”, the data word is written, and the read request flag from the receiving circuit ▲ ▼
Is monitored and the data word is read when this is "0", the writing / reading of the data word can be reliably performed.

[Problems to be solved by the invention]

However, in the above-mentioned device, when data is input / output, a flag ▲ ▼ or ▲ is set for each data word.
▼ must be determined, and for example, in the microprogram control processor, a condition determination command is issued for each data word, so that control cannot be smoothly performed. That is, in the above-described processor or the like, there are cases where operations such as so-called pipeline processing and multiple processing are performed at the same time as input / output of data. I won't. In addition, in the input / output of data, it is necessary to judge the count value of the counter when managing the number of data. In addition to these, the above-mentioned flags ▲ ▼ and ▲ ▼ should be judged for each data word. Has been a heavy burden for speeding up I / O.

By the way, in the above-described data transfer between processors, it is general to block each predetermined number of data words and perform burst transfer. In that case, the determination of the above flag may be made for each block transfer. However, the above-mentioned device cannot form the above-mentioned flag for each block.

[Means for solving problems]

The present invention provides a memory (1) having a predetermined number of stages (L) in which data words are sequentially written from the stage on the output end side, and a write clock from the stage on one end side to the other end side and a read clock. The first shift register (2) having the predetermined number of stages in which the pointer is sequentially shifted to the one end side, and sequentially from the stage on the one end side to the other end side by the write clock and to the one end side by the read clock. The pointer has an arbitrary number of stages (P) of the second shift register (3), and a predetermined number (N) of the data words are written with the block data in the memory (DI). ₁ -DI _M) read by (DO ₁ to DO _M) together, the first write per the data word in the shift register clock SI and read clock
When SO is supplied, the write request flag from the stage on the other end side ▲
▼ is output, the write clock BSI and the read clock BSO for each block are supplied to the second shift register, and the read request flag ▲ ▼ is output from the stage on the one end side. .

[Action]

According to this, the read request flag for block transfer is output from the stage on the one end side of the second shift register,
Therefore, in the circuit on the receiving side, it is sufficient to judge the flag for each transfer of a predetermined block, the number of judgments is reduced, and data can be input / output extremely smoothly.

〔Example〕

In FIG. 1, a memory (1) and a shift register (2) similar to those described in the prior art are provided, and a second shift register (3) having an arbitrary number of stages (P) is provided.

Then, the shift register (3) is provided with a pointer of "1" at the end of one end side (right side in the drawing) when all the contents of the memory (1) are cleared by the master clear signal MC, Block write clock BSI for each predetermined number (N) of data words that make up the block from the circuit
Also, according to the block read clock BSO for each predetermined number (N) of data words from the circuit on the receiving side, when the write clock BSI is supplied, the read clock BSO is supplied to the other end side (left side in the drawing). When this happens, the pointer is shifted to one end. Both the block write clock BSI and the block read clock BSO are generated when the writing or reading of N data words is completed.

Therefore, in this shift register (3), the memory (1)
A pointer is provided at one end side when no data word is written in the memory, and this pointer is shifted to the other end side only when one block of data word is written in the memory (1). To be done.

Therefore, by extracting the signal of the end stage on the one end side of the shift register (3) and setting it as a read request flag ▲ ▼, when this flag is “0”, one block or more of data is stored in the memory (1). The word has been written,
A block transfer consisting of N data words can be smoothly performed by judging this flag in the circuit on the receiving side.

In this way, according to the above-mentioned device, the read request flag for block transfer is output from the stage on the one end side of the second shift register, and therefore the flag on the receiving side can be determined for each transfer of a predetermined block. Well, the number of judgments is reduced, and data input / output can be performed extremely smoothly.

In the above-mentioned device, the second shift register (3)
The number of steps P is However, since the value of N is not constant depending on the application (however L >> N), there is no problem even if P = L, for example.
In this case, the risk of overflow of the shift register (3) can be completely eliminated.

In the above example, the case where the read request flag for block transfer is formed has been described. However, by providing a means for extracting the signal of the stage corresponding to the integer part of L / N of the shift register (3), It is also possible to form an inclusion request flag.

〔The invention's effect〕

According to the present invention, the read request flag for block transfer is output from the stage on the one end side of the second shift register, so that the circuit on the receiving side may judge the flag for each transfer of a predetermined block. The number of judgments has been reduced, and data can be input and output extremely smoothly.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of the present invention, and FIG. 2 is a diagram for explaining a conventional technique. (1) is a memory, and (2) and (3) are shift registers.

Claims (1)

(57) [Claims] 1. A memory having a predetermined number of stages in which data words are sequentially written from the stage on the output end side, and sequentially from the stage on one end side to the other end side by a write clock and to the one end side by a read clock. The first shift register having the predetermined number of stages in which the pointer is shifted, and the arbitrary number of stages in which the pointer is sequentially shifted from the stage at one end side to the other end side by the write clock and to the one end side by the read clock. A second shift register, and block data is written into and read from the memory for each predetermined number of the data words, and the first shift register is written for each of the data words. The input clock and the read clock are supplied, the write request flag is output from the stage on the other end side, and the write clock and the read clock for each block are output to the second shift register. Buffer memory which is adapted read request flags from the one end side of the step is output but is supplied.