JP2503270B2 - Communication error processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a communication method for communicating data by serial transfer in which clocks are synchronized between two devices, and more specifically, relates to a communication error processing method when an error occurs, and a clock error in serial transfer. Reliable detection of
For the purpose of realizing quick execution of the resending process of communication data at the time of occurrence of an abnormality, the receiving side device receives a synchronization signal and a predetermined number of communication data from the data transmitting means in the transmitting side device in synchronization with the synchronization signal. In the communication processing method of serially transferring to the receiving side device, and receiving the predetermined number of communication data in synchronization with the synchronizing signal by the data receiving means in the receiving side device, the receiving side device is synchronized with the synchronizing signal. And a reply data transmitting means for serially transferring the same number of reply data as the predetermined data number to the transmitting side device, and receiving the predetermined number of reply data in synchronization with the synchronization signal in the transmitting side device. A reply data receiving unit, a reply data monitoring unit that monitors whether or not an abnormality has occurred in the reply data every time the unit receives the reply data of the number of data, and the unit returns the reply data. Timing abnormality data transmitting means for serially transferring the timing adjustment data for making the data receiving means in the receivable state when the abnormality of the reception data is detected, and after transmitting the timing adjustment data, And a data resending unit that resends the predetermined number of communication data at the time when the abnormality of the reply data is detected to the receiving side device.

[Industrial applications]

The present invention relates to a communication system that communicates data by serial transfer in which clocks are synchronized between two devices, and more particularly to a communication error processing system when an error occurs.

[Conventional technology]

Among the methods of performing data communication between a plurality of devices such as a microprocessor, there is a method of serial (serial, hereinafter the same) transfer. In this method, for example, an n-bit shift register is provided in both the transmission side device (hereinafter referred to as the main device) and the reception side device (hereinafter referred to as the slave device), and the n-bit communication is previously performed in the shift register of the main device. After setting the data,
The register is sequentially shifted according to a predetermined clock to transfer the serial data output from the register to the slave device, and the clock is also transferred at the same time. In the slave device, the internal shift register is sequentially shifted in synchronization with the clock sent from the main device, and the serial data of n bit unit transferred from the main device is sequentially input to the shift register, and n bit is set. Imported when input. In this case, both the main device and the slave device are provided with shift counters for counting the number of transfer bits, and each time the transfer of n bits is completed, the result is transmitted to the internal control unit,
If there is the next communication data in the master device, set it in the shift register, and in the slave device, input n to the shift register.
Performs processing such as fetching bits inside.

In this case, various methods are conceivable for transferring the clock from the main device to the slave device for synchronizing the communication, such as a method of transferring mixed with communication data and a method of transferring using a dedicated clock line. However, in this case, when an abnormality such as noise superimposed on the clock occurs, shift shift of the shift register and shift shift of the shift counter occur, and bit shift occurs in the data being transferred and the communication data thereafter. Since the data changes, accurate communication cannot be performed. For this reason, a means for recovering from the shift deviation due to the clock abnormality is required.

[Problems to be Solved by the Invention]

However, the conventional serial transfer method does not take any special recovery measures against a clock abnormality, and only transfers the communication data from the master device to the slave device once. Therefore, the slave device has a problem that not only the communication data being transferred but also the communication data after that is changed, and there is a possibility that processing may be performed by incorrect communication data.

An object of the present invention is to realize reliable detection of a clock abnormality in serial transfer and rapid execution of communication data retransmission processing when an abnormality occurs.

[Means for solving the problem]

FIG. 1 is a block diagram of the present invention. According to the present invention, the data transmission means 2 in the transmission side device 1 serially transfers the synchronization signal 3 and a predetermined number of communication data 4 in synchronization with the synchronization signal to the reception side device 5. It is premised on a communication processing system in which the reception means 6 receives the predetermined number of communication data 4 in synchronization with the synchronization signal 3. Note that various methods are conceivable, such as a method in which the synchronization signal is transferred using a dedicated line different from the communication data transfer line, a method in which the synchronization signal is mixed with the communication data, and the like. Further, when the transmission side device 1 and the reception side device 5 mutually transfer communication data, they become a transmission side device and a reception side device, and the respective means shown below are the transmission side device 1 and the reception side device. However, in order to clarify the means of the transmitter and the means of the receiver, the case where the communication data 4 is transferred from the transmitter device 1 to the receiver device 5 is shown here.

According to the present invention, first, the receiving side device 5 has a reply data transmitting means 8 for serially transferring to the transmitting side device 1 the same number of return data 7 as the predetermined number of data in synchronization with the synchronization signal 3.
The means is, for example, means for serially transferring a predetermined bit pattern of the same number as the predetermined data number to the transmission side device 1.

Next, the sending side device 1 has a reply data receiving means 9 for receiving the predetermined number of reply data 7 in synchronization with the synchronizing signal 3.

Then, it has a reply data monitoring means 10 for monitoring whether or not an abnormality has occurred in the reply data every time the means receives the predetermined number of reply data 7. The means is, for example, the reply data 7 received by the reply data receiving means 9.
Is a means for determining whether or not it is equal to the predetermined bit pattern.

Further, the timing for serially transferring the timing adjustment data 11 for making the data receiving means 6 in the receiving side device 5 in the receivable state when the abnormality of the reply data 7 is detected by the means. Adjustment data transmission means 12
Have. The means is, for example, means for serially transferring the predetermined bit pattern of the predetermined number of bits.

After the timing adjustment data 11 is transmitted, the data resending unit 13 resends the predetermined number of communication data 4 at the time when the abnormality of the reply data 7 is detected to the receiving side device 5.

In the above-described configuration, the data transmitting means 2, the return data receiving means 9, the timing adjustment data transmitting means 12 and the data retransmitting means 13 in the transmitting side device 1 transmit the predetermined amount of serial data to the synchronization signal 3, for example. The shift register is composed of the predetermined number of data (number of bits) for transmitting each data bit by bit while sequentially shifting in synchronization.
Moreover, the shift register of each means can be realized by sharing one shift register, for example. Further, the count of the predetermined number of data is, for example, 1 in the shift register.
It is a shift counter that counts up each time it is shifted. This shift counter can also be shared.

On the other hand, the serial communication data receiving part of the data receiving means 6 in the receiving side device 5 and the reply data 7 sending part of the reply data transmitting means 8 are, for example, the same number of shift registers and shift counters as the above. The shift register and shift counter of both can be shared by one shift register and shift counter. In this case, at the start of communication, first, the predetermined number of reply data 7 is set in the shift register, and in synchronization with the synchronization signal 3, the communication data 4 is input and the reply data 7 is output one bit at a time. At the time of shifting by the number of data, the transmission of the reply data 7 of the predetermined number of data is completed, and at the same time, the communication data 4 of the predetermined number of data transferred from the transmitting side device 1 can be input to the shift register.

[Action]

At the same time that the communication data 4 is transferred from the transmission side device 1 to the reception side device 5 in the predetermined number of data units, the same number of predetermined reply data 7 is transferred from the reception side device 5 to the transmission side device 1. When an abnormality occurs in the synchronization signal 3, the transmitting side device 1 transmits the predetermined number of communication data 4 and the receiving side device 5 receives the predetermined number of communication data 4 and return data. Since the transmission operation of 7 is not synchronized, the reply data 7 received by the reply data receiving means 9 at the time when the transmission side device 1 has finished transmitting the predetermined number of communication data 4 has a predetermined bit. No longer a pattern. Therefore, by monitoring the reply data 7 with the reply data monitoring means 10 in the transmission side device 1, the abnormality of the synchronization signal 3 can be easily detected.

When an abnormality is detected, as a result of the synchronization being lost, the data receiving means 6 of the receiving side device 5 may not have completed the reception operation of the predetermined number of data. Therefore, the transmitting side device 1
The dummy timing adjustment data 11 is transmitted from the internal timing adjustment data transmitting means 12 to the data receiving means 6 so that the data receiving means 6 is in a receivable state.

After that, the data resending means 13 is activated to resend the communication data 4 at the time of occurrence of an abnormality to the data receiving means 6, whereby the correct communication data 4 can be reliably transferred to the receiving side device 5.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is an overall configuration diagram of an embodiment of the present invention. The present embodiment is realized as a serial (serial, hereinafter the same) transfer portion of communication data between a plurality of processors incorporated in a telephone terminal in ISDN (Integrated Services Digital Network). FIG. 2 mainly shows two processors, a main device 14 and a slave device 15, which perform serial transfer of communication data in the telephone terminal.

The main unit 14 is a processor mainly responsible for interfacing with subscribers, operates in synchronization with the clock CLK # 1, and is a key matrix 17 which is a push button of a telephone.
From the signal, hook switch detection signal 19, hands-free / headset switching detection signal 20, power failure detection signal 21 from the switch that switches the transmission and reception with the speaker and microphone or with the headset, from the switch that switches the tone of the ringing tone Ringer tone color switch detection signal 22,
The ringer volume control signal 25, which is not particularly shown in the figure, is processed by the reception volume changeover switch detection signal 23 from the switch for changing the reception volume and the reset signal RST for performing mutual reset with the slave device 15. Output to the circuit for. At this time, the switching of the ringer tone color is performed by the tone color switching circuit connected to the main device 14.
Performed at AIU24. In addition, the parallel control data CTL is exchanged with another processor (not shown) through the PPI 18, which is an interface circuit.

The slave device 15 is a processor that performs an actual communication process mainly based on the result of each interface process in the main device 14. Further, the slave device 15 controls the lamp matrix 26 which is various lamps, performs each process for the reset signal RST and the like for performing mutual reset with the main device 14, and # 1 to # The external device connected to each function port 27 of 6 is controlled.

A serial transfer portion 16 is provided between the main device 14 and the slave device 15 to serially transfer a control signal based on each interface process from the main device 14 to the slave device 15.

The circuit configuration of this portion is shown in FIG. First, the main device 14
Inside the slave device 15, there are shift registers 28 and 30 which are buffers for serial transfer, and each register has an n bit (plural bits) configuration. Note that FIG. 3 shows a 4-bit configuration of B _{0 to} B ₃ for simplicity. Then, the serial output SO from the least significant bit B ₀ of the shift register 28 of the master device 14 becomes the serial input SI of the slave device 15 and is input to the most significant bit B ₃ of the shift register 30, and conversely, the slave device. The serial output SO from the least significant bit B ₀ of the shift register 30 of 15 becomes the serial input SI of the main device 14 and is input to the most significant bit B ₃ of the shift register 28. The shift register 28 shifts according to the shift clock SC / TO generated in the main unit 14, and the shift register 30 also shifts according to the shift clock SC / TO transferred from the main unit 14 by a dedicated line. To do.

Next, in the main device 14 and the slave device 15, there are provided 2-bit shift counters 29 and 31 for counting the shift count numbers in the shift registers 28 and 30, respectively. The shift counter 29 shifts according to the shift clock SC / TO generated in the main unit 14, and the shift counter 31 also
The shift operation is performed according to the shift clock SC / TO transferred from the main unit 14 by a dedicated line. The number of bits of the shift counters 29 and 31 changes according to the number of bits of the shift registers 28 and 30.

The operation of the embodiment having the above configuration will be described below. The part particularly related to the present invention is the serial transfer part of FIG.
That is, since it has the configuration shown in FIG. 16, that is, FIG. 3, the description will be focused on this part.

First, the basic operation of the serial transfer portion of FIG.
A description will be given according to the operation timing chart in the figure.

First, each bit B ₃ of the shift register 28 in the main unit 14
To B ₀ are communication data SB to be transferred to the slave device 15 in advance.
Assume that _{3 to} SB ₀ are set.

Then, a serial port activation signal (not shown) in the main device 14 rises (by software control) at the timing t ₁ in FIG. 4 (a), whereby the main device 14
The shift clock SC / TO is internally generated as shown in FIG. 4 (b).

Subsequently, first, at the falling timing t ₁ of the first cycle of the shift clock SC / TO, B ₀ of the shift register 28 is changed.
The content SB _{0 of} is output as a serial output SO as shown in FIG. 4 (c). At this time, the data SI ₀ is input from the slave device 15 to the serial input SI. Then, at the next rising timing t ₂ of the shift clock SC / TO, the data SI ₀ input to the serial input SI is input to B _{3 of the} shift register 28 (FIG. 4 (d) → (e)). ),
Contents of B ₃ SB ₃ shifts to B ₂ (Fig. 4 (e) →
(F)), the contents of B ₂ SB ₂ shifts to B ₁ (Fig. 4 (f)
→ (g)), the contents of B ₁ SB ₁ shifts to B ₀ (FIG. 4 (g) → (h)).

Next, at the falling timing t ₃ of the second cycle of the shift clock SC / TO, the contents SB of B ₀ of the shift register 28
₁ is output as the serial output SO as shown in FIG. 4 (c). At this time, the data SI ₁ is input from the slave device 15 to the serial input SI. Then, with the trigger of the next rising timing t ₄ of the shift clock SC / TO,
Data SI ₁ which is input to the serial input SI is input to B ₃ of the shift register 28 (FIG. 4 (d) → (e)) , the contents SI ₀ of B ₃ is shifted to B ₂ (Figure 4 (E) → (f)), contents of B ₂ SB ₃ shifts to B ₁ (FIG. 4 (f) → (g)), B ₁
Content SB ₂ shifts to B ₀ (Fig. 4 (g) →
(H)).

The same applies to the third cycle of the shift clock SC / TO. At t ₅ , the contents of B ₀ SB ₂ → serial output SO, SI ₂ → serial input
SI next, the trigger of t _6, the serial input SI data SI
₂ → Content of B ₃ , B ₃ SI ₁ → Content of B ₂ , B ₂ SI ₀ → Content of B ₁ , B ₁ S
Shift from B _{3 to} B ₀ .

Then, in the fourth cycle of the shift clock SC / TO, at t ₇ , the contents of B ₀ are SB ₃ → serial output SO, SI ₃ → serial input SI, and at the trigger of t ₈ , the data SI ₃ → Contents of B ₃ , B ₃ SI ₂ → B ₂ , contents of B ₂ SI ₁ → B ₁ , contents of B ₁ SI ₀ → B ₀ Shift.

In the above four cycles, the output operation of the communication data SB _{0 to} SB ₃ set in the shift register 28 of FIG. ₃ and the slave device
Input operations of the data SI ₀ to SI ₃ from 15 to the shift register 28 are simultaneously executed. In this case, shift clock SC / T
The 2-bit shift counter 29 (cleared in advance) counts up in synchronization with each rising edge of O (t ₂ , t ₄ , t ₆ , t _{8 in} FIG. 4 (b)), and FIG. the count value at t ₈ in b) is at the time of return to "00", the serial port of the serial interrupt signal as FIG. 4 (i) rises, thereby Figure 4 at the timing t ₉ (a) The activation signal falls, and the transfer of 4-bit communication data is completed.

In the above operation, although the operation on the slave device 15 side in FIG. 3 is omitted, the shift clock SC / T from the master device 14 is omitted.
In synchronization with O, the shift register 30 and the shift counter 31 operate in exactly the same way.

Next, a specific operation of this embodiment based on the above basic operation will be described below.

First, the operation during normal operation will be described. In this case, the 8th
As shown in the figure, the transmission data (communication data) is transferred from the master device 14 to the slave device 15, and at the same time, the slave device 15 transfers the transmission data (communication data) to the slave device 15.
Transfer the reply data to. Then, when the master device 14 side normally receives the reply data, the slave device 15 side also normally receives the transmission data. This operation will be described with reference to the operation example of FIG. It is to be noted that items 1 to 3 in FIG. 8 correspond to respective processes having the same numbers in FIG.

First, as shown in FIG. 5 (first stage), in the main device 14, the transmission data “0100” is preset in B _{3 to} B ₀ of the shift register 28. In the slave device 15, the shift register 30
The reply data “0010” is set in B _{3 to} B ₀ of.

In this state, serial transfer is activated from the control program of the main unit 14 (see FIG. 4 (a)), and after the shift counter 29 clears "00", the shift clock is changed as shown in the same figure (second stage). With SC / TO, master device 14 is slave device 15
1 bit of the transmission data of the shift register 28 is transferred to and the 1-bit reply data from the slave device 15 is received (see FIG. 5).
S1). In the slave device 15, before transmission from the master device 14,
The control program activates serial transfer, clears the shift counter 31, and receives 1-bit transmission data from the main unit 14 according to the shift clock SC / TO,
The reply data of the shift register 30 is transferred to the main unit 14 by 1 bit (S4 in FIG. 5).

Similarly, the same operation as above is repeated in synchronization with the shift clock SC / TO in FIG.
1, S4).

After the operation of, the shift counter 29 on the main unit 14 side displays "0.
It becomes "0", whereby the transfer of the transmission data is completed, and the control program is serially interrupted (see the explanation of FIG. 4). As a result, the control program recognizes that the transfer is completed (S2 in FIG. 5), and then determines whether or not the value of the shift register 28 is the return data “0010” (S3 in FIG. 5).

Since the reply data "0100" set in the shift register 30 of the slave device 15 has been correctly input to the shift register 28 of the main device 14 by the operations of to in FIG.
The determination is YES, and the transfer operation of the transmission data in the main device 14 ends normally.

On the other hand, on the slave device 15 side, after the operation of FIG. 5 is completed, the shift counter 29 becomes "00", whereby the transfer of the transmission data is completed, and the serial interrupt is sent to the control program on the slave device 15 side. It takes. As a result, the control program fetches the transmission data “0100” input to the shift register 30 into a RAM (not shown) if no other communication data is input within a certain period of time (the reason for this will be described later). Processing is performed (S5 in FIG. 5).

Next, the operation at the time of abnormal operation will be described. in this case,
As shown in FIG. 9, as in the normal operation, the main unit 14
From the slave device 15 to the transmission data at the same time
The reply data is transferred from 15 to the main device 14. Then, when the main device 14 side determines that the reply data is abnormal, the abnormality is recognized. In this case, the transmission data is ignored on the slave device 15 side. Subsequently, the shift timing adjustment data is transferred from the master device 14 to the slave device 15, and the shift register 30 of the slave device 15 is put into a receivable state as described later. At this time, the data in the shift register 30 is transferred from the slave device 15 to the master device 14, but this is ignored. After this operation, the transmission data that has failed to be transferred is retransmitted from the main device 14 to the slave device 15. As a result, the slave device 15 receives this transmission data normally. Also at this time, the transfer data from the slave device 15 is ignored by the main device 14. The above operation will be described with reference to the operation examples of FIGS. 6 and 7. Incidentally, in FIG.
('),-And-correspond to each process having the same number in FIG. 6 or FIG.

FIG. 6 shows the shift clock SC from the master device 14 to the slave device 15.
This is an operation example when / TO is not transferred correctly and the slave device 15 does not perform a correct shift operation.

First, as in the case of FIG. 5, FIG. 6 (a)
As shown in (first stage), in the main device 14, the shift register 28
Transmission data “0100” is preset in B _{3 to} B ₀ . Further, in the slave device 15, reply data “0010” is set in B _{3 to} B ₀ of the shift register 30.

In this state, the serial transfer is activated from the control program of the main unit 14, and after the shift counter 29 clears "00", the shift clock SC / T as shown in the same figure (second stage)
By O, the master device 14 transfers 1 bit of the transmission data of the shift register 28 to the slave device 15 and receives the 1-bit reply data from the slave device 15 (FIG. 6 (a) S1). At the same time,
The slave device 15 is activated by serial transfer upon receipt of the shift clock SC / TO, clears the shift counter 31, and then receives 1-bit transmission data from the main device 14 in accordance with the shift clock SC / TO. Transfer the reply data of the shift register 30 by 1 bit to 14 (Fig. 6 (a))
S4).

Next, in FIG. 6 (a), the master device 14 shifts by 1 bit in the same manner as described above, but the slave device 15 does not shift because noise is generated in the shift clock SC / TO, and the shift register 30 and The contents of the shift counter 31 do not change.

Then, in FIG. 6 (a), the same operation as the above case is repeated in synchronization with the shift clock SC / TO (FIG. 6 (a) S1, S4).

When the operation of is completed, the shift counter 29 of the main device 14 becomes "00", so the transfer of the transmission data is completed and the control program is serially interrupted.
In 15, the shift counter 31 is still “11”, so the transfer is not completed.

Then, the control program of the main unit 14 recognizes the completion of transfer (S2 in FIG. 6 (a)), and then determines whether or not the value of the shift register 28 is the reply data “0010” (FIG. 6 ( a) S3).

Now, in the operations (1) to (6) of FIG. 6, since the reply data correctly shifted from the slave device 15 to the master device 14 is not input in the process, the reply data input to the shift register 28 of the master device 14 is Since the correct data “0010” has not been obtained, the determination at S3 in FIG. 6 (a) is NO.

As a result, in the main device 14, as shown in FIG.
Shift timing adjustment data “111” is stored in the shift register 28.
1 "is set (S6 in FIG. 6 (b)). At this time, the value of the shift counter 29 is "00" because the transfer has been completed once.

After that, in FIG. 6 (b) to FIG.
A total of 4 bits of shift timing adjustment data are transferred from the shift register 28 of the master device 14 to the shift register 30 of the slave device 15 in synchronization with the SC / TO.

In the slave device 15, the shift counter 31 becomes “00” at the end of the process of FIG. 6B, and the control is transferred to the control program by the serial interrupt of the transfer completion. In the control program, thereafter, the reception time for receiving the shift timing adjustment data in an idle state is measured. Then, after the reception time elapses, serial transfer is activated from the control program (see FIG. 4A), and the shift counter 31 is cleared as shown in FIG. 6B.

In the main unit 14, after the transfer of the shift timing adjustment data is completed in FIG.
Since it becomes "0", the control is transferred to the control program by the serial interrupt of the transfer completion. Then, the control program sets the transmission data "0100", which has failed to be transferred in FIG. 6 (a) to the shift register 28, as shown in FIG. 6 (b) (S8 in FIG. 6 (b)). ).

After this operation, serial transfer is activated in the main unit 14 (S9 in FIG. 6 (b)), and as shown in FIG. 6 (b), a total of 4 bits are transmitted one bit at a time in synchronization with the shift clock SC / TO. Data is transferred from the shift register 28 of the master device 14 to the slave device 15
It is retransmitted to the shift register 30 of.

After this operation, the main device 14 does not interrupt the control program and ends the data transfer process.

On the other hand, in the slave device 15, after receiving the 4-bit resend data, the process returns to the control program by the serial interrupt at the end of transfer. As a result, the control program, if no other communication data is input within the fixed time, shift register
The transmission data “0100” input to 30 is not shown in the RA
Import to M and perform the subsequent processing (Fig. 6 (b) S1
1).

Next, FIG. 7 shows an operation example in the case where the correct shift operation is not performed in the main device 14 for some reason (noise or the like).

In this case, in FIG. 7 (a), contrary to FIG. 6 (a), the main device 14 does not shift and the contents of the shift register 28 and the shift counter 29 do not change.

Therefore, in the main device 14, the transfer is not completed in
The transfer is completed when there is one more timing '. Then, in this case, the reply data input from the slave device 15 to the shift register 28 is different from the data “0010” set in the slave device 15, and therefore the determination in S3 of FIG. 7 (a) is NO.

On the other hand, in the slave device 15, after the processing of FIG. 7A, a serial interrupt for transfer completion is applied, and after being recognized by the control program (S12 of FIG. 7A), the shift counter 31 is cleared ( In FIG. 7 (a) S13), the shift register 30 is in a receivable state.

After the above operation, the processes of to are performed in FIG. 7B as in the case of FIG. 6B to transfer the shift timing adjustment data from the main device 14 to the slave device 15. The transmission data is retransmitted.

〔The invention's effect〕

According to the present invention, the communication data is transferred from the transmission side device to the reception side device in the unit of the predetermined number of data, and at the same time, the same number of predetermined reply data is transferred from the reception side device to the transmission side device and the reply data is transmitted. By monitoring the reply data monitoring means in the side device, it is possible to easily detect the abnormality of the synchronization signal.

Then, when an abnormality is detected, the transmission side device sends dummy timing adjustment data to the data receiving means to make the data receiving means ready for reception, and then retransmits the communication data when the abnormality occurs to the data receiving means. By doing so, correct communication data can be surely and quickly transferred to the receiving side device.

[Brief description of drawings]

1 is a block diagram of the present invention, FIG. 2 is an overall configuration diagram of an embodiment of the present invention, FIG. 3 is a configuration diagram of a serial transfer portion, and FIG. 4 is a basic operation timing chart of serial transfer. , FIG. 5 is an explanatory diagram of normal operation, FIGS. 6 (a) and 6 (b) are explanatory diagrams when the slave device does not shift, and FIGS. 7 (a) and 7 (b) are main devices. FIG. 8 is a conceptual diagram when no shift is performed, FIG. 8 is a conceptual diagram during normal operation, and FIG. 9 is a conceptual diagram during abnormal operation. 1 ... Sending side device, 2 ... Data sending means, 3 ... Sync signal, 4 ... Communication data, 5 ... Receiving side device, 6 ... Data receiving means, 7 ... Reply data, 8 ... Reply Data sending means, 9 ... Reply data receiving means, 10 ... Reply data monitoring means, 11 ... Timing adjustment data, 12 ... Timing adjustment data sending means, 13 ... Data resending means.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukie Tachibana Taka 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Fujitsu First Communication Software Co., Ltd. (72) Hirofumi Onodera 3 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture Fujitsu 9 Communications Software Co., Ltd. (72) Inventor Masahiro Todo 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture Masahiro Todo Fujitsu 1 Communications Software Co., Ltd. (72) Inventor Ichiro Takahashi Kanagawa 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi Fujitsu Daiichi Communication Software Co., Ltd.

Claims (1)

(57) [Claims] 1. A reception side device (1) receives a synchronization signal (3) from a data transmission means (2) in a transmission side device (1) and a predetermined number of communication data (4) in synchronization with the synchronization signal (3). In the communication processing method, the data is transferred serially to 5), and the predetermined number of communication data (4) is received by the data receiving means (6) in the receiving side device in synchronization with the synchronization signal (3). In the side device (5), reply data transmitting means (8) for serially transferring the same number of reply data (7) as the predetermined number of data to the sending device (1) in synchronization with the synchronization signal (3). And a reply data receiving means (9) for receiving the predetermined number of reply data (7) in synchronization with the synchronization signal (3) in the transmitting side device (1), and the predetermined data by the means. Every time the reply data (7) of the number of data is received, there is an abnormality in the reply data. Reply data monitoring means (10) for monitoring whether or not it has occurred, and for making the data receiving means (6) in a receivable state when an abnormality of the reply data (7) is detected by the means. A timing adjustment data transmitting means (12) for serially transferring the timing adjustment data (11) to the data receiving means (6), and an abnormality of the reply data (7) is detected after the timing adjustment data (11) is transmitted. And a data resending means (13) for resending the predetermined number of communication data (4) to the receiving side device (5) at the point of time.