JP2598936B2 - Method for manufacturing photovoltaic device - Google Patents
Method for manufacturing photovoltaic deviceInfo
- Publication number
- JP2598936B2 JP2598936B2 JP63010011A JP1001188A JP2598936B2 JP 2598936 B2 JP2598936 B2 JP 2598936B2 JP 63010011 A JP63010011 A JP 63010011A JP 1001188 A JP1001188 A JP 1001188A JP 2598936 B2 JP2598936 B2 JP 2598936B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode film
- electrode
- power generation
- photovoltaic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は、例えば電卓、腕時計等の民生用小型電子機
器の電源として用いられる光起電力装置の製造方法に関
する。The present invention relates to a method of manufacturing a photovoltaic device used as a power source for small consumer electronic devices such as calculators and watches.
(ロ) 従来の技術 基板の絶縁表面の複数の発電領域に光電変換素子を設
けそれら光電変換素子を電気的に直列接続した光起電力
装置は例えば特公昭58−21827号公報に開示された如く
既に知られており、上述の如き電卓等の民生用小型電子
機器の電源として実用化されている。光起電力装置に対
する一般的要求は、単位発電量当りの価格の低減にあ
り、光電変換効率の上昇と、製造コストの引き下げによ
り達成される。(B) Conventional technology A photovoltaic device in which photoelectric conversion elements are provided in a plurality of power generation regions on an insulating surface of a substrate and the photoelectric conversion elements are electrically connected in series is disclosed, for example, in Japanese Patent Publication No. 58-21827. It is already known and has been put into practical use as a power source for small consumer electronic devices such as the above-mentioned calculators. A general requirement for a photovoltaic device is to reduce the price per unit of power generation, which is achieved by increasing the photoelectric conversion efficiency and reducing the manufacturing cost.
ところが、上記民生用小型電子機器の電源として用い
られる光起電力装置は、太陽光発電に利用されるものに
比して、負荷の駆動回路を構成するLSI等の低消費電力
化が進み、50lux以下の室内光下に於ける発電出力によ
って、十分に電子機器を動作させることができる現在、
光電変換効率の上昇よりはむしろ製造コストに対する要
求が厳しい。However, the photovoltaic device used as a power source for the above-mentioned small consumer electronic devices has been reduced in power consumption, such as an LSI constituting a drive circuit of a load, as compared with that used for photovoltaic power generation. At present, it is possible to operate electronic devices sufficiently with the power generation output under the following room light,
Rather than increasing the photoelectric conversion efficiency, the demand for the manufacturing cost is strict.
上記先行技術に開示された光起電力装置の製造は、光
電変換素子を構成する第1電極膜、半導体膜及び第2電
極膜の各々に対し、形成時に被着してはならないところ
を金属マスクで覆うマスキング法を用いることによっ
て、製造工程の簡略化を図り、製造コストの低減化を達
成している。In the manufacture of the photovoltaic device disclosed in the above prior art, the first electrode film, the semiconductor film, and the second electrode film constituting the photoelectric conversion element must be covered with a metal mask at a place where they should not be adhered at the time of formation. By using the masking method of covering with, the manufacturing process is simplified and the manufacturing cost is reduced.
然し乍ら、斯るマスキング法によれば、各光電変換素
子毎に膜を形成する際、基板が加熱状態にあると該マス
キング法特有の膜周縁に於いて膜の泌み出し(にじみ)
が発生するために、予め定められた微細なフアインパタ
ーンが得られず、各光電変換素子が互いに隣接する隣接
間隔部の間隔長を十分にとらないと例えば隣接関係にあ
り分割すべき第2電極膜同士が接触する短絡危惧を持
つ。特に第2電極膜を光入射面とすべくITOやSnO2に代
表される透光性導電酸化物(以下TCOと呼ぶ)を用いる
と、当該TCOの第2電極膜の好適な成膜には基板を第200
℃以上の温度に保持しなければならないため、斯る高温
状態では金属マスクは著しく線膨張することとなり、マ
スキングしなければならないところを密閉するに至らず
膜周縁における膜の泌み出しが著しく、その結果第2電
極膜同士の短絡事故の発生が顕著となる。またTCO第2
電極は透光性であるために短絡事故が発生していたとし
ても目視判定することは難しい。そして、更に視る隣接
間隔部は光電変換素子間に位置する結果、光電変換に寄
与しない無効領域を形成し、受光面積中に占める有効発
電領域の割合を減少させるために、可及的に狭くしなけ
ればならない、という短絡事故の回避と相い反すること
が要求される。However, according to such a masking method, when a film is formed for each photoelectric conversion element, when the substrate is in a heated state, the film exudes (bleeds) at the film periphery peculiar to the masking method.
Occurs, a predetermined fine fine pattern cannot be obtained, and if the photoelectric conversion elements do not have a sufficient interval length between adjacent adjacent portions, for example, the photoelectric conversion elements are in an adjacent relationship and the second There is a danger of short circuit between the electrode films. In particular, when a light-transmitting conductive oxide (hereinafter referred to as TCO) typified by ITO or SnO 2 is used to make the second electrode film a light incident surface, a suitable film formation of the second electrode film of the TCO is performed. Substrate 200
Since the temperature must be maintained at a temperature of at least 0 ° C., the metal mask will undergo significant linear expansion in such a high temperature state, and the exudation of the film at the periphery of the film will not be sufficient without sealing the area where the mask must be performed. As a result, the occurrence of a short circuit accident between the second electrode films becomes remarkable. Also TCO 2
Since the electrodes are translucent, it is difficult to visually determine even if a short circuit accident has occurred. Then, as a result of being located between the photoelectric conversion elements, the adjacent space to be further viewed forms an ineffective region that does not contribute to photoelectric conversion, and is as narrow as possible in order to reduce the ratio of the effective power generation region to the light receiving area. Must be done, which is inconsistent with the avoidance of short-circuit accidents.
周知の如く予め定められた微細なフアインパターンに
膜を加工する手法としてフオトリソグラフイ法が存在す
るが、フオトリソグラフイ法は、フオトレジストの塗
布、ベーキング、露光、現像、エツチング、フオトレジ
ストの剥離等の一連の煩雑な工程を経なければならず、
製造コストの上昇原因となり、低廉価が要求される民生
用小型電子機器の電源として用いられる光起電力装置の
製造には不向きである。As is well known, there is a photolithography method as a method for processing a film into a predetermined fine fine pattern, but the photolithography method involves coating, baking, exposing, developing, etching, and applying a photoresist. It must go through a series of complicated steps such as peeling,
It is not suitable for manufacturing a photovoltaic device used as a power source of a small-sized consumer electronic device which requires a low price because it causes an increase in manufacturing cost.
特開昭59−35487号公報に開示された光起電力装置の
製造方法は、第6図に示す如く基板(1)の絶縁表面
に、マスキング法を利用するものの、各発電領域(2a)
〜(2d)毎には分割することなく先ず第1電極膜(3)
が形成され、その後各膜専用のマスクを用いて半導体膜
(4)及び第2電極膜(5)が上記第1電極膜(3)上
に同様に分割することなく順次重畳被着され、最後に第
7図のように各発電領域毎に光電変換素子(7a)〜(7
d)を分割すべく、それらの隣接間隔部(ab)(bc)(c
d)にレーザビーム(LB)が照射される。即ち、隣接間
隔部(ab)(bc)(cd)の各膜に対してレーザビーム
(LB)を照射して、焼損除去により各光電変換素子(7
a)〜(7d)を分割しようとするその技法は、隣接間隔
部(ab)(bc)(cd)のパターニングをマスキング法や
フオトリソグラフイ法により行なう従来の技法の欠点を
解決する上で極めて有益である。The method of manufacturing a photovoltaic device disclosed in Japanese Patent Application Laid-Open No. 59-35487 uses a masking method on an insulating surface of a substrate (1) as shown in FIG.
First, the first electrode film (3) is not divided for each (2d).
Is formed, and then the semiconductor film (4) and the second electrode film (5) are successively superimposed and deposited on the first electrode film (3) without being divided, using a mask dedicated to each film. As shown in FIG. 7, the photoelectric conversion elements (7a) to (7a)
In order to divide d), their adjacent intervals (ab) (bc) (c
d) is irradiated with a laser beam (LB). That is, a laser beam (LB) is irradiated to each film of the adjacent interval portions (ab), (bc), and (cd), and each photoelectric conversion element (7
The technique of trying to divide a) to (7d) is extremely disadvantageous in solving the drawbacks of the conventional technique of patterning adjacent spaces (ab) (bc) (cd) by a masking method or a photolithography method. It is informative.
然るに、斯るレーザビームの照射による隣接間隔部
(ab)(bc)(cd)のパターニングにあっても、第8図
(A)及び(B)に示すような問題点がある。即ち、隣
接間隔部(ab)に位置する第2電極膜(5)、半導体膜
(4)及び第1電極膜(3)が同時にレーザビームの照
射により除去されると、斯る隣接間隔部(ab)に於いて
相隣り合う光電変換素子(7a)(7b)の対向側面は第1
電極膜(3a)(3b)、半導体膜(4a)(4b)及び第2電
極膜(5a)(5b)の三者が露出する状態となるために、
第8図(A)の如く当該隣接間隔部(ab)にレーザ加工
時の残留物(8)が発生し、これが導電体であると露出
状態にある同一の光電変換素子(7a)、(7b)を構成す
る第1電極膜(3a)、(3b)と第2電極膜(4a)、(4
b)とが不所望に結合したりする。また、第9図(B)
のようにレーザビーム(LB)の周縁部が照射された半導
体膜部分は、該レーザビーム(LB)の周縁部が除去する
に足りる十分なエネルギを持たないためにアニーリング
され微結晶化、或いは結晶化されて、その結果低抵抗層
(9)(9)を形成し同一の光電変換素子(7a)、(7
b)を短絡する原因となる。However, the patterning of the adjacent gaps (ab), (bc), and (cd) by the irradiation of the laser beam also has a problem as shown in FIGS. 8A and 8B. That is, when the second electrode film (5), the semiconductor film (4) and the first electrode film (3) located in the adjacent space (ab) are simultaneously removed by laser beam irradiation, the adjacent space ((ab)) is removed. In ab), the opposing side faces of the adjacent photoelectric conversion elements (7a) and (7b) are the first.
In order for the electrode film (3a) (3b), the semiconductor film (4a) (4b) and the second electrode film (5a) (5b) to be exposed,
As shown in FIG. 8 (A), a residue (8) during laser processing is generated in the adjacent space (ab), and if this is a conductor, the same photoelectric conversion element (7a), (7b) exposed ), The first electrode films (3a) and (3b) and the second electrode films (4a) and (4)
b) undesirably binds. FIG. 9 (B)
The semiconductor film portion irradiated with the peripheral portion of the laser beam (LB) is annealed and micro-crystallized or crystallized because the peripheral portion of the laser beam (LB) does not have enough energy to remove it. As a result, low resistance layers (9) and (9) are formed, and the same photoelectric conversion elements (7a) and (7) are formed.
b) may cause a short circuit.
(ハ) 発明が解決しようとする課題 このように従来の製造方法にあっては、マスキング法
を用いて製造コストの低減化を図ろうとすると第2電極
膜同士の短絡事故や光電変換に寄与しない無効領域の増
大を招いたり、フオトリソグラフイ法においては製造コ
ストの低減化自体達成することができず、またレーザビ
ームを使用したパターニングでも短絡事故の要因を含ん
でいる。従って、本発明は従来の製造方法が持つ上記課
題を同時に解決せんとするものである。(C) Problems to be Solved by the Invention As described above, in the conventional manufacturing method, if the manufacturing cost is reduced by using the masking method, it does not contribute to the short circuit accident between the second electrode films or the photoelectric conversion. The ineffective area is increased, the manufacturing cost cannot be reduced by the photolithography method, and the patterning using a laser beam also involves a short circuit accident. Therefore, the present invention is to solve the above problems of the conventional manufacturing method at the same time.
(ニ) 課題を解決するための手段 本発明は上記課題を解決するために、基板の絶縁表面
における複数の発電領域毎に、該発電領域から上記基板
の周縁に向って延出した延長部分を有する第1電極膜を
分割配置し、上記第1電極膜延長部分を除いて発電領域
の第1電極膜上及び該第1電極膜の隣接間隔部における
絶縁表面上に光活性層を含む半導体膜を被着すると共
に、当該半導体膜から露出した隣接する発電領域の第1
電極膜延長部分上に延出する延長部分を備えた第2電極
を、上記隣接間隔部を含む半導体膜上に積層し、更に少
なくとも発電領域毎の第2電極膜及びその延長部分を覆
い隣接間隔部に位置する第2電極膜部分を露出せしめる
保護膜を、上記半導体膜及び第2電極膜の成膜温度より
低温でのマスキング法を用いて選択的に形成した後、当
該保護膜をマスクとして上記隣接間隔部に露出した第2
電極膜部分をエツチングし、第2電極膜を各発電領域毎
に分割することを特徴とする。(D) Means for Solving the Problems In order to solve the above problems, the present invention provides, for each of a plurality of power generation regions on an insulating surface of a substrate, an extended portion extending from the power generation region toward the periphery of the substrate. A semiconductor film including a photoactive layer on a first electrode film in a power generation region and on an insulating surface at an adjacent space between the first electrode films except for the above-mentioned first electrode film extension portion; And the first of the adjacent power generation regions exposed from the semiconductor film.
A second electrode having an extended portion extending on the electrode film extended portion is laminated on the semiconductor film including the adjacent interval portion, and further covers at least the second electrode film for each power generation region and the extended portion to form the adjacent interval. After selectively forming a protective film for exposing the second electrode film portion located in the portion by using a masking method at a temperature lower than the film forming temperature of the semiconductor film and the second electrode film, the protective film is used as a mask. The second exposed at the adjacent space portion
The electrode film portion is etched, and the second electrode film is divided for each power generation region.
また、上記保護膜をマスクとした隣接間隔部の第2電
極膜部分のエツチングは、当該第2電極膜部分の除去に
より露出した半導体膜部分をその露出面側から基板方向
に向って少なくとも一部除去する工程を含んでいる。Further, the etching of the second electrode film portion at the adjacent interval using the protective film as a mask is performed by removing at least a part of the semiconductor film portion exposed by removing the second electrode film portion from the exposed surface side toward the substrate. Removing step.
(ホ) 作用 上述の如く各発電領域毎に分割することなく半導体膜
上に形成された第2電極膜の分割をエツチングにより用
なうに際し、斯る第2電極膜及び半導体膜の成膜温度よ
り低温でのマスキング法を用いて選択的に形成された保
護膜をマスクとすることによって、当該保護膜はマスキ
ング法により形成されたにも拘らず低温状態での成膜で
あるため、膜の泌み出しが抑圧されている結果、隣接間
隔部の幅を縮小しても斯る隣接間隔部において露出した
第2電極を確実に除去し得る。(E) Function In the case where the division of the second electrode film formed on the semiconductor film is used by etching without being divided for each power generation region as described above, the deposition temperature of the second electrode film and the semiconductor film is used. By using the protective film selectively formed using the masking method at a lower temperature as a mask, the protective film is formed in a low temperature state despite being formed by the masking method. As a result of suppression of exudation, even if the width of the adjacent space is reduced, the second electrode exposed in the adjacent space can be reliably removed.
(ヘ) 実施例 第1図乃至第5図は本発明製造方法を説明するための
ものであって、先ず第1図の工程では、ガラス、セラミ
ツク、高分子フイルム等の絶縁材料或いは表面が絶縁処
理された金属からなる長方形状の基板(1)の一方の主
面(1a)にその主面(1a)の長辺方向に整列して複数の
発電領域(2a)〜(2d)を区画すべき第1電極膜(3a)
〜(3d)が分割配置される。斯る第1電極膜(3a)〜
(3d)は、基板(1)を背面側とするとき、アルミニウ
ム(Al)、チタン銀合金(TiAg)、銀(Ag)の金属から
なる単層、或いは積層構造、更には斯る金属層の表面を
上記TCOで被覆した積層構造を持つと共に、基板(1)
の長辺の一方の周縁に向って延出した延長部分(3ae)
〜(3de)が設けられ、右隣りに分割された第1電極膜
(3b)〜(3d)のある第1電極膜(3a)〜(3c)の延長
部分(3ae)〜(3ce)は、右隣りの第1電極膜(3b)〜
(3d)に向って屈曲したL字状にパターニングされてい
る。尚、この第1電極膜(3a)〜(3d)の形成時に右端
第1電極膜(3d)の延長部分(3de)と共に出力取り出
し用の端子として動作する島状領域(3t)が左端第1電
極膜(3a)に近接して設けられる。(F) Embodiment FIGS. 1 to 5 are for explaining the manufacturing method of the present invention. First, in the step of FIG. 1, an insulating material such as glass, ceramic, polymer film or the like is insulated. A plurality of power generation areas (2a) to (2d) are aligned on one main surface (1a) of the rectangular substrate (1) made of the treated metal and aligned in the long side direction of the main surface (1a). First electrode film to be formed (3a)
To (3d) are divided and arranged. Such a first electrode film (3a)-
(3d) When the substrate (1) is on the back side, a single layer or a laminated structure composed of aluminum (Al), titanium silver alloy (TiAg), silver (Ag) metal, It has a laminated structure whose surface is covered with the above TCO and a substrate (1)
Extension of the long side of one of the long sides (3ae)
(3de) are provided, and the extended portions (3ae) to (3ce) of the first electrode films (3a) to (3c) having the first electrode films (3b) to (3d) divided on the right side are: First electrode film (3b) on the right
It is patterned in an L-shape bent toward (3d). When the first electrode films (3a) to (3d) are formed, the island-shaped region (3t) that operates as an output extraction terminal together with the extension (3de) of the right end first electrode film (3d) is formed on the left end first. It is provided close to the electrode film (3a).
第2図の工程では、上記第1電極膜(3a)〜(3d)の
延長部分(3ae)〜(3de)を含む基板(1)の周縁部分
を金属マスクで覆い、該マスクから露出した第1電極膜
(3a)〜(3d)上及びそれら第1電極膜(3a)〜(3d)
の隣接間隔部分(ab)、(bc)、(cd)の絶縁表面にSi
H4、Si2H6、SiF4等のシリコン化合物ガスを主原料ガス
とするプラズマCVD法或いは光CVD法により、アモルフア
スシリコン、アモルフアスシリコンカーバイド、アモル
フアスシリコンゲルマニウム、微結晶シリコン等を適宜
各層に配置したpin接合型、pn接合型、pi接合型、或い
はそれらのタンデム構造の半導体光活性層を含む半導体
膜(4)が基板(1)を約200〜300℃に加熱保持した状
態で形成される。In the step of FIG. 2, the peripheral portion of the substrate (1) including the extended portions (3ae) to (3de) of the first electrode films (3a) to (3d) is covered with a metal mask, and the second exposed from the mask. On the first electrode films (3a) to (3d) and their first electrode films (3a) to (3d)
Adjacent space (ab), (bc), (cd) insulated surface
Amorphous silicon, amorphous silicon carbide, amorphous silicon germanium, microcrystalline silicon, etc. are appropriately formed by a plasma CVD method or a photo CVD method using a silicon compound gas such as H 4 , Si 2 H 6 , SiF 4 as a main source gas. The semiconductor film (4) including the pin-type, pn-type, pi-type, or tandem-type semiconductor photoactive layer disposed in each layer is obtained by heating the substrate (1) to about 200 to 300 ° C. It is formed.
第3図の工程では、上記隣接間隔部分(ab)、(b
c)、(cd)が除去されることなく連続して配置された
半導体膜(4)と同じく、該半導体膜(4)上に各発電
領域(2a)〜(2d)毎に分割することなく第2電極膜
(5)が設けられる。第2電極膜(5)は各発電領域
(2a)〜(2d)毎に分割されてはいないものの、後工程
で各発電領域(2a)〜(2d)毎に分割されたとき、左隣
りに発電領域(2a)〜(2c)が存在する第2電極膜部分
には半導体膜(4)から露出した第1電極膜(3a)〜
(3c)の延長部分(3ae)〜(3ce)と結合すべく、基板
(1)の長辺の一方の周縁に向って延出した延長部分
(3be)〜(5de)及び出力端子となる島領域(3t)に延
びる延長部分(5ae)を持つ。斯る第2電極膜(5)は
この第2電極膜を受光面とすべく上記TCOからなり、下
層の半導体膜(4)への熱的ダメージを考慮して、約20
0〜300℃程度の加熱状態での電子ビーム蒸着法或いはス
パツタ法等により金属マスクを利用して上述のパターン
に形成される。このように、TCOは透光性を得るために
通常でも最低約200℃に基板(1)を保持する必要があ
る。従って、斯る工程では基板(1)の加熱状態に保持
するために金属マスクを利用しては微細パターンが得ら
れず、その結果第2電極膜(5)は各発電領域(2a)〜
(2d)毎に分割されていない。In the step of FIG. 3, the above-mentioned adjacent space portions (ab), (b)
c) Like the semiconductor film (4) which is continuously arranged without removing (cd), without dividing the power generation regions (2a) to (2d) on the semiconductor film (4). A second electrode film (5) is provided. Although the second electrode film (5) is not divided for each of the power generation regions (2a) to (2d), when divided for each of the power generation regions (2a) to (2d) in a later step, the second electrode film (5) is located on the left side. The first electrode films (3a) to (2a) exposed from the semiconductor film (4) are located on the second electrode film portions where the power generation regions (2a) to (2c) exist.
Extensions (3be) to (5de) extending toward one of the long sides of the long side of the substrate (1) to be combined with the extensions (3ae) to (3ce) of (3c) and an island serving as an output terminal It has an extension (5ae) extending to the region (3t). The second electrode film (5) is made of the above-mentioned TCO so that the second electrode film is used as a light receiving surface. In consideration of thermal damage to the underlying semiconductor film (4), about 20
The above-mentioned pattern is formed using a metal mask by an electron beam evaporation method or a sputter method in a heating state of about 0 to 300 ° C. As described above, the TCO usually needs to maintain the substrate (1) at a minimum of about 200 ° C. in order to obtain light transmission. Therefore, in such a process, a fine pattern cannot be obtained by using a metal mask to keep the substrate (1) in a heated state, and as a result, the second electrode film (5) is formed in each of the power generation regions (2a) to (2).
(2d) Not divided for each.
第4図の工程では、各発電領域(2a)〜(2d)の受光
面を保護すべくSiO2、Si3N4、SnO5、Ta2O5等の無機系の
透光性保護膜(6a)〜(6d)が基板(1)への加熱を施
すことなく、電子ビーム蒸着法、抵抗加熱蒸着法、CVD
法により形成される。斯る工程で注目すべきは、金属マ
スクを用いたマスキング法により所望形状の透光性保護
膜(6a)〜(6d)を選択的に得んとするところである。
即ち、透光性保護膜(6a)〜(6d)は基板(1)を加熱
することなく、従って半導体膜(4)やTCOの第2電極
膜(5)の成膜時よりも極めて低い温度で形成するため
に、金属マスクを用いても斯る金属マスクの熱膨張によ
る熱変形が回避されることから、隣接間隔部(ab)(b
c)(cd)を当該金属マスクで良好にマスキングするこ
とができ、膜の泌み出し(にじみ)の少ないパターンが
得られる。斯る透光性保護膜(6a)〜(6d)の成膜の結
果、第2電極膜(5)の隣接間隔部(ab)(bc)(c
d)、出力端子用の第1電極膜(3d)の延長部分(3de)
及び第2電極膜(5a)の延長部分(5ae)を含む島領域
(3t)が露出状態となる。In the fourth view of a step, the power generation region (2a) SiO 2 to protect the light-receiving surface of ~ (2d), Si 3 N 4, SnO 5, Ta 2 O 5 or the like inorganic translucent protective film of ( 6a) to (6d), without heating the substrate (1), using electron beam evaporation, resistance heating evaporation, CVD
It is formed by a method. It should be noted in such a process that the transparent protective films (6a) to (6d) having desired shapes are selectively obtained by a masking method using a metal mask.
That is, the light-transmitting protective films (6a) to (6d) do not heat the substrate (1), and therefore have a temperature much lower than that at the time of forming the semiconductor film (4) or the second electrode film (5) of TCO. Therefore, even if a metal mask is used, thermal deformation due to thermal expansion of the metal mask can be avoided, so that the adjacent space portions (ab) (b
c) (cd) can be favorably masked with the metal mask, and a pattern with less exudation (bleeding) of the film can be obtained. As a result of the formation of the light-transmitting protective films (6a) to (6d), the adjacent space portions (ab), (bc), and (c) of the second electrode film (5) were formed.
d), an extension (3de) of the first electrode film (3d) for the output terminal
The island region (3t) including the extension (5ae) of the second electrode film (5a) is exposed.
第5図の最終工程では、受光面保護のために設けられ
た上記透光性保護膜(6a)〜(6d)をマスクとして、TC
Oの第2電極膜(5)及び半導体膜(4)に対してエツ
チング作用のあるガス、例えばCF4ガスを用いたドライ
エツチングが施される。このドライエツチングの結果、
上記透光性保護膜(6a)〜(6d)から露出した第2電極
膜部分、即ち隣接間隔部(ab)(bc)(cd)及び左端第
2電極膜(5a)の延長部分(5ae)の先端がエツチング
除去され、次いで第2電極膜部分の除去により露出した
半導体膜部分が除去される。尚、本実施例にあっては斯
るドライエツチングの断面を示す第5図(B)から明ら
かな如く、半導体膜部分の除去は露出面側から基板
(1)方向に向う途中までとしているが、リーク電流を
より低減するためには基板に到達するまでエツチングを
施しても良い。In the final step of FIG. 5, the light-transmissive protective films (6a) to (6d) provided for
Dry etching is performed on the O second electrode film (5) and the semiconductor film (4) using a gas having an etching action, for example, CF 4 gas. As a result of this dry etching,
The second electrode film portion exposed from the translucent protective films (6a) to (6d), that is, the adjacent interval portions (ab), (bc), and (cd) and the extension portion (5ae) of the left end second electrode film (5a). Is removed by etching, and then the semiconductor film portion exposed by removing the second electrode film portion is removed. In this embodiment, as is apparent from FIG. 5 (B) showing a cross section of the dry etching, the removal of the semiconductor film portion is performed from the exposed surface side to the middle in the direction of the substrate (1). In order to further reduce the leakage current, etching may be performed until the current reaches the substrate.
このようにしてエツチングされた第2電極膜(5a)〜
(5d)は各発電領域(2a)〜(2d)毎に分割されること
となり、第1電極膜(3a)(3b)(3c)及び第2電極膜
(5b)(5c)(5d)の各延長部分(3ae)(5be)(3b
e)(5ce)、(3ce)(5de)の重畳の結果、当該発電領
域(2a)〜(2d)の光電変換出力は出力端子(3t)(3d
e)から電気的に相加した状態で出力される。The second electrode film (5a) thus etched is formed.
(5d) is divided for each of the power generation areas (2a) to (2d), and the first electrode films (3a) (3b) (3c) and the second electrode films (5b) (5c) (5d) Each extension (3ae) (5be) (3b
e) As a result of the superposition of (5ce), (3ce) and (5de), the photoelectric conversion outputs of the power generation areas (2a) to (2d) are output terminals (3t) (3d
It is output in a state electrically added from e).
尚、最終工程におけるドライエツチングの際、マスク
として作用する透光性の保護膜(6a)〜(6d)表面は、
プラズマに曝されることから若干粗面に加工されるもの
の、逆に当該保護膜(6a)〜(6d)は受光面を構成する
ことから直進入射光を散乱光として半導体膜(4)に導
入することができ、その結果斯る入射光を半導体膜
(4)中に封じ込めることによる所謂デクスチエア効果
を期待することができる。In dry etching in the final step, the surfaces of the light-transmitting protective films (6a) to (6d) acting as a mask are:
Since the surface is exposed to the plasma, the surface is slightly roughened. On the contrary, since the protective films (6a) to (6d) constitute the light receiving surface, the straight incident light is introduced into the semiconductor film (4) as scattered light. As a result, a so-called dextiair effect can be expected by confining such incident light in the semiconductor film (4).
(ト) 発明の効果 本発明製造方法は以上の説明から明らかな如く、第2
電極膜の各発電領域毎に分割するエツチングの際、マス
クとして作用する保護膜は低温状態でのマスキング法に
より形成されているので、隣接間隔部の幅を縮小しても
斯る隣接間隔部において露出した第2電極を確実に除去
し得、従って第2電極膜同士の短絡事故や光電変換に寄
与しない無効領域の増大のみならず製造コストの大幅な
上昇を招くことなく直列接続形態の光起電力装置を製造
することができる。(G) Effect of the Invention As is clear from the above description, the production method of the present invention is the second method.
At the time of etching for dividing the electrode film into each power generation region, the protective film serving as a mask is formed by a masking method in a low temperature state. The exposed second electrode can be surely removed, so that not only a short circuit between the second electrode films and an increase in an ineffective region that does not contribute to photoelectric conversion, but also a large increase in manufacturing cost without incurring a significant increase in manufacturing cost. A power device can be manufactured.
更に、第2電極膜の隣接間隔部分のエツチングの際、
不要な半導体膜部分を除去することができるので、リー
ク電流の低減が図れると共に、ドライエツチングを用い
ることによって、保護膜表面が僅かながらも粗面化され
るので、斯る保護膜を光照射面とすると、光封じ込めに
よる光電変換効率の上昇が更に期待できる。Further, when etching the adjacent space portion of the second electrode film,
Since unnecessary semiconductor film portions can be removed, leakage current can be reduced, and the surface of the protective film can be slightly roughened by using dry etching. Then, an increase in photoelectric conversion efficiency due to light confinement can be further expected.
第1図乃至第3図、第4図(A)及び第5図(A)は本
発明製造方法を工程別に説明するための上面図、第4図
(B)及び第4図(C)は同図(A)のB−B′線断面
図及びC−C′線断面図、第5図(B)及び第5図
(C)は同図(A)のB−B′線断面図及びC−C′線
断面図、第6図及び第7図は従来の製造方法を工程別に
説明するための上面図、第8図(A)及び第8図(B)
は従来の欠点を説明するための一つの隣接間隔部の拡大
断面図、を夫々示している。 (1)……基板、(2a)〜(2d)……発電領域、(3)
(3a)〜(3d)……第1電極膜、(4)(4a)〜(4d)
……半導体膜、(5)(5a)〜(5d)……第2電極膜、
(6a)〜(6d)……透光性保護膜。FIGS. 1 to 3, FIGS. 4 (A) and 5 (A) are top views for explaining the manufacturing method of the present invention for each step, and FIGS. 4 (B) and 4 (C) are FIG. 5A is a sectional view taken along line BB ′ and CC ′, and FIGS. 5B and 5C are sectional views taken along line BB ′ in FIG. FIGS. 6 and 7 are cross-sectional views taken along the line CC ', FIGS. 6 and 7 are top views for explaining the conventional manufacturing method for each process, FIGS. 8 (A) and 8 (B).
2 are enlarged cross-sectional views of one adjacent space portion for explaining a conventional defect. (1) ... substrate, (2a) to (2d) ... power generation area, (3)
(3a) to (3d): First electrode film, (4) (4a) to (4d)
... semiconductor film, (5) (5a) to (5d) ... second electrode film,
(6a) to (6d): Transparent protective film.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−188285(JP,A) 特開 昭59−172274(JP,A) 特開 昭55−107276(JP,A) ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-188285 (JP, A) JP-A-59-172274 (JP, A) JP-A-55-107276 (JP, A)
Claims (4)
に、該発電領域から上記基板の周縁に向って延出した延
長部分を有する第1電極膜を分割配置し、上記第1電極
膜延長部分を除いて発電領域の第1電極膜上及び該第1
電極膜の隣接間隔部における絶縁表面上に光活性層を含
む半導体膜を被着すると共に、当該半導体膜から露出し
た隣接する発電領域の第1電極膜延長部分上に延在する
延長部分を備えた第2電極を、上記隣接間隔部を含む半
導体膜上に積層し、更に少なくとも発電領域毎の第2電
極膜及びその延長部分を覆い隣接間隔部に位置する第2
電極膜部分を露出せしめる保護膜を、上記半導体膜及び
第2電極膜の成膜温度より低温でのマスキング法を用い
て選択的に形成した後、当該保護膜をマスクとして上記
隣接間隔部に露出した第2電極膜部分をエツチングし、
第2電極膜を各発電領域毎に分割することを特徴とした
光起電力装置の製造方法。A first electrode film having an extended portion extending from the power generation region toward the periphery of the substrate for each of a plurality of power generation regions on the insulating surface of the substrate; Except for the portion, on the first electrode film of the power generation region and the first electrode film
The semiconductor device includes a semiconductor film including a photoactive layer on an insulating surface at an interval between adjacent electrode films, and includes an extension portion extending over the first electrode film extension portion of an adjacent power generation region exposed from the semiconductor film. The second electrode is laminated on the semiconductor film including the adjacent space, and further covers at least the second electrode film for each power generation region and an extended portion thereof, and the second electrode film is located at the adjacent space.
After selectively forming a protective film for exposing the electrode film portion by using a masking method at a temperature lower than the film forming temperature of the semiconductor film and the second electrode film, the protective film is exposed to the adjacent space using the protective film as a mask. Etching the second electrode film portion,
A method for manufacturing a photovoltaic device, wherein the second electrode film is divided for each power generation region.
2電極膜部分のエツチングは、当該第2電極膜部分の除
去により露出した半導体膜部分をその露出面側から基板
方向に向って少なくとも一部除去する工程を含む請求項
1記載の光起電力装置の製造方法。2. Etching of the second electrode film portion in the adjacent space portion using the protective film as a mask is performed by removing the semiconductor film portion exposed by removing the second electrode film portion from the exposed surface side toward the substrate. The method for manufacturing a photovoltaic device according to claim 1, further comprising a step of removing at least a part of the photovoltaic device.
ライエツチングである請求項1又は2記載の光起電力装
置の製造方法。3. The method for manufacturing a photovoltaic device according to claim 1, wherein the etching using the protective film as a mask is dry etching.
り、当該保護膜から光照射が施される請求項1、2又は
3記載の光起電力装置の製造方法。4. The method for manufacturing a photovoltaic device according to claim 1, wherein the protective film and the second electrode film are translucent, and light is applied from the protective film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63010011A JP2598936B2 (en) | 1988-01-20 | 1988-01-20 | Method for manufacturing photovoltaic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63010011A JP2598936B2 (en) | 1988-01-20 | 1988-01-20 | Method for manufacturing photovoltaic device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01184960A JPH01184960A (en) | 1989-07-24 |
JP2598936B2 true JP2598936B2 (en) | 1997-04-09 |
Family
ID=11738455
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63010011A Expired - Lifetime JP2598936B2 (en) | 1988-01-20 | 1988-01-20 | Method for manufacturing photovoltaic device |
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---|---|
JP (1) | JP2598936B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101079614B1 (en) * | 2010-04-09 | 2011-11-03 | 주성엔지니어링(주) | Method for manufacturing of thin film type solar cell |
KR101118929B1 (en) * | 2010-09-13 | 2012-02-27 | 주성엔지니어링(주) | Apparatus and method for manufacturing of thin film type solar cell |
KR101137700B1 (en) * | 2010-09-01 | 2012-04-25 | 주성엔지니어링(주) | Apparatus and method for manufacturing of thin film type solar cell |
-
1988
- 1988-01-20 JP JP63010011A patent/JP2598936B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101079614B1 (en) * | 2010-04-09 | 2011-11-03 | 주성엔지니어링(주) | Method for manufacturing of thin film type solar cell |
KR101137700B1 (en) * | 2010-09-01 | 2012-04-25 | 주성엔지니어링(주) | Apparatus and method for manufacturing of thin film type solar cell |
KR101118929B1 (en) * | 2010-09-13 | 2012-02-27 | 주성엔지니어링(주) | Apparatus and method for manufacturing of thin film type solar cell |
Also Published As
Publication number | Publication date |
---|---|
JPH01184960A (en) | 1989-07-24 |
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