JP2598916B2 - Drawing equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drawing device using a refresh memory suitable for application to a graphic display terminal device for teletext.

2. Description of the Related Art A drawing apparatus using a refresh memory used in a graphic display terminal device for teletext broadcasting, which has recently started broadcasting, is usually configured as shown in FIG.

That is, in this type of drawing apparatus, a bit map type refresh memory 1 composed of n layers is used, and a refresh device 1 such as a CPU (hereinafter simply referred to as a CPU) 2 is connected to the refresh memory 1 through an address bus 4. Predetermined drawing data is drawn to the specified address via the data bus 3.

The drawing of the drawing data is performed in the plane type, and the output is also output in the plane type.

One dot on the display screen is the refresh memory 1
In a pack-type memory configuration in which a bit string in one address indicates color information corresponding to the above address, the drawing speed is increased. However, the circuit at the time of display reading becomes complicated.

[Problems to be Solved by the Invention] By the way, the drawing apparatus using the refresh memory as described above has the following requirements.

Requirement (1) Able to perform high-speed drawing by distinguishing foreground color (FG) and background color (BG) by binary dot pattern information.

This is a function required for drawing characters of teletext.

Requirement (2) The foreground color and the background color are specified, and the foreground color and the background color are drawn at an arbitrary address with binary dot information.

This is, for example, a function required in drawing a figure of teletext.

Requirement (3) Able to be drawn with arbitrary data in an arbitrary layer of the refresh memory 1, that is, a claim memory for specifying a color.

This is a function required, for example, in telegraphic drawing of teletext.

In the conventional drawing apparatus 10 shown in FIG. 6, in response to the request (1), the drawing address and the drawing data must be given to the refresh memory 1 for each dot. And that it takes time for data processing.

In response to the request (2), in the graphic drawing, the processing of the line type generation pattern is performed by a device such as a CPU.

For request (3), when only data of a certain layer is to be drawn, it is necessary to read all bits (for one dot) once, process only necessary bits, and draw all bits again. Met.

As described above, in the conventional drawing apparatus 10, the request (1)
All of the requirements (3) have a drawback that high-speed drawing processing is impossible.

In view of the above, the present invention has solved such a conventional problem, and proposes a drawing apparatus using a refresh memory capable of performing high-speed drawing.

[Technical Means for Solving the Problems] In order to solve the above problems, in the present invention,
a refresh memory for use as an n-layer (n is an integer) plane memory, wherein each of the plane memories is constituted by a dual-port memory, while a first latch circuit for latching drawing data of a background color; A second latch circuit for latching drawing data, a drawing layer specifying latch circuit for latching drawing layer specifying data for selecting a plane memory to be a drawing target in response to a request for character drawing, figure drawing, color drawing, etc. A selection circuit for inputting dot pattern designating data, and selecting one of the first and second latch circuits based on the data. The plane memory designated by the drawing layer designating latch circuit When writing the drawing data given from the first and second latch circuits, it operates as a pack-type refresh memory accessed simultaneously, When the drawing data is read, it is configured to operate as a plane type refresh memory using a serial output port.

[Operation] In this configuration, in response to the above-mentioned request (1) or request (2), the data for specifying the entire plane memory layer is previously stored in the drawing layer specifying latch circuit, and the background color is stored in the first latch circuit. The drawing data is latched in the second latch circuit with the drawing data of the foreground color. Then, when the binary dot pattern data (0, 1) is given to the selection circuit, the selection circuit selects the first and second latch circuits according to the dot pattern data. In synchronization with this, when each dot of the refresh memory is designated by the drawing address, the background color and the foreground color are distinguished for all the plane memories (n layers) according to the binary dot pattern. Will be drawn. That is, if the background color, the foreground color, and the dot pattern are predetermined, the drawing data is written to the refresh memory at high speed without the intervention of the CPU. In addition, since the reading of the drawing data is performed using the serial output port of each plane memory, high-speed drawing is performed without being restricted by the writing time of the drawing data.

In response to the above-mentioned request (3), data for designating a partial layer of the plane memory is previously latched in the drawing layer designation latch circuit, and the layer of the plane memory to be rendered is designated. High-speed drawing processing is performed as in the cases of (1) and (2).

Embodiment Next, an example of a drawing apparatus using a refresh memory according to the present invention will be described in detail with reference to FIG.

In FIG. 1, reference numeral 11 denotes a bit map type refresh memory, which is composed of n layers (11A to 11N). Details will be described later.

Reference numeral 20 denotes a device such as a CPU (hereinafter referred to as a CPU) which generates data to be drawn in the refresh memory 11, generates a drawing address thereof, and supplies various information such as supplying necessary signals to necessary devices. An intelligent device to give.

The n-bit configuration color designation data sent from the CPU 20 is supplied to first and second latch circuits 21 and 22 having an n-bit configuration.

The first latch circuit 21 is a circuit for latching the color designation data of the background color, and the second latch circuit 22 is
This is a circuit for latching foreground color designation data.

The drawing data is further supplied from the CPU 20 to a shift register 24 composed of m bits via a data bus.

The shift register 24 is a register for temporarily storing the display dot pattern, and such data is stored in the CP.
Supplied from U20. The shift register 24 corresponds to the selection circuit in the claims.

The address generation unit 25 for the refresh memory 11 is supplied with address data for starting drawing from the CPU 20 via the address bus, and based on this, the drawing address of the next dot to be drawn on the refresh memory 11 is generated.

Reference numeral 26 denotes a drawing clock generator, which receives information on the number of drawing clocks sent from the CPU 20, and
This is a device for generating a drawing clock based on the information on the number of drawing clocks.

The drawing layer designating third latch circuit 30 composed of n bits is supplied with the drawing layer designating data from the CPU 20 via the data bus. When one dot on the display screen is composed of a plurality of bits, this is data for designating which bit data is to be rewritten among the plurality of bits.

One of the first and second latch circuits is selected by the data in the shift register 24. Therefore, data for distinguishing whether the drawing data represents the background color or the foreground color is stored in the shift register 24.

In the embodiment, the data of the shift register 24 is represented as “1” for the foreground color and “0” for the background color.

As the refresh memory 11, a dual port memory is used as a bitmap type memory.

It has normal DRAM memory cells 11A-11N functioning as a plane memory as shown in FIG.
Bit line mask register 15 and shift register 13A
~ 13N in combination.

Each data of the DRAM memory cells 11A to 11N is transferred to the shift registers 13A to 13N according to an external shift register transfer timing signal. Then, in synchronization with an external serial dot clock, the shift registers 13A to 13N
Each serial data is sent to serial output port 14 (14A ~ 14
N).

The drawing data by the first and second latch circuits 21 and 22 having the n-bit configuration is drawn through the random access port 12, and the serial data output from the serial output port 14 is subjected to necessary signal processing. Above, it is input to a display device (not shown).

In this manner, the refresh memory 11
Since the dots are composed of a plurality of bits of one address, the first and second latch circuits 21 and 22 can draw a plurality of bits (n bits) of one dot at a time. It is composed of n layers of plane memories 11A to 11N.

That is, when viewed from the CPU 20, the address is each layer 1 to 1.
n are the same if they are at the same position in n.
Each layer can be divided in the bit direction by 1,22.

For this reason, the refresh memory 11 using the dual port memory operates as a packed refresh memory using the random access port 12 at the time of writing the drawing data, and the serial output port 14 at the time of reading the drawing data. It will operate as the used plane refresh memory.

By the way, the drawing functions for the refresh memory 11 include the requests (1) to (3) as described above. If reprinted, it is as follows.

Requirement (1) To draw at high speed by distinguishing the foreground color and the background color using binary dot pattern information.

This is a function required for drawing characters of teletext.

In response to the request (1), the CPU 20 previously specifies all-bit drawing for the third latch circuit 30 for specifying the drawing layer, and the first latch circuit 21 has a refresh memory corresponding to the background color. The second latch circuit 22 stores a color pattern to be written in the refresh memory 11 corresponding to the foreground color.
The color pattern to be written is set respectively.

Then, when actually drawing on the refresh memory 11, the CPU 20 transfers the initial value of the drawing address of the refresh memory 11 to the address generator 25 via the address bus.

At the same time, pattern data of x dots (x ≦ m) is transferred to the shift register 24. Also, the drawing clock generator
26 is given information that x dots are to be drawn.

As a result, in the drawing clock generator 26, x drawing clocks are formed to draw x dots,
This is supplied to the shift register 24 and the address generator 25.

As a result, one of the first and second latch circuits 21 and 22 is selected by the data output from the shift register 24, and the selected latch output is used as the drawing data of the refresh memory 11.

On the other hand, the drawing address of the refresh memory 11 is calculated from the initial value (drawing start address) supplied from the CPU 20 by the address generator 25, the size of the character, and the size of the refresh memory 11, and the drawing address of the next dot is calculated. Is output.

In this manner, each time the drawing clock is obtained, the shift register 24 shifts one bit at a time, and one of the latch circuits 21 and 22 is selected based on the output data and stored in the selected latch circuit. The drawing data is used as drawing data for the refresh memory 11.
Then, the drawing address generated by the address generation unit 25 is
The selected drawing data is drawn.

This drawing operation is continued continuously for the number of dots initially set in the shift register 24, that is, x times.

In this case, the drawing address is an n-layer plane memory 11A.
1111N will be specified at the same time. As a result, if the initial address of the drawing, the size of the drawing rectangle, the foreground color, the background color, and the dot pattern data are known in advance, high-speed drawing can be performed on the refresh memory 11 without the intervention of the CPU 20.

FIG. 4 shows an example of this drawing, where n =
4 shows an example of character drawing when x = 8.

It is assumed that green of full brightness is specified as the background color, yellow of half brightness is specified as the foreground color, and eight data as shown are specified as the dot pattern. Further, the plane memory 11A is a plane for storing drawing data of red, and similarly, 11B is a plane memory for drawing green, 11C is for blue, and 11D is a plane memory for drawing a luminance level. I do.

In the case of the refresh memory 11 using such a four-layer plane memory, if the pattern data stored in the shift register 24 is as shown in the figure, the first control output from the shift register 24 is performed. The second latch circuit 22 is selected according to the data (LSB data).

At this time, the data of each bit is simultaneously drawn on the corresponding plane memories 11A to 11D.

The next control data output from the shift register 24 is 0
Therefore, in this case, the first latch circuit 21 is selected, whereby the data stored in the first latch circuit 21 is simultaneously drawn at the addresses of the plane memories 11A to 11D. Become.

Hereinafter, in a similar process, the drawing data of the foreground color or the background color is simultaneously drawn on each of the plane memories 11A to 11D. That is, when writing the drawing data, the refresh memory 11 operates as a pack-type refresh memory.

Requirement (2) A foreground color and a background color are specified, and the CPU 20 generates a binary dot information for an arbitrary address to draw the foreground color and the background color separately.

This is, for example, a function required in drawing a figure of teletext.

In response to the request (2), similarly to the request (1), all bit drawing is specified in advance to the third latch circuit 30 for specifying the drawing layer, and the first latch circuit 21 The color designation data to be written in the refresh memory 11 corresponding to the background color is set, and the color designation data to be written in the refresh memory 11 corresponding to the foreground color is set in the second latch circuit 22, respectively.

Y dot to be drawn in shift register 24 (y> 0)
(For example, a pattern such as a solid line, a dashed line, and a broken line) is set.

At this time, the shift register 24 has a setting data holding register and a y-dot counter, and when drawing is performed for y dots, the initial data from the setting data holding register is reset in the shift register 24.

The drawing address of an arbitrary figure is calculated by the CPU 20, and when the calculated drawing address is output to the address generating unit 25, a predetermined signal is sent to the drawing clock generating unit 26 so that the drawing clock generates one clock in synchronization with this. Is output.

With this setting, when the CPU 20 outputs the drawing address to the address generator, it simultaneously outputs a predetermined signal to the drawing clock generator 26. The drawing clock generator 26 stores 1 dot of data in the refresh memory.
To draw at 11, shift register 24 is shifted one bit.

Based on the output, one of the latch circuits 21 and 22 is selected, and the selected data becomes drawing data.

The address generator 25 outputs the drawing address input when the drawing clock is generated as it is.

In this manner, the CPU 20 generates a drawing address of an arbitrary figure on the refresh memory 11 and stores the line type pattern in the shift register 24, so that an arbitrary line type pattern Can be drawn at the position.

Requirement (3) Able to be drawn with arbitrary data on an arbitrary layer of the refresh memory 11.

This is a function required for, for example, photographic drawing of teletext.

For this request (3), the bit write mask register 15 of the dual port memory shown in FIG. 2 is used.

FIG. 3 shows an example of a write timing chart of the random access port 12 in the dual port memory.

Usually, in DRAM, the address is time-division multiplexed,
The lower address is recognized at the falling edge of the RAS (row address strobe) signal, and the upper address is recognized at the falling edge of the CAS (column address strobe) signal.

In the dual-port RAM, the drawing layer is specified by falling data of the RAS signal.

Therefore, when the RAS signal falls, the third latch circuit 30
To the data bus of the DRAM, and output the n-bit latch data selected when the CAS signal falls, that is, the output of the color designation data indicating the background color or the foreground color, to the plane memories (DRAMs) 11A to 11N, respectively. What is necessary is just to input to a data bus.

In this case, the data at the time of the falling edge of the RAS signal is set in the bit write mask register 15 of the dual port memory, and the drawing bit is selected in the dual port memory.

For this reason, when drawing is to be performed on an arbitrary layer, the layer to be drawn is first specified in the third latch circuit 30 for specifying the drawing layer, and then the drawing is performed in the same manner as in the case of the requests (1) and (2) do it.

In the case where one layer is drawn on each layer in order to express a very complicated color, all bits 0 are stored in the first latch circuit 21.
All bits 1 are designated in the second latch circuit 22, and only the bit corresponding to the layer to be rendered is activated in the third latch circuit 30 for designating the rendering layer. Further, the drawing data may be set by the shift register 24.

For example, FIG. 5 shows an example where n = 4 and x = 8.

As shown in the figure, if it is assumed that the drawing layer designating data as shown is latched in the third latch circuit 30, only the plane memory 11B as the second layer is selected, and No plane memory is selected. That is, the drawing permission signal is output from the third latch circuit 30 only to the plane memory 11B.

In this state, the first and second latch circuits 21 and 22
If the drawing data as shown in the drawing is latched, the latch circuits 21 and 22 are sequentially selected according to the control data from the shift register 24, and the selected drawing data is stored in the plane memory of the second layer. It will be drawn on 11B.

[Effects of the Invention] As described above, in the present invention, a dual port memory is used as a bitmap type refresh memory, and the first and second latch circuits which respectively latch drawing data of a background color and a foreground color are provided. , A drawing layer specifying latch circuit for latching drawing layer specifying data for selecting a plane memory to be drawn according to a request for character drawing, graphic drawing, color drawing, etc., and dot pattern specifying data, Based on this data, the first and second
A selection circuit for selecting one of the latch circuits is provided,
This allows the refresh memory to operate as a pack-type refresh memory when writing drawing data, and to operate as a plane-type refresh memory when reading drawing data.
The drawing data can be written at high speed in response to any of the above-mentioned requests (1) to (3).

As described above, the high-speed drawing can be easily performed. As a result, according to the present invention, the drawing function required in a graphic display terminal device such as a character broadcast having a bitmap type refresh memory can be sufficiently satisfied. it can.

Therefore, the drawing apparatus according to the present invention is extremely suitable for application to the above-described terminal apparatus for displaying graphics such as teletext.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of a drawing apparatus using a refresh memory according to the present invention, FIG. 2 is a system diagram of an example of a dual-port memory used as a refresh memory, and FIG. Waveform diagram,
4 and 5 show an example of writing of drawing data, and FIG. 6 is a system diagram of a drawing device using a conventional refresh memory. 10 Drawing apparatus 11 Bitmap refresh memory 11A-11N Plane memory 12 (12A-12N) Random access port 13A-13N Serial data shift register 14 (14A-14N) Serial output Port 20 Device such as CPU 21 Latch circuit for storing background color drawing data 22 Latch circuit for storing foreground drawing data 30 Latch circuit for specifying drawing layer 24 Shift register for specifying dot pattern 25 ... Drawing address generator 26 ... Drawing clock generator

Claims (1)

(57) [Claims] 1. A first latch circuit having a refresh memory used as an n-layer (n is an integer) plane memory, wherein each of the plane memories is constituted by a dual-port memory, while latching drawing data of a background color. A second latch circuit for latching drawing data of a foreground color, and a drawing layer for latching drawing layer designation data for selecting a plane memory to be drawn in response to a request for character drawing, figure drawing, color drawing or the like A latch circuit for designation and dot pattern designation data are input, and the
A selection circuit for selecting one of the first and second latch circuits, wherein the plane memory specified by the drawing layer specifying latch circuit is used when writing the drawing data given from the first and second latch circuits. Is configured to operate as a pack-type refresh memory accessed simultaneously, and to operate as a plane-type refresh memory using a serial output port when reading out drawing data.