JP2595088B2 - Character / pattern storage and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial application field> The present invention relates to a character / pattern storage bond capable of storing an image pattern such as a title character or a figure and outputting it over other video. It is.

<Prior Art> In recent years, with the spread of home VTRs, the demand for home video cameras has increased, and demands for multifunctional and editing functions of home video cameras have increased.

Among these functions, the imposition for inserting a title and the like, the terrorist, and the like are one of the functions that are particularly demanded.

Hereinafter, a conventional telop device for inserting a title or the like will be described with reference to FIG. In FIG.
(1) is a video signal input terminal, (2) is a detection circuit that extracts character / pattern information, (3) is a synchronization separation circuit that separates a synchronization signal from a video signal input, (4) is a serial-parallel conversion circuit, 5) is a parallel-serial conversion circuit,
(6) is a memory, (7) is an oscillation circuit of a reference clock,
(8) and (9) are vertical counters and horizontal counters for instructing addresses of the respective memories (6), and (10) are vertical counters (10) based on a synchronization signal of a synchronization separation circuit (3) and a reference clock of an oscillation circuit (7). 8) a frequency dividing circuit for controlling the up / down timing of the horizontal counter (9);
(11) is a controller, (12) is a command signal of a user such as a switch, (13) is a character superimposing circuit for superimposing character / pattern information with another video signal, and (14) is a video signal output terminal. .

Here, the controller (11) receives the user's command signal (12) and the synchronization signal of the synchronization separation circuit (3), and receives a memory (6), a serial / parallel conversion circuit (4), a parallel / serial conversion circuit (5), A horizontal counter (9), a vertical counter (8), and an oscillation circuit (7) are controlled.

First, the main flow of the character / pattern signal will be described. The video signal input from the video signal input terminal (1) is converted into a digital signal by the detection circuit (2) at the same time that a synchronization signal is generated by the synchronization separation circuit (3). This digital signal is converted into a digital signal (pixel data) of 8 bits or the like by the serial / parallel conversion circuit (4) and stored in the memory (6). Also, a digital signal of 8 bits or the like which is information of characters and patterns stored in the memory (6) is converted into a serial digital signal by a parallel-serial conversion circuit (5) and is superimposed on an original video signal by a character superimposition circuit (13). And output to the video output signal (14).

In order to realize the above operation, a reference clock is generated by the oscillation circuit (7) of the present telop device, and this reference clock is supplied to the serial / parallel conversion circuit (4) and the parallel / serial conversion circuit (5) to convert the reference clock. give. This clock is supplied to a horizontal counter (9), which is an addressing counter for the lower bits of the memory (6), and performs addressing of the memory (6). The carry signal of the horizontal counter (9) is supplied to a vertical counter (8), which is a higher-order bit addressing counter of the memory (6), and addresses the memory (6). Further, the controller (11) is instructed to write or read a character / pattern by a command signal (12) from a user. Accordingly, the controller (11) operates or disables the memory (6), the serial / parallel conversion circuit (4), the parallel / serial conversion circuit (5), the horizontal counter (9), the vertical counter (8), and the oscillation circuit (7). Set to operation state. The controller (11) resets the horizontal counter (9) and the vertical counter (8) at the start of one field with reference to the synchronization signal supplied by the synchronization separation circuit (3), and performs pattern and character Is correlated with the address of the memory (6).

<Problems to be Solved by the Invention> As described above, the conventional character / pattern storage / playback apparatus has been described. In the conventional character / pattern storage / playback apparatus, character / pattern information such as that used in a movie or video broadcast is stored. I can't scroll horizontally.

SUMMARY OF THE INVENTION An object of the present invention is to provide a character / pattern information which can be horizontally scrolled in a home video camera or VTR as in a movie or a television broadcast.
An object of the present invention is to provide a pattern storage / reproduction device.

<Means for Solving the Problem> A character / pattern storage / reproducing apparatus according to claim 1 of the present invention comprises: means for digitizing a first input video signal to form character / pattern information; A memory means for storing information based on horizontal and vertical synchronization signals, reading character / pattern information from the memory means, and adding and superimposing the information on a new second input video signal to output a video signal And a read address obtained by adding a predetermined offset to a write address of character / pattern information to said memory means, and said character / pattern for said second input video signal based on a horizontal synchronizing signal and a vertical synchronizing signal. An offset addressing circuit for controlling the horizontal and vertical position of the start point of reading information from the memory means; A controller for instructing the offset address designating circuit with N kinds of read start points corresponding to a plurality of bits (N) that can be read from the memory means at one time; and a horizontal synchronizing signal and a vertical synchronizing signal inputted from the controller. A decoding circuit for generating a timing signal corresponding to the N types of read start points based on the instruction from the controller, and selecting the N types of timing signals generated by the decoding circuit based on an instruction from the controller; A selector for switching a horizontal read start point for the second input video signal.

Further, the character / pattern storage / reproducing apparatus according to claim 2 of the present invention further comprises the step of adding and superimposing the character / pattern information read from the memory means on the second input video signal. A switch circuit for forcibly switching an area other than the read range to only the second input video signal and outputting the signal is provided.

<Operation> In the character / pattern storage / reproduction device according to claim 1 of the present invention, an offset address designating circuit, a decoding circuit,
And a selector to add an offset address in synchronization with the video signal to the horizontal counter and vertical counter that specify the address of the memory from the controller so that the address can be read from it and read from the memory at once. Number of bits that can be output (N)
Are finely adjusted.

In the character / pattern storage / reproduction device according to the second aspect, a switch circuit is provided so that data other than the stored range is not read by a read masking signal generated according to a read address.

Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the attached drawings.

FIG. 1 is a block diagram showing an embodiment of a character / pattern storage / reproduction device according to the present invention. In FIG.
(1) is a video signal input terminal, (2) is a detection circuit for extracting character and pattern information, (3) is a sync separation circuit for separating a sync signal from a video signal input, (4) is a serial-parallel conversion circuit, 5) is a parallel-serial conversion circuit,
(6) is a memory, (7) is an oscillation circuit of a reference clock,
(8) and (9) are vertical counters and horizontal counters for instructing addresses of the respective memories (6), and (10) are vertical counters (10) based on a synchronization signal of a synchronization separation circuit (3) and a reference clock of an oscillation circuit (7). 8) a frequency divider circuit for controlling the up / down timing of the horizontal counter (9); (12)
Is a user command signal such as a switch, (13) is a frequency dividing circuit that superimposes character / pattern information on another video signal, (1)
4) is a video signal terminal. The configuration so far is the same as that of the conventional device (FIG. 5).

(15) an offset address designating circuit for designating a read address by adding a predetermined offset to a write address at the time of writing character / pattern information in the memory (6), based on the synchronization signal The read start point of the memory (6) for the second input video signal that captures the subject later is controlled. This control will be described later.

(16) is a read masking signal for preventing data other than the stored range from being read, and (31) is a read masking signal for reading a serial digital signal which is character / pattern information output from the parallel / serial conversion circuit (5). This is a switch circuit that is turned on and off by (16).

(11) receives the command signal (12) and the synchronization signal from the synchronization separation circuit (3) and increases or decreases the count values of the vertical counter (8), the horizontal counter (9), and the offset address designation circuit (15). Stepping in the down direction or controlling the timing of resetting them, and further controlling switching between reading and writing of the memory (6);
A controller for instructing the offset address designating circuit (15) with eight kinds of read start points in the horizontal direction for the title image corresponding to a plurality of bits (N) that can be read at a time from the memory (6), for example, eight; (32)
Is a decoding circuit for generating timing signals corresponding to eight kinds of read start points based on the horizontal synchronizing signal (H) and the vertical synchronizing signal (V) inputted from the controller (11), and (33) is a decoding circuit (32) ) Is a selector for selecting the timing signal generated in step (1) in accordance with an instruction from the controller (11) and switching the horizontal read start point of the title image with respect to the second input video signal. Equipment (17)
Is composed.

FIG. 2 shows an example in which the character / pattern storage / reproduction device of the present invention is used for a video camera.
9) is the title picture to be inserted, (20) is the lens, (21)
Denotes an image sensor, (22) denotes a signal processing circuit, and (23) denotes a monitor television.

FIG. 3 shows an H synchronization signal for controlling a count value of a horizontal counter (9) when a title image is recorded, a video image of a subject is superimposed, and the title image is horizontally scrolled, and an offset address designating circuit. 15 shows an example of a preset value from (15), a readout masking signal, and an image on a monitor television.

In FIG. 2, a title picture to be inserted is photographed in advance, passed through a lens (20), a video signal is taken out by an image sensor (21), a video signal is synthesized from the video signal by a signal processing circuit (22), and a character・ Input to the pattern storage and playback device.

The input video signal is converted into a digital signal by a detection circuit (2) at the same time as a synchronization signal is created by a synchronization separation circuit (3), as in the conventional character / pattern storage / playback apparatus. The digital signal is converted into a digital signal of 8 bits or the like by the serial / parallel conversion circuit (4) and stored in the memory (6). The controller (11) controls the horizontal counter (9), 1
It is assumed that the vertical counter (8) is preset at the starting point of the vertical scanning.

When the title image (19) is stored, the subject (18) is photographed, and the video signal is input to the character / pattern storage / reproduction device. When a video signal of a subject is input, the controller (11) performs one horizontal scan (hereinafter, referred to as H) based on the synchronization signal generated by the synchronization separation circuit (3).
The vertical counter (8) is preset at the starting point of the effective image of the horizontal scanning (9) and the vertical scanning (hereinafter, referred to as V) at the starting point of the effective image of the pattern, the pattern in the screen, the character position and the memory (6). ) Is correlated with the address of the title image (19) stored in ().

In the following, referring also to FIG.
The horizontal scroll in the case of using a memory of 64 × 8 bits (bit) will be described.

FIG. 4 is a diagram showing the relationship between the start of a valid image and the read start point.

In response to a command from the controller (11), the offset addressing circuit (15) is synchronized with the vertical scanning (V).
The offset address is preset to the horizontal counter (9) so that the start point of the effective image of the horizontal scanning (H) is shifted by one pixel to the read start point. Here, the memory (6) has a 64 × 8 bit configuration as described above,
If an offset address in bit units is preset, the same offset address will be preset during eight vertical scans (V). The selector (33) has another 3-bit control signal (X) from the controller (11),
(Y) and (Z) are input, and one of eight types of timing signals generated by the decoding circuit (32) is selected in accordance with an instruction from the controller (11). Is switched to any one of the eight types. As a result, the fourth
As shown, in the effective image area, the title image (19)
Move pixel by pixel. However, 1-1 in FIG. 4 is 8-bit data of the first pixel of address 1, 2-3 is address 2
3 shows 8-bit data of the third pixel.

The state of each point when the horizontal scroll is performed is as shown in FIG. 3, but in the state of FIG. 3A, the offset is 0, and the count value of the horizontal counter (9) is stored in the memory (6) as it is. Read address. For this reason, the read masking signal (16) is not output, and the telop is displayed in a state where the video of the monitor television (23) is not scrolled (reference position). FIG. 3B shows when the offset address is 32, and 32 is preset in the horizontal counter (9) at the beginning of the effective image of H. The title image (19) is read from the memory (6) in accordance with the address obtained by adding the count up. Then, a read masking signal is output when the read address is 64 or more, and the monitor television image is scrolled to the left by half. The start and stop of scrolling are performed by the offset addressing circuit (15)
Can be controlled by the start and stop of the increment of the count value, and the scroll direction can also be controlled by switching the count value up and down.

The video camera has been described above, but the same applies to a camera-integrated VTR. In this case, a more complete editing function can be realized by recording the created character / pattern on a tape or inputting a video signal reproduced from the tape to a character / pattern storage / reproduction device.

<Effects of the Invention> As described above, according to the present invention, when reading is performed from the memory at a timing different from the timing of writing to the memory, the difference between the writing and reading timings is synchronized with the video signal. By changing the character / pattern information at a position different from the writing position by changing the character / pattern information at a constant interval, the character / pattern information can be moved and a smooth scroll can be executed. Therefore, when reading arbitrary characters and figures stored in the memory, superimposing and displaying the characters and graphics on a normal video signal, and using them for video camera shooting and video editing, as in movie and television broadcasting, titles, Information such as comments and illustrations can be smoothly scrolled horizontally.

[Brief description of the drawings]

1 to 3 show one embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration. FIG. 2 is a diagram in which the character / pattern storage / reproduction device of the present invention is applied to a video camera.
FIG. 4 is a diagram showing a state of scrolling characters / patterns according to the present invention. FIG. 4 is a diagram showing a relationship between the start of an effective image and a reading start point. FIG. 5 is a block diagram showing a conventional embodiment. It is. 2: detection circuit, 4: serial-parallel conversion circuit, 5: parallel-serial conversion circuit, 6: memory, 11: controller, 13: character superimposition circuit, 15: offset address designating circuit, 16: read masking signal, 31: switch circuit , 32: decoding circuit, 33: selector. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] And means for digitizing a first input video signal to form character / pattern information; and memory means for storing the character / pattern information based on horizontal and vertical synchronization signals. In a device for reading out character / pattern information from a memory means and adding and superimposing it on a new second input video signal to output a video signal, a predetermined offset is added to a writing address of the character / pattern information to the memory means. An offset for designating a read address and controlling a horizontal and vertical position of a start point of reading the character / pattern information from the memory means with respect to the second input video signal based on a horizontal synchronization signal and a vertical synchronization signal; Address designation circuit and N types corresponding to a plurality of bits (N) that can be read at once from the memory means A controller for instructing the offset address designating circuit of a read start point; a decode circuit for generating timing signals corresponding to the N types of read start points based on a horizontal synchronization signal and a vertical synchronization signal input from the controller; A selector for selecting N types of timing signals generated by the decoding circuit in accordance with an instruction from the controller, and switching a horizontal read start point of the character / pattern information with respect to the second input video signal. A character / pattern storage / reproduction device characterized by the above-mentioned. 2. When the character / pattern information read from said memory means is added to and superimposed on said second input video signal, an area other than the read range of said memory means is limited to said second input video signal only. 2. A switch circuit for forcibly switching and outputting a signal.
The character / pattern description reproducing device described in 1.