JP2594470Y2 - Reference voltage generation circuit - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit using complementary field effect transistors.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional reference voltage generating circuit.

The reference voltage generating circuit shown in FIG. 3 uses a resistance value of a resistor 304 and a P-type MOS transistor (hereinafter referred to as PM).
OS) 301 and 305, and N-type MOS transistors (hereinafter referred to as NMOS) 303 and 307
A circuit that generates an arbitrary voltage at the output node 302, which is the first node, by adjusting the transistor size, that is, the channel length and channel width, and the threshold voltage of the transistor (hereinafter referred to as Vt) .

[0004]

However, when the power supply is turned on or when the reference voltage generating circuit is in an unstable state such as at the start of an intermittent operation, the output node 302 shown in FIG. 3 is connected to the grounded positive power supply VDD. Generates very close values of voltage,
Still further, the second node 306 exhibits a voltage very close to the negative power supply VSS.

For this reason, the PMOSs 301 and 305 and the NMOSs 303 and 307 are almost cut off and have no current path, so that a considerable time is required until a stable state is reached.

Further, in the reference voltage generating circuit shown in FIG. 3, current continues to flow. Therefore, in order to reduce the power consumption of the entire circuit, the resistance value of the resistor 304 is increased, the transistor size of the PMOS or NMOS, the Vt
Is generally performed to limit the current flowing through the entire reference voltage generating circuit. Therefore, the time until a stable state is further increased.

An object of the present invention is to provide a reference voltage generation circuit which can solve the above-mentioned problem and can shorten the time until the reference voltage generation circuit is stabilized.

[0008]

In order to achieve the above object, a reference voltage generating circuit according to the present invention is provided between an output node as a first node and a negative power supply VSS, or between a second node and a positive power supply VSS. A capacitor is provided between VDD and VDD.

[0009]

The capacitor inserted between the output node and the negative power supply VSS or between the second node and the positive power supply VDD is connected to the output node when the power supply is turned on or at the time of an unstable state such as at the start of an intermittent operation. The second node is forced to have the same potential as the negative or positive power supply voltage. For this reason, PMO
S or the NMOS is turned on, a large current flows in the reference voltage generating circuit, and the state can be instantaneously stabilized.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a reference voltage generating circuit according to a first embodiment of the present invention.

As shown in FIG. 1, the source of a PMOS 101 is connected to VDD, which is a positive power supply grounded.
The drain and gate of S101 are connected to the output node 102, which is the first node.

The source of the PMOS 105 is connected to the resistor 104, and the drain of the PMOS 105 is connected to the second node 1.
06, and the gate of the PMOS 105 is connected to the output node 1
02 respectively.

The resistor 104 is connected between the source of the PMOS 105 and the positive power supply VDD.

The source of the NMOS 103 is connected to the negative power supply VSS, and the drain of the NMOS 103 is connected to the output node 102.
And the gate of the NMOS 103 is connected to the second node 10
Connect to 6.

The source of the NMOS 107 is connected to the negative power supply VSS, and the gate and drain of the NMOS 107 are connected to the second node 106.

Further, the capacitor 108 is connected to the output node 1
02 and the negative power supply VSS.

The reference voltage generating circuit of the present invention shown in FIG.
By connecting a capacitor 108 between the output node 102 and the negative power supply VSS, the output node 102 is set to the same potential as the negative power supply VSS in an unstable state,
101 and the PMOS 105 are turned on.

As a result, a current path is generated between output node 102 and second node 106, and output node 10
2 and the second node 106 are instantaneously stabilized together with the power supply.

Similar effects can be obtained even when the capacitor 108 is connected between the second node 106 and the grounded positive power supply VDD terminal.

Next, the second embodiment of the present invention will be described with reference to the circuit diagram of FIG.
The reference voltage generation circuit according to the embodiment will be described.

As shown in FIG. 2, the source of the NMOS 201 is connected to VSS, which is a grounded negative power supply,
The drain and gate of S201 are connected to the output node 202, which is the first node.

The source of the NMOS 205 is connected to the resistor 204, and the drain of the NMOS 205 is connected to the second node 206.
, And the gate of the NMOS 205 is connected to the output node 202.
Connect to each.

The resistor 204 is connected between the source of the NMOS 205 and the negative power supply VSS.

The source of the PMOS 203 is connected to the positive power supply VDD, and the drain of the PMOS 203 is connected to the output node 202.
And the gate of the PMOS 203 is connected to the second node 20.
6 respectively.

The source of the PMOS 207 is connected to the positive power supply VDD, and the gate and the drain of the PMOS 207 are connected to the second node 206.

Further, the capacitor 208 is connected to the output node 2
02 and the positive power supply VDD.

The reference voltage generation circuit shown in FIG. 2 is a circuit in which the ground provided for the positive power supply VDD of the reference voltage generation circuit shown in FIG. 1 is replaced with a negative power supply VSS.

In the reference voltage generation circuit according to the second embodiment of the present invention shown in FIG.
The capacitor 208 is connected between the capacitor and the DD. As a result, the output node 202 is connected to the positive power supply V during the unstable state.
The same potential as DD is set, and the NMOS 201 and the NMOS 205
Are turned on.

Therefore, a current path is generated between the output node 202 and the second node 206, and the output node 20
2 and the second node 206 stabilize instantaneously with the stabilization of the power supply.

Further, the connection position of the capacitor 208 is determined by connecting the second node 206 to the negative power source VS
Needless to say, the same effect can be obtained even with the S terminal.

[0031]

As apparent from the above description, the present invention makes it possible to stabilize the reference voltage generating circuit instantaneously. Therefore, when power is turned on or when intermittent operation starts,
The waiting time in the unstable state can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a reference voltage generating circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a reference voltage generating circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional reference voltage generation circuit.

[Explanation of symbols]

 Reference Signs List 101 P-type MOS transistor 102 Output node 103 N-type MOS transistor 104 Resistance 105 P-type MOS transistor 106 Second node 107 N-type MOS transistor 108 Capacitor

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G05F 3/24 G11C 11/34 H01L 21/822 H01L 27/04

Claims (2)

(57) [Scope of request for utility model registration] A source connected to a grounded positive power supply ,
P-type MOS transistor connecting the gate and gate to the output node
Resistor (104) between the resistor (101) and the grounded positive power supply
Connects the source via and connects the drain to the second node
P-type MOS transistor connecting gate to output node
(105) and connect the source to the negative power supply and output the drain.
N-type connected to the force node and the gate connected to the second node
Connect the source to the MOS transistor (103) and the negative power supply
N-type connecting the drain and gate to the second node
MOS transistor (107), output node and negative power supply
Or between the second node and the positive power supply
A reference voltage generation circuit , comprising: a capacitor (108) . 2. A drain connected to a grounded negative power supply.
N-type MOS transistor connecting the gate and gate to the output node.
Resistor (204) with a resistor (201) and a grounded negative power supply
Connects the source via and connects the drain to the second node
N-type MOS transistor connecting gate to output node
(205) and connect the source to the positive power supply and output the drain.
P-type connected to force node and gate connected to second node
Connect the source to the MOS transistor (203) and the positive power supply
P-type connecting the drain and the gate to the second node
MOS transistor (207), output node and negative power supply
Or between the second node and the positive power supply
A reference voltage generation circuit , comprising: a capacitor (208) .