JP2586712B2 - Asynchronous signal selection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous signal selection circuit for selecting and outputting one asynchronous signal from a plurality of asynchronous signals.

2. Description of the Related Art In recent years, digital circuits often select and handle various different asynchronous signals, and the output waveform is an important issue. Hereinafter, regarding the conventional asynchronous signal selection circuit,
This will be described with reference to the drawings. FIG. 3 is a circuit diagram showing a configuration of a conventional asynchronous signal selection circuit, and FIG. 4 is a timing chart showing its operation. In FIG.
The conventional asynchronous signal selection circuit is composed of a multiplexer 8 that inputs the asynchronous signal 1, the asynchronous signal 2, and the output selection signal 3, and the output is a selected asynchronous signal.

In such a conventional asynchronous signal selection circuit, as shown in the timing chart of FIG. 4, the switching timing of the output selection signal is selected next to the currently selected asynchronous signal. When the asynchronous signal and the asynchronous signal have different polarities from each other, the multiplexer generates a pulse narrower than the original asynchronous signal as shown in the figure, which may cause a malfunction of a device receiving this output. . An object of the present invention is to provide an asynchronous signal selection circuit that does not output a waveform narrower than the original asynchronous signal when switching.

Means for Solving the Problems In order to achieve the above object, the present invention is to input a plurality of asynchronous signals and a first output selection signal, and use the first output selection signal to output one of the asynchronous signals. An output selection signal forming circuit for forming a second output selection signal, and the plurality of asynchronous signals and the second output selection signal being input and output from among the asynchronous signals. And a multiplexer for selecting and outputting one of the output selection signals by the second output selection signal, and the output selection signal forming circuit sets the switching timing of the second output selection signal to the currently selected asynchronous signal and the next output signal. The asynchronous signal selection circuit is formed so that the timing is such that the asynchronous signals to be selected are both at the high level.

According to the present invention, the switching timing of the second output selection signal to be supplied to the multiplexer is such that the currently selected asynchronous signal is at the high level and the next selected asynchronous signal is also at the high level. Therefore, the signal is continuously switched from the high level of the currently selected asynchronous signal to the high level of the next selected asynchronous signal, and a waveform narrower than the width of the asynchronous signal is not output.

Embodiment Hereinafter, an asynchronous signal selection circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of an asynchronous signal selection circuit according to one embodiment of the present invention when two asynchronous signals are selected, and FIG. 2 is a timing chart showing the operation thereof. In this embodiment, there are two input asynchronous signals and one output selection signal, and the high level and the low level are switched corresponding to the asynchronous signal 1 and the asynchronous signal 2, respectively. In this case, the timing detection circuit is realized by a rise detection circuit and a fall detection circuit of the output selection signal. In FIG. 1, 1 and 2 are asynchronous input signals, 3 is an output selection signal for selecting which of the input signal 1 and the input signal 2 is output, 4 is a rising detection circuit, 5 is a falling detection circuit, 6 and 7 are latches, 8
Is a multiplexer, 9 is an RS latch for outputting a selection signal of the multiplexer 8, 10 is a signal after switching, 11
Is an inverter. Here, when the output selection signal 3 is at a logic level high, the input signal 1 is selected, and when the logic level is low, the input signal 2 is selected.

In the asynchronous signal selection circuit in which the above components are connected as shown in FIG. 1, when the asynchronous signals 1 and 2 are inputted as shown in FIG. When the signal changes to low, the falling edge detection circuit 5 outputs a logic low level in synchronization with the rising of the asynchronous input signal 2. Since the asynchronous input signal 1 is used as the enable signal E of the latch 7, the output signal of the latch 7 is input to the RS latch 9 while the asynchronous input signal 1 is at the logic high level, The output of 9 becomes a logic level high, and the output of the multiplexer 8 becomes the input signal 2.

When the selection signal 3 changes from low to high, the rising edge detection circuit 4 outputs
A logic low level is output in synchronization with the rising edge of the asynchronous input signal 1. When the output of the latch 6 changes to a logic low level, the output of the RS latch 9 goes to a low level, and the output of the multiplexer 8 outputs the input signal 1 Becomes

When the outputs of the latches 6 and 7 both change to logic level low, the asynchronous input signals 1 and 2
Are both at logic level high, and when switched, the output of the multiplexer 8 remains at logic level high and does not change, so that no narrow signal is output.

As described above, according to the asynchronous signal selection circuit of one embodiment of the present invention, the rising edge detection circuit and the falling edge detection circuit of the output selection signal, the latch circuit are provided, and the timing of the output selection signal supplied to the multiplexer is changed before switching. By setting the timing at which both the asynchronous signal and the switched asynchronous signal are at the logic level high, it is possible to obtain an asynchronous signal selection circuit that does not output a pulse waveform narrower than the original asynchronous signal in signal switching.

It should be noted that the same effect can be obtained by the same concept in an asynchronous signal selection circuit in which there are two or more asynchronous signals.

As is clear from the above embodiments, the present invention receives a plurality of asynchronous signals and a first output selection signal, and selects one of the asynchronous signals with the first output selection signal. An output selection signal forming circuit for forming a second output selection signal; and receiving the plurality of asynchronous signals and the second output selection signal and outputting one of the asynchronous signals. A multiplexer for selecting and outputting one of the two signals with the second output selection signal, and the output selection signal forming circuit selects the switching timing of the second output selection signal and the next selected asynchronous signal and the next selected signal. Asynchronous signal selection circuit formed so that both asynchronous signals are at a high level timing, the pulse width narrower than the original asynchronous signal at the time of signal switching It is possible to realize an asynchronous signal selection circuit in which a waveform is not erroneously output.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing the configuration of an asynchronous signal selection circuit according to one embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the asynchronous signal selection circuit according to one embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing the configuration of the asynchronous signal selection circuit, and FIG. 4 is a timing chart showing the operation of the conventional asynchronous signal selection circuit. 1 ... Asynchronous signal input, 2 ... Asynchronous signal input, 3 ...
Output selection signal input (first output selection signal), 4... Rising detection circuit (timing detection circuit), 5... Falling detection circuit (timing detection circuit), 6... Latch circuit, 7. 8 …… Multiplexer, 10 ……
Output signal, 12 ... Output selection signal forming circuit, 13 ... Second output selection signal.

Claims (1)

(57) [Claims] An output for adjusting a signal received from the outside so that the timing for switching from one asynchronous signal to the next asynchronous signal is when both of these signals are at a high level. An asynchronous signal selection circuit comprising: a selection signal formation circuit; and a multiplexer that receives an output selection signal from the output selection signal formation circuit and selects and outputs one of a plurality of asynchronous signals.