JP2586157B2 - System control unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system control device, and more particularly, to a system control device for performing a request control to a high-speed arithmetic main storage device of a super computer such as an information processing system.

[Conventional technology]

Conventionally, this type of system controller has a priority control for competing individual requests when a block data transfer request from the high-speed processing unit to the high-speed processing main storage device and a contention from the input / output control device to the high-speed processing main storage device. And when both requests are continuous, the system control device processes both requests alternately.

[Problems to be solved by the invention]

Today's system control for the above-described conventional system controller is performed by transferring a large amount of block data from the high-speed processing unit to the high-speed processing main storage unit and performing input / output operations in accordance with higher-speed and large-volume data processing of the high-speed processing unit. In order to increase the speed of the control device and increase the frequency of requests from the input / output control device to the high-speed operation main storage device by the user program, block data transfer requests from the high-speed operation processing device to the high-speed operation main storage device, There is a problem that contention with the data transfer request from the control device to the high-speed operation main storage device frequently occurs, and the request processing time from the input / output control device of the system control device cannot catch up with the processing time of the input / output control device. .

[Means for solving the problem]

The system control device of the present invention controls data transfer request processing between a high-speed operation device and a high-speed operation main storage device of a high-speed information processing system, and controls request processing of data transfer from an input / output control device to a high-speed operation main storage device. An input / output request unit having an input / output request reception buffer capable of receiving and holding m requests from the input / output control device, and a block data transfer from the high-speed arithmetic processing unit to the high-speed arithmetic main storage device. In priority control at the time of contention between a request and m requests held in an input / output request reception buffer from the input / output control device to the high-speed processing main storage device, the m requests held in the input / output request reception buffer Request for block data transfer from the high-speed processing unit to the high-speed processing main memory It has a changeable output request counter for determining the n-number of requests to override the bets.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG.
One embodiment of the present invention is a system control device including an input / output request unit having m input / output request reception buffers.

The input / output control device 1 is connected to the input / output request unit 10 of the system control device 4, the input / output request control 40 and the input / output request data 30. High-speed processing unit 2
Is a high-speed operation request unit 12 of the system control device 4,
High-speed operation request control 42 and high-speed operation request data
32 and connected. The high-speed operation main memory 3 is connected to the high-speed operation main memory request control 45 and the high-speed operation main memory request data 34 of the high-speed operation main memory request unit 13 of the system controller 4.

The input / output request unit 10 has m input / output request receiving buffers 20, is connected to the request control unit 11 by the input / output request control 41,
And the input / output request data 31.

The request control unit 11 is connected to the initial state control device 5 by the initial value control 46, and is set to a maximum count number n that can be changed.
The I / O request counter 21 is connected to the high-speed operation request unit 12 by a high-speed operation request control 43, and is connected to the high-speed operation main memory request unit 13 by a high-speed operation main memory request control 44. The high-speed operation request unit 12 and the high-speed operation main memory request unit 13 are connected by high-speed operation request data 33.

Next, the operation will be described. A request to the high-speed operation main storage device 3 sent from the high-speed operation processing device 2 is as follows.
The data is transferred to the high-speed operation request unit 12 through the high-speed operation request control 42, and further transferred to the request control 11 through the high-speed operation request control 43. Request control 11
When receiving a request from the high-speed processing unit 2 to the high-speed processing main memory 3, it checks that there is no conflict with the request from the input / output control unit 1 to the high-speed processing main storage 3, and checks the high-speed processing main memory request control. The data is transferred to the high-speed main memory request unit 13 through 44.

When there is a request conflict, the request control 11 notifies the high-speed operation request unit 12 of the holding of the request through the high-speed operation request control 43, and the input / output control device 1
The request from the high-speed processing unit 2 to the high-speed processing main storage unit 3 is repeated until the request processing to the high-speed processing main storage unit 3 is completed by the number of requests in the input / output request reception buffer up to the input / output request counter 21. It is received from the high-speed operation request unit 12 and transferred to the high-speed operation main memory request unit 13.

The request from the high-speed operation processing device 2 to the high-speed operation main storage device 3 transferred to the high-speed operation main memory request unit 13 is transferred to the high-speed operation main storage device 3 by the high-speed operation main memory request control 45, and the high-speed operation The block data transfer process of the processing device 2 with the high-speed operation main storage device 3 is started.

The path of the control signal used in the block data transfer includes the high-speed operation main storage device 3, the high-speed operation main memory request control 45, the high-speed operation main memory request unit 13, the high-speed operation main memory request control 44, the request control 11, the high-speed operation The request control 43, the high-speed operation request unit 12, the high-speed operation request control 42, and the high-speed operation processing device 2. The data transfer path is a high-speed operation that connects each block except the request control unit 11 on the control signal path and the data transfer path. The main storage request data 34 and the high-speed operation request data 33 and 32.

Continuous high-speed operation processing device 2 and high-speed operation main storage device 3
In the block transfer request processing described above, the request control unit 11 monitors a request from the input / output control device 1 to the high-speed operation main storage device 3, and when a request is generated, finds a break between successive block transfer requests and finds an input / output request. Control is performed so that requests held in the input / output request buffer 20 up to the counter 21 are processed with priority.

The request from the input / output control device 1 to the high-speed operation main storage device 3 is transferred to the input / output request receiving buffer 20 of the input / output request unit 10 through the input / output request control 40, and further transmitted to the request control unit through the input / output request control 41. Transferred to 11.

The request from the input / output control device 1 to the high-speed operation main storage device 3 transferred to the request control unit 11 is checked for a conflict with the request from the high-speed operation processing device 2 to the high-speed operation main storage device 3, and the contention is checked. If there is no request, the high-speed operation main memory request
The request is transferred to the high-speed operation main storage device 3 via the control unit 13.

When there is a request conflict, priority is given to the requests held in the input / output request reception buffer 20 up to the counter number of the input / output request counter 21, and the processing is performed. If the number of requests held in the input / output request reception buffer 20 is less than the number of counters, the request processing is prioritized for the number of requests, and then the request from the high-speed processing unit 2 is processed. The request from the input / output control device 1 transferred to the high-speed operation main storage device 3 is:
The data transfer process is started, and a path to be used is the same as the path to which the request has been transferred except for the input / output request reception buffer 20 and the input / output request counter 21 for the control signal.

The data transfer path uses each block except the request control unit 11 from the path of the control signal, the high-speed operation main memory request data 34, and the input / output request data 31, 30.

The input / output request counter 21 included in the request control unit 11 is a variable type, and an initial value n is set by the initial state control device 5 through the initial value control 46 at the time of device startup.

If the number of requests from the input / output control device 1 competing with the request from the high-speed processing unit 2 is less than the set value of the input / output request counter 21, the priority is given to the number of requests held in the input / output request reception buffer 20. After processing, the post-processing input / output request counter 21 is set to an initial value.

〔The invention's effect〕

As described above, the present invention provides a high-speed arithmetic operation from an input / output control device that performs priority processing when a request from the input / output control device to the high-speed arithmetic main storage device and a request from the high-speed arithmetic processing device to the high-speed arithmetic main storage device conflict. By making the number of requests to the main storage device variable by user software, it is possible to efficiently control requests to the high-speed operation main storage device, and to cope with various types of user software.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system control device according to one embodiment of the present invention. 1 ... I / O control device, 2 ... High-speed processing device, 3 ...
... High-speed operation main storage device, 4 ... System control device, 10 ...
... I / O request part, 11 ... Request control part, 12 ...
... High-speed operation request unit, 13 ... High-speed operation main memory request unit, 20 ... I / O request reception buffer, 21 ...
I / O request counter.

Claims (1)

(57) [Claims] 1. A system for controlling data transfer request processing between a high-speed processing device and a high-speed processing main storage device of a high-speed information processing system and request processing for data transfer from an input / output control device to the high-speed processing main storage device. An input / output request unit having an input / output request reception buffer capable of receiving and holding m requests from the input / output control device; a request for block data transfer from the high-speed processing unit to the high-speed processing main storage; In priority control at the time of contention with the m requests held in the I / O request reception buffer from the I / O controller to the high-speed operation main storage device, the m requests held in the I / O request reception buffer Priority over block data transfer requests from high-speed processing units to high-speed main storage A changeable input / output request counter that determines n requests to be executed, and a block data transfer request from the high-speed processing unit to the high-speed processing main storage device and a request from the input / output control device to the high-speed processing main storage device When there is a conflict with the request, a request control unit that performs request control always giving priority to a maximum of n requests determined by the input / output request counter among the m requests held in the input / output request reception buffer must be provided. Characteristic system control device.