JP2583679B2 - Cell switching equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell exchange apparatus for exchanging various types of multimedia information such as voice, data, images, and the like at a high speed with a cell.

[0002]

2. Description of the Related Art FIG. 25 shows, for example, IEICE Transactions B-1 Vol.
It is a block diagram which shows the conventional cell exchange apparatus shown on page 1075 (issued in November, 1989).

In the figure, ₁₁ to 1 _n are n (n ≧ 2) input lines to which a packet is input, and this packet has a fixed length and each has a header section containing coded destination information. ing. 2 _{1 to} 2 _n are m (m ≧ 2 ₎ in which the packet is output according to the destination specified in the header portion.
2) Outgoing lines. 3 _{1 to} 3 _l are l (l ≧ n) buffer memories for temporarily storing the input packets, and 4 is an input line ₁₁ to 1 _n to which the packets are input.
And a vacant buffer selecting switches connected to vacant buffer memory 3 ₁ to 3 _l.

[0004] 5 ₁ to 5 _l is the buffer memory 3 ₁ to 3
_l each are prepared corresponding to the establishment and stored in the buffer memory 3 ₁ to 3 _l associated packet, a header storage circuit for extracting and storing only the header portion. 6 _{1 to} 6
_l is provided corresponding to each header memory circuits 5 ₁ to 5 _l, corresponding header memory circuits 5 ₁ to 5 _l outgoing selection circuit which significantly output only to be sent to the output line corresponding to the memory contents of It is.

[0005] 7 ₁ to _7-m are provided in correspondence to each of the output line 2 ₁ to 2 _m, each outgoing line selecting circuits 6 ₁ to 6 _l
Receiving the output of the delivery, it buffer memory 3 ₁ -
An encoder that encodes a buffer number of 3 _l .
8 ₁ to 8 _m is provided to the encoder 7 ₁ to _7-m correspondingly coded buffer number is written in each of the encoders 7 ₁ to _7-m, first-in first-out in which it is read out in order of input (Hereinafter referred to as FIFO) type FIFO memory.

[0006] 9 ₁ to 9 _m is prepared for each outgoing line 2 ₁ to 2 _m corresponds, is controlled by the buffer number which is output from the corresponding FIFO memory 8 ₁ to 8 _m, the buffer memory 3
The packets stored in the ₁ to 3 _l is a buffer connection switch for outputting the outgoing lines 2 ₁ to 2 _m designated by the header portion.

[0007] Here, although a packet instead of a cell is used as a unit of information to be transmitted, the multimedia information is divided into blocks and a header section including destination information is added to the divided multimedia information. In that respect, both cells and packets represent the same thing. However, the difference is that a packet is generally treated as a variable length of one block, whereas a cell is treated as a fixed length defined by an international standard.

Next, the operation will be described. Here, FIG.
6 is a time chart showing the timings of the respective parts of the signal, the flow of control in the case when, who simultaneously receive packets outgoing 2 ₁ addressed incoming 1 ₁ and from 1 _n buffer memory 3 ₁ and 3 _l is vacant Is shown. The packet handled here has a fixed length as described above, and its header portion includes a coded outgoing line number as destination information.

[0009] When the packet arrives at the incoming lines _{1 1 ~1 n,}
Free buffer selection switch 4 the buffer memory 3 ₁ to 3
select one that is vacant in _l, it connects the incoming line 1 ₁ to 1 _n which it arrived packet. Here, FIG.
As shown in (b) and (b), the same outgoing line 2
_{Packet 1} of outgoing line number "1" is specified as the destination, when you arrive at the same time incoming lines 1 ₁ and from 1 _n, the empty buffer selection switch 4, for example, the incoming line 1 ₁ to 1 _n youth turn order, and vacant and that the buffer memory 3 ₁ ~3 _l also to connect them to choose the young number order.

Accordingly, in this case, the incoming line 1 ₁ in the buffer memory 3 ₁ by free buffer selection switch 4, the incoming line 1 _n are respectively connected to the buffer memory 3 _l, the incoming line 1
Packet A arriving at ₁ in the buffer memory 3 _1, packet B arriving at incoming lines 1 _n are respectively accumulated in the buffer memory 3 _l.

[0011] By switching the empty buffer selection switch 4, the packet A buffer memory 3 ₁
The header memory circuit 5 ₁ corresponding to the packet B is also supplied to the header memory circuits 5 corresponding to the buffer memory 3 _l. Here, is for storing the outgoing line number is the content by extracting only the header portion of each packet received header memory circuits 5 ₁ to 5 _l. Therefore, the header storage circuit 5
The ₁ and 5 _l, respectively outgoing 2 ₁ of the output line number "1"
Is stored.

[0012] The contents of these header memory circuits 5 ₁ to 5 _l is sent to the corresponding outgoing line selecting circuit 6 ₁ to 6 _l, the outgoing line selecting circuit 6 ₁ to 6 _l is the corresponding header memory circuits 5 ₁
Only the output sent to the output line corresponding to the outgoing line number designated by the contents of .about.5 _l is made significant, that is, "1".
Outputs sent to other output lines are insignificant, that is, "0". Accordingly, as the outgoing line selecting circuit 6 ₁ shows the output to the encoder ₇₁ in FIG. 26 (c) "1"
And then, the outgoing line selecting circuit 6 _l is a "1" as shown in FIG. 26 (d) output to the encoder _71.

[0013] Here, the encoder 7 ₁ to _7-m are any one of the outputs of the outgoing line selecting circuit 6 ₁ in to 6 _l is "1",
Encoding the appropriate outgoing line selecting circuit 6 ₁ to 6 _l buffer number of the buffer memory 3 ₁ to 3 _l associated are stored it in the FIFO memory 8 ₁ to 8 _m associated with itself. As shown in FIG. 26 (c) and (d), FIFO memory if the output of the two outgoing lines selecting circuits 6 ₁ and 6 _l becomes "1" at the same time, the encoder ₇₁ is the buffer number, for example, young turn order 8 Store in ₁ .

[0014] Therefore, in the FIFO memory 8 and _a buffer memory 3 ₁ of the buffer number is stored first, buffer number l of the buffer memory 3 _l are stored subsequently. Buffer connection switch 9 ₁ to 9 _m from the FIFO memory 8 ₁ to 8 _m associated, read according to the order stored a buffer number stored therein, the buffer 3 ₁ in which the buffer number ~l is assigned ~ 3 _l
The connection to the outgoing lines 2 ₁ to 2 _m associated with itself.

[0015] That is, the buffer connection switch 9 ₁ reads the first buffer number from the FIFO memory ₈₁ as shown in FIG. 26 (e), after the completion of the connection process, reads the next packet number l. When the buffer number is read out, first connect the buffer memory 3 ₁ to OUT line 2 _1, and outputs the packet A stored in the buffer memory 3 ₁ As shown in FIG. 26 (f) to the output line 2 _1.

[0016] transmission of packet A to the output line 2 ₁ is completed, the packet number l is read out as described above, is connected a buffer memory 3 _l is the output line 2 ₁ in the same manner, FIG. 2
6 (g) packet B stored in the buffer memory 3 _l as a is outputted to the outgoing line 2 _1. Thus, the outgoing line 2 _1, the packet A and B are successively output as shown in FIG. 26 (h).

[0017] Buffer connection switch 9 ₁ to 9 _m are each time transmits the packet to the outgoing line 2 ₁ to 2 _m, to release the corresponding buffer memory 3 ₁ to 3 _l, by knowing it in the empty buffer selection switch 4 Be prepared for reception of subsequent packets.

[0018]

Since the conventional cell switching apparatus is configured as described above, the buffer memory 3 ₁
When reading the cell (packet) from to 3 _l, of one to avoid conflicts with other cell buffer memory 3 ₁ to 3
_l can not only one cell accumulates, when the number of write of the cells exceeds the number of buffer memories 3 ₁ to 3 _l,
The cell will be discarded, and a large number of buffer memory 3 ₁ to 3 _l in order to reduce the loss rate of the cells
It is necessary to prepare a further and consequently the incoming line and a buffer memory 3 ₁ to 3 _{l 1} 1 to 1 _n and outgoing lines 2 ₁ -
For connection 2 _m, a problem such as scale of the free buffer selection switch 4 and a buffer connection switch 9 ₁ to 9 _m increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to reduce the probability of cell collision and obtain a cell switching device with high throughput.

[0020]

Means for Solving the Problems] cell switching apparatus according to the first aspect of the present invention, from the previous entry line between one time slot
When the input cell is reserved in the header processing circuit,
In both cases, the buffer memory is stored (number of input lines + number of output lines -1).
More than one, and one time slot
Multiple cells are written to one buffer memory at the same time.
Selected buffer memos to avoid duplication
Control the input space switch to control the header processing.
Write pending cells in the circuit and
Written and addressed at the address in the buffer memory
Avoid duplicate destinations in different and same time slots,
Read, cells managed by time slot,
By controlling the outgoing line space switch, the header portion of the cell
The specified outgoing line is now output in a predetermined order.
Things.

In the cell switching apparatus according to the second aspect of the present invention, the buffer memory is connected to the buffer memory via the outgoing line space switch.
Outgoing speed connected to accumulate cells and adjust outgoing speed
Degree adjustment buffer added for outgoing line, buffer control circuit
Buffer that writes cells by controlling the input line space switch
Select the memory and select the memory of the written cell.
Address in the buffer memory for each cell destination, and
Cells from the buffer memory in a predetermined order based on the
Read at a speed r times the linear speed (where 2 ≦ r ≦ number of wires)
Control the outgoing line space switch to place the cells in a predetermined order.
Write to the exit speed adjustment buffer specified in
A function to read and output to the outgoing line according to the outgoing speed
It is what you have.

Further, in the cell switching apparatus according to the third aspect of the present invention, an incoming line for accumulating cells and adjusting an incoming line speed is provided.
A speed adjustment buffer is added for incoming lines, and the buffer control
Control the output line space switch on the
In addition to controlling the connection between the line and the input space switch
To select the buffer memory to be written and
Read from the input speed adjustment buffer in the buffer memory
The speed of the cell is w times the incoming speed (however, 2 ≦ w <the number of incoming lines)
In the buffer memory of the written cell
Addresses by cell destination, and
Executing the control of the drawing line space switch to place the cells in a predetermined order.
Has a function to output to a designated outgoing line.

According to the fourth aspect of the present invention, there is provided a cell switching apparatus including a buffer memory via an outgoing line space switch.
Connected to one or more cells,
A frame bar that sends cells to outgoing lines in the outgoing line sending order.
Buffer for the outgoing line, and the incoming line to the buffer control circuit.
Buffer memory for writing cells by controlling the space switch
And select the buffer memory of the written cell.
The addresses in the memory are managed by cell destination, and
Control the outgoing line space switch based on the
Output to the frame buffer corresponding to the outgoing line specified by
And the transmission time of one cell at the outgoing line is set to 1
When a time slot is used, it consists of multiple time slots
Operating in one frame time unit
The cells to be sent to the outgoing line are
Frame frames independently and avoiding cell collisions
With a function to control the data to be sent to the
is there.

The cell switching apparatus according to the fifth aspect of the present invention is capable of storing a plurality of cells, and is capable of storing outgoing lines in the order of transmission.
Therefore, exit the frame buffer that sends the cell to the outgoing line.
A cell added to the line and the cell input to the switch
Is output to the outgoing line specified by the header, and
In the event of a collision, the cell must wait
In addition, the transmission time of one cell at the outgoing line is set to one time slot.
One slot consisting of multiple time slots
Operates in frame time units and sends out to the outgoing line within one frame
Cells are independent of the predetermined transmission order
The frame buffer while avoiding cell collision.
This function has a function to control the
You.

[0025]

[Action] cell switching apparatus in the invention of claim 1, as an operation unit of one time slot, this Times
Cells are stored in the selected buffer memory to avoid duplication in lots.
When writing, the buffer
Addresses in the memory and destinations, and in the same time slot
Management for each read time slot to avoid duplication of destinations
By outputting the cell that is
Cell destruction due to collisions in write and read operations
A cell switching device that can avoid abandonment or waiting
I do.

The cell switching device according to the second aspect of the present invention provides a cell switching device in which a cell whose destination has been detected is selected as a battery.
Data in the buffer memory of the cell.
Manage dresses by their destination, and based on that address
Access the buffer memory and store the cells stored there
Is read out at a speed r times the output speed (2 ≦ r <number of outputs).
Read cells from the same buffer memory
More opportunities to reduce cell discard due to read collisions
A cell switching device that can be reduced is realized.

Further, the cell switching apparatus according to the third aspect of the present invention, the cell switching apparatus detects a cell whose destination has been detected by an incoming line switch.
Switch, w times the incoming speed
(2 ≦ w <number of incoming lines) at a speed of
Manages the addresses on the remote memory for each destination, and
Access the buffer memory based on the
By reading, w is stored in the same buffer memory.
Cell writing up to twice
Cell switching that can reduce cell loss due to collisions
Implement the device.

The cell switching device according to the fourth aspect of the present invention provides a cell switching device in which a cell whose destination has been detected is selected from a selected cell.
Stored in the buffer memory of the relevant cell.
Manage addresses by their destination and base them on that address.
To access the buffer memory, and
Frame read out and connected by the outgoing space switch
By outputting to the buffer, the entire buffer memory can be output.
Efficient use by sharing with lines, buffer memory required
The number of switches to reduce the number of switches,
From memory, the order of multiple cells can be changed in frame units.
To avoid cell collisions and reduce cell collision rate
Thus, a cell switching device with high throughput is realized.

The cell according to the fifth aspect of the present invention.
The exchange specifies the input cell in its header.
Output according to destination and cell collision occurred
In that case, the switch unit that waits for cells
One frame is stored in the frame buffer provided for each outgoing line.
For multiple cells to be sent to the outgoing line in the system,
Irrespective of the specified sending order and avoid collisions
So that the cells send out the frame buffer outgoing outgoing order
The cell to the outgoing line in accordance with
Cell collision rate
Implement an exchange device.

[0030]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Before that, the cell switching equipment of each embodiment is described with reference to FIG.
A cell switching device as a premise of the replacement will be described. In Figure _1, 1 1 ~1 _n cell formed of a header portion and a data portion including the outgoing line number as destination information is input n (n ≧ 2)
This input line, the _{2 1 ~2 m m (m ≧} 2) output in accordance with the destination on which cell is designated by the header part is present in the output, these and conventional thereof (FIG. 25) Are equivalent.

[0031] 10a ₁ 10 A _n is the incoming lines ₁ 1 to 1 _n
Each provided corresponding to a header processing circuit that detects the outgoing 2 ₁ to 2 _n of the destination from the header of the cell inputted from the incoming line 1 ₁ to 1 _n.

The cells 11 _{1 to} 11 _p store the cells at a specified address, and can specify the address to read the stored cells irrespective of the writing order. in ≧ n) number of buffer memories, in that it can accumulate a plurality of cells in one buffer memory 11 ₁ to 11 _p, is different from the conventional buffer memory 3 ₁ to 3 _l shown in FIG. 25.

12 _{1 to} 12 _p correspond to the buffer memory 11
Provided for each of _{1 to} 11 _p , for example, FIFO
It manages the free address using the type of memory, a storage control circuit in the buffer memory 11 ₁ to 11 _p associated giving a read address and write address.

Reference numeral 13 denotes the header processing circuits 10a ₁ to 10a
The a _n is the incoming line space switch for selectively connecting a predetermined buffer memory 11 ₁ ~11 _p, 14 exits for selectively connecting the buffer memory 11 ₁ to 11 _p to the prescribed outgoing line 2 ₁ to 2 _m It is a line space switch.

Reference numeral 15a denotes a buffer memory 1 in which cells are stored by controlling the switching of the input line space switch 13.
Performs selection of 1 ₁ to 11 _p, an accumulated address of the buffer memory 11 on ₁ to 11 _p of cells was, managed by the destination of each cell, based on the address that is managed on the destination outgoing line and controls the switching of space switch 14, the cell to the outgoing line 2 ₁ to 2 _m designated by the header part is a buffer control circuit for outputting in a predetermined order.

Further, in the above buffer control circuit 15a, the 16 cell arrives to the input lines ₁ 1 to 1 _n, the header processing circuits 10a associated with that incoming ₁ 1 to 1 _n
It receives the outgoing line number of the detected relevant cell by ₁ 10 A _n, the buffer memory 11 ₁ to 11 for storing the cell
header processing circuits 10a ₁ ~ to the it to select the _p
To connect to 10a _n, a write buffer selection circuits for controlling the switching of the entering-line space switch 13.

[0037] 17 output line 2 ₁ by detecting reference cells arriving by the outgoing line number was the destination of the buffer selection circuits 16 ~
2 _m divided separately, the storage control circuit 12 ₁ to 1 in which the cell is a write address of the buffer memory 11 on ₁ to 11 _p written, corresponding to the buffer memory 11 ₁ to 11 _p
Obtained from 2 _p, which is the address exchange circuit to be written to the address queue for later it.

[0038] 18 ₁ ~ 18 _m is its address queue is configured by the FIFO type memories, are provided corresponding to each of the output line 2 ₁ to 2 _m. This address queue 18 ₁ ~ 18 _m, it is the outgoing lines 2 ₁ each to 2 _m associated, the output line 2 ₁ to 2 _m the _first buffer memory 11 which cell is accumulated destined ~ write address on 11 _p is written by the address exchange circuit 17 in arriving order.

Reference numeral 19 denotes the address queues 18 ₁ to 18
_The cells to be read from the buffer memories 11 _{1 to} 11 _p are determined with reference to _m , and their address queues 18 ₁ to 18 _m are determined.
As a read address read out address from and sends the associated to the memory control circuit 12 ₁ to 12 _p in the appropriate buffer memory 11 ₁ to 11 _p, by controlling the switching of the outgoing line space switch 14, the buffer memory 11 is a read buffer selection circuit connected to outgoing lines 2 ₁ to 2 _m to the appropriate ₁ to 11 _p.

Next, the operation will be described. Here, FIG.
In through 4 is a time chart showing the timing of the respective parts of the signal, the incoming line 1 ₁ to 1 _n number n and the output line 2 ₁ to 2 _m of
Are four each, and the buffer memories 11 ₁ to 1
The flow of control when the number p of 1 _p is 10 is shown.

The cells to be treated here are of a fixed length and are randomly inputted, and the cell input phase is adjusted before being inputted to the input lines ₁₁ to 1 _n , so that the cell inputs from all lines are the same. Are supplied in the phase of

FIGS. 2 to 4 (a) to (d) show incoming lines 1 ₁ to 1.
An example of a cell that is input to _4, FIG. (E) - (f) is an example of a storage cell of the buffer memory 11 ₁ to 11 ₁₀ in this case, FIG. (Yo) - (SEO) is the outgoing line shows an example of a cell output from ₂₁ to _24. Here, it is assumed that all circuits are synchronized and one cell can be input and output in one time slot.

[0043] When the incoming ₁ 1 to 1 ₄ in a cell is inputted, the header processing circuits 10a provided corresponding to each incoming line ₁ 1 to 1 _4
1 10 A ₄ detects the outgoing line number from the header portion of the input cell. The write buffer selection circuit 16 of the buffer control circuit 15a, the header processing circuits 10a ₁ to 1
Referring to 0a _4, the incoming line space switch 13, an instruction to connect the buffer memory 11 ₁ to 11 ₁₀ selected for storing arriving incoming lines 1 ₁ to 1 ₄ and the cell of the cell individually.

Here, there are various ways of connecting the input line space switch 13, but the cells are stored in the buffer memories 11 ₁ to 11 ₁ .
11 ₁₀ is stored in, the same buffer memory 11 ₁ to 11 ₁₀ when read after, since it is not desirable to read desired cell is 2 or more, a number of buffer memories 11 ₁ to 11 cells to prevent this _The method of dispersing in ₁₀ is good.

For this purpose, the buffer memories 11 ₁ to 11 ₁
1 ₁₀ not enough as many incoming 1 ₁ to 1 _4, in order to solve the above problem, the Write as many buffer memories 11 ₁ to 11 ₁₀ becomes easy to control. Or alternatively the a simple control example from above, is also conceivable that the cell holding remaining writes cell select the fewest buffer memories 11 ₁ to 11 _10. That is, at the same time x
When the number of cell arrives, select the smallest x-number of buffer memories 11 ₁ to 11 ₁₀ cells remaining, the incoming line 1 ₁
A buffer memory 11 ₁ to 11 ₁₀ selected ~ 1 ₄ is a method for spatially connected.

[0046] In FIGS sequentially select buffer memory 11 ₁ to 11 ₁₀ as simpler control example illustrates a method and writes the arriving cell. That is, the cells are selected in the order of the buffer memories 11 ₁ , 11 ₂ , 11 ₃ ... 11 ₁₀ and the arriving cells are written.

[0047] In time slot 1, the incoming line 1 1st F1 cells ₁ from the signal f (hereinafter, the cell designation in that the first cell of the signal f that F1 cell. For other cells as well.) G1 cells from the incoming line 1 ₂ signal g, 11 cell signal i is input from the incoming line 1 _4. The header portion of each cell, the destination of the outgoing line number, i.e., O ₁ is the output line 2 ₄ in the cell G1 to F1 cell to specify the outgoing line 2 ₁
The O ₄ to specify, in the 11 cells to specify the outgoing 2 ₃ O
₃ is indicated respectively.

[0048] In time slot 2, the incoming line space switch 13, the incoming line 1 ₁ and the buffer memory 11 _1, incoming lines 1 ₂ and the buffer memory 11 _2, incoming lines 1 ₄ and the buffer memory 11
Connect ₃ to each. Therefore, these cells
In slot 2, it is stored in the address specified by the memory control circuit 12 ₁ to 12 ₃ of the buffer memory 11 ₁ to 11 _3.

[0049] At this time, from the storage control circuit 12 ₁ to 12 _p write address of the buffer memories 11 ₁ to 11 ₃ are sent to the address exchange circuit 17. The write address is selected from among the addresses each storage control circuit 12 ₁ to 12 ₃ are respectively managed as an empty address.

The address exchange circuit 17 divides each cell inputted with reference to the write buffer selection circuit 16 by the destination main wire, the write address of the buffer memory 11 ₁ in the address queue 18 _1, the buffer memory 11 ₂ La < br /> Lee bets address into the address queue 18 _4, the address queue 18 ₃ write address of the buffer memory 11 ₃
Write at the end of each.

Next, in time slot 3, the read buffer selecting circuit 19
Takes out the address stored therein from _{1-18 3,} and sends the to the storage control circuit 12 ₁ to 12 ₃ corresponding to the appropriate buffer memory 11 ₁ to 11 _3, the buffer memory 11 ₁ to OUT line space switch 14 ~ 11 ₃ and outgoing line 2
_1, and 2 ₃ and 2 ₄ instructs to connect individually. As a result, the outgoing line space switch 14
Buffer memory 11 ₁ and the output line 2 ₁ at slot 3, the buffer memory 11 ₂ and the output line 2 _4, respectively connected a buffer memory 11 _3-outgoing line 2 _3.

[0052] buffer memory 11 ₁ to 1 associated with each storage control circuit 12 ₁ to 12 ₃ address received
Feed 1 ₃ as a read address, hereinafter, it manages the addresses as an empty address. Each buffer memory 11
Cell read from ₁ to 11 ₃ is outputted to the outgoing line 2 _1, 2 ₄ and 2 ₃ of the destination specified in each header.

In the above example, the destination outgoing lines of the input cells are all different, but the cells input in time slot 2 have the same destination outgoing line. F2 cell, G2 cell entered in the time slot 2, H1 cell is respectively written into the buffer memory 11 _4, 11 ₅ and 11 ₆ In the same manner, the header portion of the three cell,
All are O ₄ is marked to specify the same outgoing line 2 _4.

Here, in the examples of FIGS. 2 to 4, priority is given to incoming lines in ascending order, cells are waited for, and the buffer memories 11 ₄ , 11 ₅ ,
11 in the order of ₆ reads F2, G2, H1 cells, and sends it to the outgoing line 2 _4. Hereinafter, cell exchange is performed in this procedure.

[0055] Here, in the time slot 8, the I2 cell and H6 cell in the buffer memory 11 ₃ is stored, in each destination I2 cell and outgoing 2 ₃ is the outgoing line 2 _2, H6 cells together it is different, but can not be taken out at the same time because they are accumulated in the same buffer memory 11 _3.

[0056] In such a case, prioritize as changes every time the fixed or random number output line ₂₁ to ₂₄ correspond, one cell, for example, takes out only the cells I2, other cell Le H By meeting 6, a collision can be avoided.

Such a phenomenon also occurs in the time slots 9, 10, and 15, but none of the cells is lost due to collision.

Embodiment 1 First it is explained with reference to an embodiment of the invention described in claim 1. Figure 5 is a block diagram showing the configuration of the cell exchanging apparatus according to an embodiment of the invention as set forth in claim 1, the above-mentioned
The same or corresponding parts as those of the cell switching apparatus of FIG.

[0059] In FIG, 10b ₁ ~10b _n are provided corresponding to the incoming line ₁ 1 to 1 _n, the incoming line ₁ 1 to 1 from the header portion of the cell inputted from the _n of the destination output line 2 ₁ to 2 detects _m, also a header processing circuit for holding only the cell during one time slot, the buffer memory 11 ₁ to 1
1 _p (n + m-1) pieces are prepared.

[0060] Also, (write cell) with 15b performs the incoming line selection of the buffer memory 11 ₁ to 11 _p to the cell by controlling the switching are accumulated in the space switch 13 in one time slot, the stored cells the address of the buffer memory 11 ₁ to 11 _p, each address of each cell, and managed by the read time slot, the output line 2 ₁ to 2 _m are specified each cell read time slot in its header Are output in a predetermined order.

In the buffer control circuit 15b, 2
1 is an address table is provided corresponding to each of the outgoing lines 2 ₁ to 2 _m. When the incoming lines 1 ₁ to 1 _n cells arrive, this address table 21 stores the incoming line _11.
Header associated with to 1 _n processing circuit 10b ₁ to 10
receiving the outgoing line number of the cell detected by b _n, the accumulation buffer memory number by selecting the buffer memory 11 ₁ to 11 _p by the outgoing destination for storing the cell and its line bets <br/> address I do.

Reference numeral 20 denotes a buffer memory number for storing cells determined by the address table 21 and a write address, and the buffer memory 11 _{1 to} 11 _p is connected to the header processing circuits 10 b _{1 to} 10 b _n. An input line connection instruction circuit for controlling switching of the line space switch 13.

Reference numeral 22 denotes a cell to be read from the buffer memories 11 _{1 to} 11 _p with reference to the address table 21, and an address read from the address table 21 is used as a read address to read the corresponding buffer memory 1.
And it sends to the memory control circuit 12 associated with the 1 ₁ to 11 _p, by controlling the switching of the outgoing line space switch 14, connecting the buffer memory 11 ₁ to 11 _p to the appropriate outgoing line 2 ₁ to 2 _m Outgoing line connection instruction circuit.

Next, the operation will be described. Here, FIG.
In through 8 is a time chart showing the timing of the respective parts of the signal, the input line in ₁ 1 to 1 _n number n and the output line 2 ₁ to 2 _m number m is four each of the buffer memories 11 ₁ to 11
The number p of _p indicates the flow of control when a seven n + m-1.

[0065] Further, where the cells to be treated has a fixed length, are adjusted cell input phase before being input to the input line 1 ₁ to 1 _4, those cell input from all lines supplied with the same phase and then, convenience this incoming line _{1 1 ~1 4} I ₀ description,
_{I 1, I 2, I 3} , the output line 2 ₁ to 2 ₄ O _0, O _1, O
₂ and O ₃ . Further, each of the buffer memories 11 ₁ to 11 ₁
11 ₇ Number of each buffer # 0, buffer # 1,
..., buffer # 6.

FIGS. 6 to 8A show time slot numbers, FIG. 6B shows an example of cells input to the input lines I _{0 to} I ₃ , FIG.
(D) and (e) the internal state of each incoming line connection instruction circuit 20 and the outgoing line connection instruction circuit 22, the storage state of (f) a cell of the buffer memory 11 ₁ to 11 _7, (g) the outgoing line O
Shows the cells output to ₁ ~ O _3. Here, it is assumed that all circuits can input and output one cell in a time slot in synchronization.

[0067] incoming I ₀ when ~I ₃ in the cell is inputted, the header processing circuit 1 provided corresponding to each incoming line I ₀ ~I ₃
0b ₁ ~10b ₄ detects the outgoing line number from the header portion of the input cell, also during this time slot is reserved for the cell.

[0068] buffer control circuit address table 21 in 15b refers to the header processing circuit 10b ₁ ~10b _4, the cells that are input to the input line I ₀ ~I ₃ in which the buffer memory 11 ₁ to 11 ₇ respectively By deciding whether to write or not, and instructing the result to the incoming line connection instructing circuit 20, the incoming line space switch 13 causes the incoming line I
₀ ~I ₃ and connects the buffer memory 11 ₁ to 11 _7, which is selected to store the cell.

[0069] Incidentally, one buffer memory, so can not be one cell of the write and one cell to be read in the same time slot, the choice of buffer memory 11 ₁ to 11 ₇ writing and reading of a plurality of cells in the same time slot Must not occur.

Inside the address table 21, there is a table in which a row is taken for each destination outgoing line and a column is taken for each read time slot. Each cell has a buffer memory in which cells to be read in that time slot are stored. The number and the address in the buffer memory are stored. For an outgoing line having no cell to be read in an arbitrary time slot, an empty signal is entered in the corresponding cell.

[0071] Here, although the manner of connection of the incoming line space switch 13 to connect the cell to the buffer memory 11 ₁ to 11 ₇ are various when a cell arrives, the cell is stored in the buffer memory 11 ₁ to 11 ₇ It is not desirable that there be two or more cells to be read in the same buffer memory when read later.

Therefore, a method of distributing cells to a large number of buffer memories 11 _{1 to} 11 ₇ to prevent this is preferable.
The buffer memory 11 ₁ to 11 ₇ for is insufficient in the same number as the incoming lines number. Also, when writing cells, since different buffers must be selected, the buffer memory line p needs at least (number of input lines n) + (number of output lines m) -1. In the embodiment, the buffer memory number p is 7.)

In FIGS. 6 to 8, the tables in the address table 21 are divided for each read time slot, but since the capacity is limited, the time slots are reused cyclically. Therefore, the position read in the next time slot is indicated by the read pointer rp, and this is cyclically updated.

In the table, a queue of cells arriving on a first-come-first-served basis is created for each outgoing destination, and a write pointer w indicating the next write position is located at the next position at the end of this queue.
An example in which po to wp ₃ are used for each outgoing line destination is shown.

The buffer memory 11 for writing cells
_One method of determining to 11 _7, when the cell arrives at the input line, the input line I _o include a buffer memory 11 ₁ to 11 ₇ to be a candidate in the order of I ₃ from the same in the same time slot buffer memory 11 ₁ to 11 ₇ make sure that the writing of a plurality of cells, is from the same buffer memory 11 ₁ to 11 ₇ with the same buffer at the same time slot of the plurality of cells read does not occur, an example of determining the candidates. The buffer memory 11 ₁ to 11 ₇ which is a candidate shows an example includes those that are not full of holding cells cyclically.

In FIGS. 6 to 8, time slot 1
Previously, there was no cell arrival. At time slot 1, cells have arrived at incoming lines I ₀ , I ₁ and I ₃ . Here, the name of the cell is represented by using an incoming line number, an outgoing line number, and a time slot at the time of arrival of the cell.
It arrived _3, a cell addressed to the output line O _1.

In time slot 1, read pointer rp
Is at a position of the second column of the table, although not described in the figure, the write pointer wp ₀ ~ the initial time slot 1
It is assumed that wp ₃ is all at the position of the third column of the table. Incoming lines I ₀ cells 011 arriving at is stored in the current table to the buffer # 0 for example because other cells do not exist, managing the address written this to the buffer memory 11 ₁ are accompanied by the memory control circuit 12 In this example, the write address is 0. The upper part of FIG inside-out in the square represents the number of buffer memories 11 ₁ to 11 _7, whereas the lower part indicates the address of the buffer memory 11 to 11 in _7.

On the other hand, since the cell 121 arriving at the incoming line I ₁ aims at the outgoing line O ₂ , for example, a buffer # 1 other than the buffer # 0 used for the cell 121 is considered as a candidate. The buffer # 1 satisfies the condition because when reading out the cell, it is sufficient to look at the third column in the table and only the buffer # 0 is used.

Therefore, cell 121 is stored at address 0 of buffer # 1. Since cells 311 arriving at the incoming lines I ₃ aims OUT line O _1, now cell 011, the buffer # 0 used in the cell 121 is stored in the address 0 of the buffer # 2, for example other than # 1.

When the writing and reading of the next time slot are determined as described above, a connection is instructed to the input line connection instruction circuit 20 and the output line connection instruction circuit 22, and the input line space switch 13 and the output line space switch 14 exchange. 2, the incoming line space switch 13, the incoming line I ₃ and the buffer # 0, incoming line I ₁ and the buffer # 1, incoming line I ₃ and the buffer #
2 are connected, and writing of these cells is performed in time slot 2.

Since the contents indicated by the read pointer rp, that is, all the second columns in the table contain empty signals, the outgoing line connection instructing circuit 22 is instructed to disconnect the outgoing line space switch 14. Become.

In time slot 2, cells arrive at all incoming lines I _{0 to} I ₃ . Similarly to time slot 1, the buffer memory 11 ₁ to 11 ₇ so as not occur in the writing or reading of a plurality of cells identical buffer memories 11 ₁ to 11 ₇ are selected at the same time slot.

In the time slot 2, the read pointer rp is updated by one compared to the time slot 1, and is located in the third column in the table. This instructs the outgoing line connection instruction circuit 22, in time slot 3, the outgoing line space switch 14, the buffer # 0, the output line O _1, buffer # 1
And the outgoing line O ₂ are connected, and in time slot 3, these cells are read.

In the above example, when a cell arrives at the incoming line, the buffer memory 11 ₁ becomes a candidate in the order of incoming lines I ₀ to I _3.
To 11 ₇ raised, make sure that the writing of one of the plurality of cells in the same buffer memory 11 ₁ to 11 ₇ in the time slot, and that the same buffer memory 11 ₁ to 11 ₇ from the plurality of cells read does not occur, This is an example in which candidates are determined, and buffer memories 11 _{1 to} 11 ₇ that are candidates are determined.
Was an example of cyclically giving up something that was not full due to cell suspension.

In the time slot 4, the cell 134 is addressed to the outgoing line O ₃ , and the buffer # 5 is first mentioned as a candidate, but the buffer # 6 is mentioned because it will be used for reading in the same time slot. Decided .
Similarly, for the cell 304, the buffer #
3 is selected. In these two examples, they are indicated by 〇.

Thus, the buffer memory 11 is simply
₁ to 11 ₇ in comparison with the H method of allocating cyclically and can avoid collision cell, it is prevented that the cell is lost by this collision.

Embodiment 2 Next, an embodiment of the invention described in claim 2 will be described with reference to the drawings. Figure 9 is a block diagram showing the configuration of the cell exchanging apparatus according to an embodiment of the invention as set forth in claim 2, the previously described figures
The same or corresponding parts as those of the first cell switching apparatus are denoted by the same reference numerals, and description thereof is omitted.

In the figure, 23 ₁ to 23 _m are each the outgoing line 2 ₁
It provided corresponding to to 2 _m, are connected in a predetermined buffer memory 11 ₁ to 11 _p by the outgoing line space switch 14, the buffer memory 11 ₁ to 11 _p from the outgoing line speed r times (2 ≦ r < The number of cells read out at the speed of (number of outgoing lines) is accumulated, and outgoing lines 2 ₁ associated with the outgoing line speeds are stored.
This is an outgoing speed adjustment buffer that outputs the signal to 2 _m .

Further, reference numeral 15c denotes a write buffer selection circuit 16, an address exchange circuit 17, and an address queue 18 ₁
18 _m , and a read buffer selection circuit 19, and controls the switching of the input line space switch 13,
With selecting a buffer 11 ₁ to 11 _p in which the cell is written, the buffer memory 11 of the written cells ₁ to
An address on the 11 _p managed by the destination of the cell, the cell in a predetermined order from the buffer memory 11 ₁ to 11 _p and based on it, at a rate of r times the outgoing line speed (2 ≦ r <outgoing line number) to read, the output line space switch 14 so that the cell is outputted to the output line 2 ₁ to 2 _m designated by the header portion
And controls the corresponding outgoing line speed adjustment buffers 23 21 _to
Writing to 3 _m, it reads them according to the previous outgoing line speed, a buffer control circuit for outputting the corresponding outgoing lines 2 ₁ to 2 _m.

Next, the operation will be described. Here, FIG.
0 Figure 12 is a time chart showing the timings of the respective parts of the signal, Figure 2 in the cell switching apparatus of FIG. 1
As in the case of FIG. 4, in the incoming line ₁ 1 to 1 _n number n and the output line 2 ₁ to 2 _m number m is four each of the case number p of the buffer memory 11 ₁ to 11 _p is 10 The control flow of (a) to (so) is shown in FIGS.
Are identical to those of

[0091] Further, where the cells to be treated are those that are input at random in a fixed length, are adjusted cell input phase before being input to the input line 1 ₁ to 1 _n, the cell input from the whole line is the same Are supplied in the phase of

The basic cell exchange procedure is as shown in FIG.
Proceed as in the case of the device . Now, in the time slot 8 as shown, and the 12 cell and H6 cell in the buffer memory 11 ₃ is stored. Here, in these two cells each destination, 12 cells although outgoing line 2 _2, H6 cells have the different from each other and outgoing line 2 _3, they output line 2 ₁
As well as attempts to read in 21 to ₂₄ of the outgoing line speed and the same speed,
To stored in the same buffer memory 11 _3,
They cannot be taken out at the same time.

FIGS. 13 and 14 are time charts showing enlarged time slots 6 to 13 in FIGS. 13 to 14 the buffer memory 11 ₁ to 1 in
Shows the case of performing 1 ₁₀ read at three times the speed of the outgoing velocity outgoing lines 2 ₁ to 2 _4. (E) to (f) in the figure
The accumulation example of a cell of the buffer memory 11 ₁ to 11 _10,
(Tsu) - (La) is the outgoing line speed adjustment buffer 23 _{1-23 4}
Write state of the cell to, (Yo) - (SEO) is the output line 2 ₁
Shows an example of a cell output from 21 to _24, respectively.

[0094] Here, the a cell destined to a different destination than the 12 cell and the H6 cell in the buffer memory 11 ₃ in the time slot 8, be read at three times the speed of the outgoing line speed from the buffer memory 11 _3, both cell corresponding outgoing line 2 _2, it can be output simultaneously to 2 _3. That is, read out at three times the speed of the outgoing line speed from the buffer memory 11 ₁ to 11 _10, up to three in the same buffer memory 11 ₁ to 11 _10, can be tolerated duplicate read cell in the same time slot become.

Although such a situation occurs in other time slots 9, 10, and 15, none of the collisions causes the cells to wait.

Although the case where the reading speed of the buffer memories 11 _{1 to} 11 ₁₀ is set to be three times the output speed has been described, the read speed may be generally 2 or more and r times less than the output number.
Further, it is assumed the use of the dual-port memory as respective buffer memories 11 ₁ to 11 ₁₀ may also be implemented in operable single port memory with more speed.

[0097] Further, if the number of cells to be read from the same buffer memory 11 ₁ to 11 _p in one time slot exceeds the r, the outgoing line 2 ₁ to 2 _m corresponds, by fixed or random number Collision can be avoided if only r cells are extracted with priorities that change each time and other cells are made to wait.

Embodiment 3 FIG . Next, an embodiment of the invention described in claim 3 will be described with reference to the drawings. FIG. 15 is a block diagram showing the configuration of the cell switching device according to one embodiment of the third aspect of the present invention.
The same or corresponding parts as those of the cell switching apparatus of FIG.

In the figure, 24 _{1 to} 24 _n indicate each incoming line 1 ₁
Provided corresponding to to 1 _n, accumulates cells output from the header processing circuit 10a ₁ 10 A _n associated,
A incoming line speed adjusting buffer for sending it to the incoming line speed of w times (2 ≦ w <incoming number) predetermined buffer 11 ₁ to 11 _p, which are connected by the incoming line space switch 13 is read at a speed of.

Further, reference numeral 15d denotes a write buffer selection circuit 16, an address exchange circuit 17, and an address queue 18 ₁
It includes a ~ 18 _m and a read buffer selection circuit 19, reads the accumulated cells into incoming line speed adjusting buffer 24 ₁ to 24 _n at a rate of w times the incoming line speed (2 ≦ w <incoming lines number), the incoming line space switch 13 select buffer memory 11 ₁ to 11 _p in which the cell is to be written to control, the cell causes written w times the speed of the incoming velocity to the buffer memory 11 ₁ to 11 _p, programmed cell of the buffer memory 11 ₁ to 11 addresses in the _p managed by the cell destination, outgoing lines space switch 1 based thereon
4 controls the cell so that the outgoing line 2 specified by its header part
_This is a buffer control circuit for outputting data in a predetermined order to _{1 to} 2 _m .

Next, the operation will be described. Here, FIG.
6 to FIG. 18 is a time chart showing the timings of the respective parts of the signal, Figure 2 which definitive the cell switching apparatus of FIG. 1
As in the case of FIG. 4, in the incoming line ₁ 1 to 1 _n number n and the output line 2 ₁ to 2 _m number m is four each of the case number p of the buffer memory 11 ₁ to 11 _p is 10 The control flow of (a) to (so) is shown in FIGS.
Are identical to those of

The capacity of each of the buffer memories 11 _{1 to} 11 _p is equivalent to two cells, and the cells handled here are of a fixed length and are inputted at random, before being inputted to the input lines ₁₁ to 1 _n. In this case, the cell input phase is adjusted, and cell inputs from all lines are supplied with the same phase.

[0103] incoming ₁ 1 to 1 when _four cells are inputted, each incoming line ₁ 1 to 1 ₄ in a corresponding header processing circuits 10 ₁ to 10 ₄
Detects the outgoing line number from the header section, writes the cell in the corresponding incoming line speed adjusting buffer 24 _{1-24 4.}

On the other hand, the write buffer selection circuit 16 in the buffer control circuit 15d is provided with the header processing circuit 10 ₁
10 ₄ See, the incoming line space switch 13, the incoming line speed adjusting buffer 24 _{1-24 4} written the cell,
Buffer memory 1 selected to store the cell
And instructs the 1 ₁ to 11 ₁₀ to connect individually.

The input speed adjusting buffers 24 ₁ to 24 ₁
24 ₄ reading speed, i.e. the buffer memory 11 ₁ to 1
1 ₁₀ writing speed is incoming ₁ 1 to 1 of ₄ of the incoming line speed 2
Was doubled, within one time slot, it is assumed that the same buffer memory 11 ₁ to 11 ₁₀ write the two cells.

Here, the buffer memories 11 ₁ , 11 ₂ ,
11 ₃ ,..., 11 ₁₀ are selected in order, and the arriving cells are to be written in order. In the buffer memories 11 _{1 to} 11 ₁₀ to be written in a certain time slot,
If any capacity is already full, skip it and write it to the next buffer memory 11 ₁ to 11 _10.

It is preferable that the cell writing is distributed to different buffer memories 11 _{1 to} 11 ₁₀ as much as possible. In this embodiment, the writing speed of the buffer memories 11 _{1 to} 11 ₁₀ is set to twice the input speed. If the status cell discard Ru cause this is unavoidable, a plurality in one buffer memory 11 ₁ to 11 ₁₀ to 1 time slot (2
) Cells are allowed to be written, thereby reducing cell discard.

That is, the time slot 1 shown in FIGS.
The F10 cell, H10 cell, and 18 cell input at 1 are:
Empty buffer memory 11 ₆ in the time slot 11
Of only one cell of the two cells and 11 ₇ Therefore, it can not be written at each serving different from each other.

[0109] Thus, by utilizing the fact that the speed of writing into the buffer memory 11 ₁ to 11 ₁₀ is two times the incoming line speed, by writing two in the buffer memory 11 ₆ F10 cells and H10 cells, cell discard Has been prevented. The state in which writing of these three cells has been completed is shown by solid lines in FIGS.

Hereinafter, the basic cell exchange procedure is as shown in FIG.
The procedure proceeds as in the case of the exchange unit .

[0111] Having described the case where the writing speed to the buffer memory 11 ₁ to 11 ₁₀ and 2 times the incoming line speed, typically 2 or more, good as w times of less than incoming line number. Further, it is assumed the use of the dual-port memory as respective buffer memories 11 ₁ to 11 ₁₀ may also be implemented in operable single port memory with more speed.

Embodiment 4 FIG . Next, an embodiment of the invention described in claim 4 will be described with reference to the drawings. FIG. 19 is a block diagram showing the configuration of the cell switching apparatus according to an embodiment of the present invention as set forth in claim 4 .
The same or corresponding parts as those of the cell switching apparatus of FIG.

In the figure, 25 _{1 to} 25 _m correspond to each outgoing line 2 ₁
Provided corresponding to to 2 _m, is connected in a predetermined buffer memory 11 ₁ to 11 _p by the outgoing line space switch 14,
The buffer memory 11 ₁ to 11 and cells at one or a plurality can store read out from _p, a frame buffer to be transmitted to the outgoing lines 2 ₁ to 2 _m of the cell according to the output line transmission order.

Reference numeral 15e denotes a buffer selection circuit 16, an address exchange circuit 17, and address queues 18 ₁ to 18.
_m and comprising a read buffer selection circuit 19, the incoming line space by controlling the switching of the switch 13, the buffer as well as select memory 11 ₁ to 11 _p, written buffer memory 11 ₁ to 1 cell was the cell is to be written,
Manages the address on 1 _p for each destination of the cell, a frame buffer 25 and controls outgoing line space switch 14 based thereon, corresponding to the cell to the outgoing lines 2 ₁ to 2 _m designated by the header portion Write to _{1 to} 25 _m , outgoing line 2 ₁ to
When transmission time of one cell in 2 _m of the one time slot, and operating at 1 frame time unit composed of a plurality time slots, the cell to be transmitted to the outgoing lines 2 ₁ to 2 _m within one frame, advance This is a buffer control circuit that controls transmission to the frame buffers 25 _{1 to} 25 _m irrespective of the determined transmission order and while avoiding cell collision.

FIG. 20 shows the frame buffer 25.
Is a block diagram showing the configuration of ₁ to 25 _m. As shown, each of the frame buffers 25 _{1 to} 25 _m includes one distribution circuit 31 and q cell buffers 32 _{1 to} 32 _m.
q , and one circulation switch 33. Here, q indicates the number of time slots constituting one frame.

Next, the operation will be described. Here, FIG.
FIGS. 1 to 23 are time charts showing the signal timings of the respective parts, _{where n is} the number of incoming lines 11 to ₁ n and 2 is the outgoing line.
The number m of _{1 to} 2 _m is 4 each, and the buffer memory 1
1 ₁ to 11 the number of _p p indicates the flow of control when it is six.

The cells handled here are randomly input with a fixed length, and the cell input phase is adjusted before being input to the input lines 1 ₁ to 1 _n , so that the cell input from all lines is the same. Are supplied in the phase of

[0118] FIG. (A) to (d) is an example of a cell input to the input line ₁ 1 to 1 _4, Fig. (E) - (j) of the cell in the buffer memory 11 ₁ to 11 ₆ in that case FIGS. 7 (L) to 7 (S) show an example of storage of frame buffer memory 25.
Cell buffer 32 _{1 to} 253 _4, 32 _2, Fig. (Tsu) - (La) shows an example of a cell to be outputted to the outgoing line 2 ₁ to 2 _4. Here, all circuits are synchronized,
One cell can be input and output in one time slot.
It is assumed that one frame is made by a time slot. Also,
Here, reading from the buffer memory is
Allowed from the next time slot after the time slot
Noh.

[0119] When a cell is input to the input line ₁ 1 to 1 _n, the header processing circuit 1 provided corresponding to each incoming line ₁ 1 to 1 _n
0a ₁ 10 A _n detects the outgoing line number from the header portion of the input cell. The write buffer selection circuit 16 of the buffer control circuit 15 includes the header processing circuits 10a ₁ to 10a ₁ to
Referring to 10a _n, the incoming line space switch 13, an instruction to connect the buffer memory 11 ₁ to 11 ₆ selected for storing arriving incoming lines 1 ₁ to 1 ₄ and the cell of the cell individually.

[0120] Here, although the way the are various connection incoming line space switch 13, in FIGS. 21 to 23 in turn selects the buffer memory 11 ₁ to 11 ₆ as a simple control example, write the arriving cell Shows how to go. Here, the name of the cell is indicated as the cell 231 by the destination outgoing line number, the incoming line number, and the input time slot. In time slot 1, the cell arrives at all the incoming lines ₁ 1 to 1 _4, the buffer memory 11 ₁ to 11 ₆ is written is selected.

As described above, since one frame is composed of two time slots, the buffer memories 11 ₁ to 11 ₁
Reading from ₆ is performed in time slots 1 and 2 so that cell collision does not occur. In the example shown in the figure, no collision occurs and the frame buffer memories 25 ₁ to 25 ₁
Cell has been read out to the 25 _4.

[0122] However, in time slot 3, it is necessary to read out of the buffer memory 11 ₂ (f) In the cell 121 and the cell 242 at the same time, but has occurred a collision, and the first time slot in the frame, the By reading them separately in the second time slot, collisions can be avoided.

[0123] In general, if one frame is composed of q time slots, even overlap up the q cell to one buffer memory 11 ₁ to 11 _6, it is possible to prevent collisions. That is, the larger the value of q, it is possible to reduce the probability of collision occurs.

In that case, the frame buffers 25 _{1 to} 25 25
₄ works as follows. That is, q cell buffers 3
Each of 2 _{1 to} 32 _q has a storage capacity of one cell, and stores cells of the first time slot, the second time slot,..., Q time slot in one frame composed of q time slots.

[0125] distribution circuit 31 is 1 in the frame cells to be entered in random order, the cell buffer 32 ₁ to 32 _q corresponding to the output sequence to the output line 2 ₁ to 2 _m, respectively
Distribute to. The circulating switch 33 operates in synchronization with the frame, and from the beginning of the frame, the cell buffers 32 ₁ , 3.
2 ₂ ,..., 32 _q are selected in that order, and the outgoing lines 2 ₁ to 2
Connect to _m .

Embodiment 5 FIG . Incidentally, the reading speed of the buffer memory 11 ₁ to 11 _p, different from the speed of the outgoing 2 ₁ to 2 _m, r times (2 ≦ r ≦ outgoing number) may be in the case of the embodiment. In that case,
If one frame is composed of q time slots, even if there is overlap up to r × q pieces of cells in one buffer memory 11 ₁ to 11 _p are prevented from impinging, <br/> probability of occurrence of collision The rate can be further reduced.

Embodiment 6 FIG . As an example of a system for switching the frame buffers 25 _{1 to} 25 _m at a high speed by directly referring to the header information of a cell by hardware, the output of a conventionally used switch network called a banyan network is disclosed. Even if added to the line, it is effective in reducing the cell collision rate.

Next, one embodiment of the invention described in claim 5 will be described. Figure 24 is a block diagram showing a cell switching apparatus according to an embodiment of the invention described in claim 5. In the figure, ₁ 1 to 1 ₈ incoming lines, the 2 ₁ to 2 ₈ output line, is 25 _to 253 ₈ in the frame buffer, which corresponds to the portions denoted by the same reference numerals in FIG. 19.

[0129] In addition, 26 is a Banyan network, 27 ₁ ~
27 ₈ input buffers provided corresponding to each of the incoming lines ₁ 1 to 1 _8, 28 the input buffer 27 _1-27
8 is an input buffer control unit for controlling ₈ . 29 is a switch portion formed by these banyan network 26, an input buffer 27 ₁ to 27 ₈ and the input buffer control unit 28.

Next, the operation will be described. Here, the frame buffer 25 ₁ to 25 ₈ operates the same in the same manner in Example of the invention described in claim 4 (Figure 19).

[0131] In FIG 24, the cell inputted from the incoming line ₁ 1 to 1 _8, the banyan network 26 destinations outgoing line 2 ₁ to 2 ₈
It aims to. Here, it is assumed that one frame is composed of two time slots.

[0132] Now, cell A in the time slot 1 to the incoming lines 1 ₁
(Outgoing line 2 ₁ addressed), cell C (outgoing line 2 in the time slot 2
₅ addressed) arrives, the incoming line 1 ₅ cell time slots 1 to B (outgoing line 2 ₂ addressed), will be described as an example a case where the cell D in the time slot 2 (output line 2 ₆ addressed) arrives.

If the arrival order, that is, cells A and B are transmitted in time slot 1 and cells C and D are transmitted in time slot 2, the paths of the cells become the same and collide, and either cell is discarded. Or the input buffer 27 ₁ to 2
7 ₈ In wait only one time slot, also would aim to outgoing line 2 ₁ to 2 ₈ in the next time slot.

However, the input buffer control unit 28 manages these two time slots collectively, stores the input cells once in the input buffers 27 ₁ and 27 _5, and stores the cells A and D in the first one time slot. If cells C and B are transmitted in the next time slot, collision can be avoided.

In the first time slot of the frame,
Cells written in the input buffer 27 are frame buffers.
Cell buffer 32 ₁ corresponding to the first slot of the memory 25
To the input buffer 2 in the second time slot.
7 is stored in the second buffer of the frame buffer 25.
Written into the cell buffer 32 ₂ corresponding to the lot first. One
Mari, the frame buffer 25 ₁ corresponding to the outgoing line 2 _1,
Cell buffer 32 ₁ corresponding to cell A in the first slot
Writing to the frame buffer 25 corresponding to the outgoing line 2 _6
6, by writing the cell D to cell buffer 32 ₂ corresponding to the second slot, the cells are orderly delivered to the final output line 2 ₁ to 2 _8.

Embodiment 7 FIG . In the embodiments of the inventions described in the first to fifth aspects, a single cell switching device is shown. However, the cell switching devices may be connected by a link and sequentially connected in multiple stages.

Embodiment 8 FIG . In addition, as the destination information of the header part of the cell, the one in which the outgoing line number is directly provided in correspondence with the outgoing line of the cell switching device is shown. May be performed.

Embodiment 9 FIG . 2 to 4, 6 to 8, 10 to 12, 1
6 to FIG. 18 and FIGS. 21 when the 23 cell arrives at the input line, the buffer memory 11 ₁ for simplicity, 11 _2,
11 ₃ ,... (In FIGS. 6 to 8, buffers # 0, # 1,.
…)), An example of controlling the writing of cells by selecting candidates in the order of the above was shown. However, the buffer memory is individually retained so that each buffer memory has almost the same performance as one large buffer memory shared by all incoming lines. May be selected as a buffer memory having the least number of candidates as a candidate, and a cell may be written, and the cell discard rate may be further reduced with respect to fluctuations in cell arrival.

Embodiment 10 FIG . Also, in the embodiments of the present invention described in claims 1 to 5 , the case where one cell is output to only one output line has been described. It is possible to set the output stage cell selection circuit in advance so that the broadcast function can be added.

Embodiment 11 FIG . Further, the header section and the data section may be separated from each other in structure and transmitted using circuits of different speeds, and the header section and the data section may be respectively assigned to a plurality of signal lines arranged in parallel.

Embodiment 12 FIG . Further, the embodiments of the invention described in claims 1 to 4 above also
Although the link speed of the incoming lines and the same, the speed reading from the buffer memory, are possible traffic focused if faster than the link speed of the incoming lines, to the link speed of the incoming lines to reverse faster than the speed of the outgoing line Is also possible. Further, when the cell switching devices are linked, by setting the speed between the stages higher than the speed of the incoming line, the cell discard rate between the cell switching devices can be further reduced.

Embodiment 13 FIG . Also, both embodiments of the invention described in claim 1-4, it is provided with the single address queue in correspondence to the output line of the cell switching apparatus, priority apart plurality of addresses waiting to each outgoing line It is also possible to assign a matrix and read out a cell with a higher priority first from the buffer memory based on a code indicating a priority added to a header portion of the cell other than the destination outgoing line.

Embodiment 14 FIG . Further, when a restriction on the operation speed is required, a serial / parallel conversion circuit and a parallel / serial conversion circuit may be provided at the front and rear stages of the cell switching device, and processed as parallel signals.

[0144]

As described above, according to the first aspect of the present invention, one time slot is defined as an operation unit,
To the selected buffer memory to avoid duplication
Write the reserved cells in the header processing circuit and
The destination in the buffer memory and the same address.
To avoid duplication of destinations in one time slot,
The cells managed for each time slot are described in the header section of the cell.
Output to the outgoing line indicated by
Or discard due to cell collision in read operation
Is effective in obtaining a cell switching device that can avoid waiting.
is there.

According to the second aspect of the present invention, the destination
Storing the previously detected cell in the selected buffer memory
And the address of the cell in the buffer memory
It manages each destination separately and stores buffer memos based on that address.
And the cell stored there is calculated as the departure speed r
It is configured to read at double speed (2 ≦ r <number of output lines)
Therefore, when reading cells from the buffer memory,
Whether the cells are the same buffer memory by the spatial switch
While allowing overlapping of up to r cells,
Avoid the collision and be led to the outgoing line, even if it is the fastest
Up to r times the departure speed, so increase the speed too much
Cell exchange without the need for
There are many opportunities to read cells from buffer memory,
Further reduce cell loss due to read collisions
There is an effect that a cell switching device that can be obtained is obtained.

Furthermore, according to the third aspect of the present invention,
The cell where the destination is detected is selected by the incoming space switch.
W times the input speed (2 ≦ w <input
Write at the speed of
Manage addresses by their destination, and based on that address
Read the cell by accessing the buffer memory
The buffer memory is almost
In the cup, a double in one time slot in one of the buffer memory
You have to write a few cells
Also writes up to w cells to one buffer memory
Is allowed, and cells are read from the buffer memory.
When multiple cells are connected to other cells by a spatial switch
You are led to the outgoing line while avoiding a collision,
It is up to w times the incoming speed,
It is possible to exchange cells without raising
Can further reduce cell loss due to collisions
There is an effect that a possible cell switching device is obtained.

According to the fourth aspect of the present invention,
Transfer destination detected cell to selected buffer memory
And stores the address of the cell in the buffer memory
Manage by destination and buffer memory based on that address.
Access the memory and read out the cells stored there
Output to the frame buffer connected by the output space switch
To read cells from the buffer memory.
By changing the order of the cells in the frame,
Cell exchange that can avoid cell collisions and reduce the cell collision rate
There is an effect that the device can be obtained.

According to the fifth aspect of the present invention, each
One frame is stored in the frame buffer provided for the outgoing line.
For multiple cells sent to the outgoing line in the
Avoid collisions, regardless of the predetermined sending order.
Cells are sent out in the order that the frame buffer
I configured it to send that cell to the outgoing line according to the introduction
By changing the order of cells in the frame, cell collision
A cell switching device that can avoid and reduce the cell collision rate is obtained.
Has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a cell switching device serving as a premise of a cell switching device according to each embodiment .

FIG. 2 is a time chart showing timings of signals in respective units of the apparatus shown in FIG.

FIG. 3 is a time chart showing timings of signals in respective units of the one shown in FIG. 1;

FIG. 4 is a time chart showing signal timings at various parts of the apparatus shown in FIG.

5 is a block diagram showing a cell switching apparatus according to an embodiment of the invention described in claim 1.

FIG. 6 is a time chart showing the timing of signals in each unit of FIG.

FIG. 7 is a time chart showing signal timings in respective units of the one shown in FIG. 5;

FIG. 8 is a time chart showing signal timings in various parts of the apparatus shown in FIG.

9 is a block diagram showing a cell switching apparatus according to an embodiment of the invention described in claim 2.

FIG. 10 is a time chart showing the timing of signals in each section of the one shown in FIG. 9;

FIG. 11 is a time chart showing the timing of signals in each section of the one shown in FIG. 9;

FIG. 12 is a time chart showing signal timings in respective units of the one shown in FIG. 9;

FIG. 13 is a part of a time chart showing a main part thereof further enlarged.

FIG. 14 is a part of a time chart showing an enlarged main part thereof.

15 is a block diagram showing a cell switching apparatus according to an embodiment of the invention described in claim 3.

FIG. 16 is a time chart showing signal timings at various parts of the apparatus shown in FIG.

FIG. 17 is a time chart showing the timing of signals in each section of the one shown in FIG. 15;

FIG. 18 is a time chart showing signal timings at various parts of the apparatus shown in FIG.

19 is a block diagram showing a cell switching apparatus according to an embodiment of the invention described in claim 4.

FIG. 20 is a block diagram showing a configuration of a frame buffer used therefor.

FIG. 21 is a time chart showing timings of signals of respective units in one embodiment of the invention described in claim 4 ;

FIG. 22 is a time chart showing timings of signals of respective parts in one embodiment of the invention described in claim 4 ;

FIG. 23 is a time chart showing timings of signals of respective parts in one embodiment of the invention described in claim 4 ;

FIG. 24 is a block diagram showing a cell switching apparatus according to an embodiment of the invention described in claim 5.

FIG. 25 is a block diagram showing a conventional cell switching device.

FIG. 26 is a time chart showing signal timings in the respective units.

[Explanation of symbols]

1 ₁ to 1 _n incoming lines 2 ₁ to 2 _m output line 10a ₁ 10 A _n header processing circuit 10b ₁ ~10b _n header processing circuit 11 ₁ to 11 _p buffer memory 13 incoming line space switch 14 outgoing space switch 15a~15e buffer control Circuit 23 ₁ to 23 _m Outgoing line speed adjusting buffer 24 _{1 to} 24 _n Incoming line speed adjusting buffer 25 _{1 to} 25 _m Frame buffer 29 Switch section

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Setuko Miura 5-1-1, Ofuna Kamakura City Mitsubishi Electric Corporation Communication Systems Laboratory (56) References IEICE Spring National Convention 1990 B-469 Electronics IEICE technical report SS E90-35

Claims (4)

(57) [Claims] 1. A plurality of incoming lines to which cells composed of a data part and a header part including destination information thereof are inputted, and a plurality of outgoing lines to which said cells are outputted according to the destination designated by the header part. A header processing circuit that is provided corresponding to each of the incoming lines, holds the cell input from the incoming line for one time slot, and detects an outgoing line to a destination from a header portion of the cell; By designating the address, the cells are written, and by designating the address, the cells can be read irrespective of the write order (number of input lines + number of output lines−1) or more buffers. A memory, an input space switch for selectively connecting the header processing circuit to the predetermined buffer memory,
An output line space switch for selectively connecting the buffer memory to the predetermined output line, and a buffer memory selected by avoiding duplication by using one time slot as an operation unit, controlling the input line space switch to perform the header processing. The cell reserved in the circuit is written, and the cell already written and managed by the address in the buffer memory for each destination and for each read time slot is controlled by the outgoing line space switch, and A cell switching device comprising: a buffer control circuit for outputting the outgoing line specified by the header section in a predetermined order. 2. A plurality of incoming lines to which cells composed of a data part and a header part including destination information thereof are inputted, and a plurality of outgoing lines to which said cells are outputted in accordance with a destination designated by the header part. A header processing circuit that is provided corresponding to each of the incoming lines and detects a destination outgoing line from a header portion of the cell input from the incoming line, and the cell is written by designating an address, Also, by designating an address, a plurality of buffer memories capable of reading the cells irrespective of the write order, and an input space switch for selectively connecting the header processing circuit to the predetermined buffer memory. An output speed adjusting buffer provided for each of the output lines, for accumulating the cells and adjusting the output speed, and a buffer memory for storing the predetermined output speed adjusting buffer. A buffer memory to which the cell is written by controlling the outgoing line space switch and the incoming line space switch which are selectively connected to the memory, and sets the address of the written cell in the buffer memory to the cell. And the cells are read out from the buffer memory in a predetermined order at a speed obtained by multiplying the outgoing speed by 2 or more smaller than the number of outgoing lines. Controlling the outgoing line space switch so as to be output to the outgoing line specified by the header section, and writing the cell to the outgoing line speed adjustment buffer;
A buffer control circuit for reading out and outputting the cells from the output speed adjustment buffer in accordance with the output speed. 3. A plurality of incoming lines to which cells composed of a data part and a header part including destination information thereof are input, and a plurality of outgoing lines to which the cells are output according to the destination specified by the header part. , Provided for each of the incoming lines, a header processing circuit for detecting an outgoing line of the destination from the header portion of the cell input from the incoming line, provided for each of the incoming lines, An input line speed adjustment buffer for accumulating the cells to adjust the input line speed, and the cells are written by specifying an address, and the cells are read out regardless of the writing order by specifying the address. A plurality of buffer memories, an input line space switch for selectively connecting the input line speed adjustment buffer to a predetermined buffer memory, and selecting the buffer memory for the predetermined output line Outgoing space switch to connect
The cell is read from the input speed adjustment buffer, the input space switch is controlled to select a buffer memory in which the cell is written, and the cell is stored in the buffer memory, and the input speed is set to the number of the input lines. While writing at a speed multiplied by a smaller number of 2 or more, the address of the written cell in the buffer memory is managed for each destination of the cell, and the output line space switch is controlled based on the address. A cell switching device comprising: a buffer control circuit for outputting the outgoing line specified by a cell header in a predetermined order. 4. A plurality of incoming lines to which a cell comprising a data portion and a header portion including destination information thereof are inputted, and a plurality of outgoing lines to which said cell is outputted in accordance with a destination designated by the header portion. A header processing circuit that is provided corresponding to each of the incoming lines and detects a destination outgoing line from a header portion of the cell input from the incoming line, and the cell is written by designating an address, Also, by designating an address, a plurality of buffer memories capable of reading the cells irrespective of the write order, and an input space switch for selectively connecting the header processing circuit to the predetermined buffer memory. A frame buffer provided corresponding to each of the outgoing lines, capable of storing one or more cells, and transmitting the cells to the outgoing lines according to an outgoing line transmitting order; An output space switch for selectively connecting the buffer memory to the predetermined frame buffer;
The input line space switch is controlled to select a buffer memory in which the cell is written, and the address of the written cell in the buffer memory is managed for each cell destination, and the outgoing line is controlled based on the address. A space switch is controlled to output the cell to the frame buffer corresponding to the outgoing line specified by the header portion thereof. When the transmission time of one cell in the outgoing line is set to one time slot, It operates in units of one frame time constituted by slots, and transmits cells to be sent to the outgoing line in one frame to the frame buffer independently of a predetermined transmission order and while avoiding collision of the cells. And a buffer control circuit for controlling transmission.