JP2578148B2 - Semiconductor device with lead - Google Patents
Semiconductor device with leadInfo
- Publication number
- JP2578148B2 JP2578148B2 JP63014082A JP1408288A JP2578148B2 JP 2578148 B2 JP2578148 B2 JP 2578148B2 JP 63014082 A JP63014082 A JP 63014082A JP 1408288 A JP1408288 A JP 1408288A JP 2578148 B2 JP2578148 B2 JP 2578148B2
- Authority
- JP
- Japan
- Prior art keywords
- package
- lead
- leads
- semiconductor device
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔概要〕 リード付き半導体装置に関し、 取り扱い中におけるリード曲りの発生を防止すること
を目的とし、 パッケージを、その底面と側面との角の部分に、その
底面から側面に亘る開口を有する凹部を複数有する構成
とし、外リードを、該凹部の奥部より上記パッケージの
側面の開口に向かって直線状に突き出しており、上記パ
ッケージの側面及び底面から突き出さずに、上記凹部の
内部に片持ち梁状に存在している構成とし、実装に際し
て、該外リードが曲げられて、その先端が上記凹部のう
ち上記パッケージの底面の開口から突き出して上記パッ
ケージの底面に突き出すよう構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a semiconductor device with a lead, for the purpose of preventing the occurrence of lead bending during handling, a package is mounted on a corner portion between the bottom surface and the side surface and from the bottom surface to the side surface. A configuration having a plurality of recesses having openings extending over the outer leads, the outer leads are linearly protruded from the deep portion of the recess toward the openings on the side surfaces of the package, and do not protrude from the side and bottom surfaces of the package. The outer lead is bent at the time of mounting, and the tip of the outer lead is protruded from the opening of the bottom surface of the package in the concave portion so as to protrude to the bottom surface of the package. Configure.
本発明はリード付き半導体装置に関する。 The present invention relates to a semiconductor device with leads.
プリント基板の表面に実装される従来のリード付きの
半導体装置は、リードがパッケージの周面より外方に突
出した構成である。A conventional leaded semiconductor device mounted on the surface of a printed circuit board has a configuration in which the leads protrude outward from the peripheral surface of the package.
このため、半導体装置を実装するまでの取扱い中にリ
ード曲りが生じ易い。リード曲りが生じた場合には、実
装に際してリード曲りを修正しなければならず、面倒で
あり、修正作業もむずかしいという問題があった。For this reason, lead bending is likely to occur during handling until the semiconductor device is mounted. When the lead bend occurs, the lead bend must be corrected at the time of mounting, which is troublesome and has a problem that the correction work is difficult.
本発明は、取り扱い中におけるリード曲りの発生を防
止することのできるリード付き半導体装置を提供するこ
とを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with leads that can prevent occurrence of lead bending during handling.
本発明は、パッケージを、その底面と側面との角の部
分に、その底面から側面に亘る開口を有する凹部を複数
有する構成とし、 外リードを、該凹部の奥部より上記パッケージの側面
の開口に向かって直線状に突き出しており、上記パッケ
ージの側面及び底面から突き出さずに、上記凹部の内部
に片持ち梁状に存在している構成とし、 実装に際して、該外リードが曲げられて、その先端が
上記凹部のうち上記パッケージの底面の開口から突き出
して上記パッケージの底面に突き出す構成としたもので
ある。The present invention provides a package having a plurality of recesses each having an opening extending from the bottom surface to the side surface at a corner portion between the bottom surface and the side surface thereof, and forming the outer leads on the side surface of the package from the deep portion of the recess. And protrudes straight from the package, and does not protrude from the side and bottom surfaces of the package, but exists in a cantilever shape inside the concave portion.When mounting, the outer leads are bent, The tip protrudes from the opening of the bottom surface of the package in the concave portion and projects to the bottom surface of the package.
凹部と外リードとは、外リードが凹部内に収められた
関係にある。このため、取り扱い中に外リードが何物か
に押される危険が減り、外リードの曲がりを防止でき
る。The recess and the outer lead have a relationship in which the outer lead is housed in the recess. For this reason, the danger of the outer lead being pushed by something during handling is reduced, and bending of the outer lead can be prevented.
第２図は本発明の一実施例になるリード付き半導体装
置１の全体を示し、第３図は第２図中小円Ａで囲んだ部
分を拡大して示す。第１図は第２図中本発明の要部を示
す。これはセラミックパッケージの場合の例である。FIG. 2 shows the whole of the semiconductor device 1 with leads according to one embodiment of the present invention, and FIG. 3 shows an enlarged portion surrounded by a small circle A in FIG. FIG. 1 shows a main part of the present invention in FIG. This is an example in the case of a ceramic package.
第２図のリード付き半導体装置１は所謂フラットパッ
ケージタイプである。2 is a so-called flat package type.
２はセラミックパッケージであり、内部に半導体チッ
プ12が固着してあり、キャップ３により封止されてい
る。13は内部配線である。Reference numeral 2 denotes a ceramic package in which a semiconductor chip 12 is fixed and sealed by a cap 3. 13 is an internal wiring.
セラミックパッケージ２の周面には、底面４から側面
５に亘って開口した凹部６が多数形成してある。凹部６
の底面６の開口７、側面５の開口８は共にコ字状であり
連続している。On the peripheral surface of the ceramic package 2, a large number of concave portions 6 that open from the bottom surface 4 to the side surface 5 are formed. Recess 6
The opening 7 on the bottom surface 6 and the opening 8 on the side surface 5 are both U-shaped and continuous.
10は外リードであり、その基部を各凹部６の奥部にろ
う材14により固定して略水平に設けてあり、上記内部配
線13と電気的に接続されている。Reference numeral 10 denotes an outer lead, the base of which is fixed to the inner part of each recess 6 by a brazing material 14 and provided substantially horizontally, and is electrically connected to the internal wiring 13.
外リード10の長さｌは、上記開口７の深さｍより若干
短く定めてある。The length l of the outer lead 10 is set slightly shorter than the depth m of the opening 7.
これにより、各外リード10は、凹部６より外方に突出
せずに凹部６内に収まっており、その両側を、隣り合う
凹部６の間に残置形成された櫛歯部11によりガードさて
いる。As a result, each outer lead 10 is accommodated in the concave portion 6 without protruding outward from the concave portion 6, and both sides thereof are guarded by the comb teeth 11 remaining formed between the adjacent concave portions 6. .
従って、外リード10に対して矢印Ｘ方向よりの異物の
接近は、櫛歯部11の面11aにより阻止され、矢印Ｙ方向
よりの異物の接近は櫛歯部11の面11bにより阻止され、
外リード10までは到達しない。Therefore, the approach of foreign matter from the outer lead 10 in the direction of arrow X is prevented by the surface 11a of the comb tooth 11 and the approach of foreign matter in the direction of arrow Y is prevented by the surface 11b of the comb tooth 11.
It does not reach the outer lead 10.
また凹部６の幅W1は外リード10の幅Ｗより若干広いだ
けの狭いものであり、このことによっても異物が凹部６
内に入り込みにくい。The width W 1 of the recess 6 are those slightly wider just narrower than the width W of the outer lead 10, foreign matter by this recess 6
Hard to get inside.
このため、半導体装置１の取り扱い中に外リード10が
何物かに当たって押される危険が従来のものに比べて格
段に少なくなり、取り扱い中に外リード10が曲がる不都
合が効果的に防止される。For this reason, the danger of the external lead 10 being hit by something during the handling of the semiconductor device 1 is significantly reduced as compared with the conventional device, and the inconvenience that the outer lead 10 is bent during the handling is effectively prevented.
次に、上記のリード付き半導体装置１のプリント基板
への実装について説明する。Next, mounting of the semiconductor device 1 with leads on a printed circuit board will be described.
実装する直前に、第４図に示すように、治具20を使用
し、これを矢印Ｂ方向に開口７を通して凹部６内に挿入
し、同方向に押す。これにより、外リード10が同図に示
すように斜めに曲げ変形され、先端10aが開口８を通し
て凹部６外に出、パッケージ２の底面４より突出する。Immediately before mounting, as shown in FIG. 4, a jig 20 is used, inserted into the recess 6 through the opening 7 in the direction of arrow B, and pressed in the same direction. As a result, the outer lead 10 is bent obliquely as shown in the figure, and the tip 10a comes out of the recess 6 through the opening 8 and protrudes from the bottom surface 4 of the package 2.
ここで、例えば櫛歯状の治具を使用すれば、パッケー
ジ２の一の辺に並ぶ外リードを一度に曲げることが出
来、上記の曲げ作業は簡単である。Here, for example, if a comb-shaped jig is used, the outer leads arranged on one side of the package 2 can be bent at a time, and the above bending operation is simple.
半導体装置１は、第５図に示すように、外リード10の
先端10aを配線パターン21と半田22により半田付けされ
て、プリント基板23上に実装される。As shown in FIG. 5, the semiconductor device 1 is mounted on a printed circuit board 23 by soldering the tip 10a of the outer lead 10 with a wiring pattern 21 and solder 22.
外リード10は斜めの状態にあり、実装後の熱ストレス
は、外リード10が適宜変形することにより吸収され、熱
ストレスによる半田付け部の接続不良は起こらない。The outer lead 10 is in an oblique state, and the thermal stress after mounting is absorbed by appropriately deforming the outer lead 10, so that poor connection of the soldered portion due to the thermal stress does not occur.
第６図は本発明の別の実施例になるリード付き半導体
装置30を示す。これはモールドパッケージの場合の例で
ある。FIG. 6 shows a semiconductor device 30 with leads according to another embodiment of the present invention. This is an example of a mold package.
31はモールドパッケージであり、リードフレームの内
リード32、ステージ33、及びステージ33上に固着された
半導体チップ12を被包しており、周囲に凹部６が形成し
てある。Reference numeral 31 denotes a mold package, which covers the inner lead 32 of the lead frame, the stage 33, and the semiconductor chip 12 fixed on the stage 33, and has a recess 6 formed therearound.
外リード34は内リード32より延在して、モールドパッ
ケージ31より上記凹部６内に突出して凹部６内に収まっ
ており、ガードされている。The outer leads 34 extend from the inner leads 32, protrude into the recess 6 from the mold package 31, and are accommodated in the recess 6, and are guarded.
第７図は治具20により外リード34が曲げられて凹部６
外に出、先端34aがモールドパッケージ31の底面より突
出した状態を示す。FIG. 7 shows that the outer lead 34 is bent by the jig 20 and the concave portion 6 is formed.
This shows a state in which the tip 34a is outside and protrudes from the bottom surface of the mold package 31.
第８図はプリント基板23上に実装された状態を示す。 FIG. 8 shows a state of being mounted on the printed circuit board 23.
なお、本発明は、外リードがパッケージの周囲の凹部
内に収まっていればよく、凹部の形状外リードの向き等
は、上記実施例に限定されるものではない。In the present invention, the outer leads only need to be accommodated in the recess around the package, and the direction of the leads outside the shape of the recess is not limited to the above embodiment.
以上説明した様に、本発明によれば、外リードがパッ
ケージの凹部内に収まっているため、外リードがパッケ
ージ内に引き込まれた状態と等価となり、リード付き半
導体装置の取扱い中に外リードが何物かに押されて曲が
る不都合を防止することが出来る。また外リードがパッ
ケージの凹部内に片持ち梁状に存在しているため、外リ
ードを意図的に曲げて変形させることにより、パッケー
ジの底面より突出させることができるため、外リードは
熱ストレスを吸収できる形状となり、実装後の熱ストレ
スによる実装不良の発生も防止出来る。As described above, according to the present invention, since the outer leads are accommodated in the concave portions of the package, the outer leads are equivalent to a state in which the outer leads are pulled into the package. The inconvenience of being bent by being pushed by something can be prevented. In addition, since the outer leads are present in a cantilever shape in the concave portion of the package, the outer leads can be projected from the bottom surface of the package by intentionally bending and deforming the outer leads. The shape can be absorbed, and occurrence of mounting failure due to thermal stress after mounting can be prevented.
第１図は本発明のリード付き半導体装置の要部の構造を
示す図、 第２図は本発明のリード付き半導体装置の一実施例を示
す斜視図、 第３図は第２図中小円で囲んだ部分を拡大して示す図、 第４図は実装に際しての外リードの曲げを説明する図、 第５図は本発明のリード付き半導体装置の一実施例の実
装状態を示す図、 第６図は本発明の別の実施例のリード付き半導体装置の
要部の構造を示す図、 第７図は外リードの曲げを説明する図、 第８図は実装状態を示す図である。 図において、 1,30はリード付き半導体装置、 ２はセラミックパッケージ、 ４は底面、 ５は側面、 ６は凹部、 7,8は開口、 10,34は外リード、 13は内部配線、 11は櫛歯部、 20は治具、 31はモールドバッケージ、 32は内リード を示す。FIG. 1 is a diagram showing the structure of a main part of a semiconductor device with leads of the present invention, FIG. 2 is a perspective view showing one embodiment of a semiconductor device with leads of the present invention, and FIG. 3 is a small circle in FIG. FIG. 4 is an enlarged view of an enclosed portion, FIG. 4 is a view for explaining bending of outer leads during mounting, FIG. 5 is a view showing a mounted state of an embodiment of a semiconductor device with leads of the present invention, FIG. FIG. 7 is a view showing a structure of a main part of a semiconductor device with leads according to another embodiment of the present invention. FIG. 7 is a view for explaining bending of outer leads, and FIG. 8 is a view showing a mounted state. In the figure, 1, 30 is a semiconductor device with leads, 2 is a ceramic package, 4 is a bottom surface, 5 is a side surface, 6 is a concave portion, 7, 8 is an opening, 10, 34 is an external lead, 13 is an internal wiring, and 11 is a comb. Tooth part, 20 is a jig, 31 is a mold package, and 32 is an inner lead.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 村田 昭彦 愛知県春日井市高蔵寺町２丁目1844番２ 富士通ヴィエルエスアイ株式会社内 (56)参考文献 実開 昭61−207043（ＪＰ，Ｕ) ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Akihiko Murata 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Inside Fujitsu VSI Co., Ltd.
Claims (1)
分に、その底面から側面に亘る開口を有する凹部を複数
有する構成とし、 外リードを、該凹部の奥部より上記パッケージの側面の
開口に向かって直線状に突き出しており、上記パッケー
ジの側面及び底面から突き出さずに、上記凹部の内部に
片持ち梁状に存在している構成とし、 実装に際して、該外リードが曲げられて、その先端が上
記凹部のうち上記パッケージの底面の開口から突き出し
て上記パッケージの底面に突き出す構成としたことを特
徴とするリード付き半導体装置。1. A package having a plurality of recesses having an opening extending from the bottom surface to the side surface at a corner between the bottom surface and the side surface thereof. It protrudes linearly toward the opening, and does not protrude from the side and bottom surfaces of the package, but exists in a cantilever shape inside the concave portion.When mounting, the outer leads are bent. A semiconductor device with a lead, the tip of which protrudes from the opening of the bottom surface of the package in the concave portion and protrudes to the bottom surface of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63014082A JP2578148B2 (en) | 1988-01-25 | 1988-01-25 | Semiconductor device with lead |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63014082A JP2578148B2 (en) | 1988-01-25 | 1988-01-25 | Semiconductor device with lead |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01189149A JPH01189149A (en) | 1989-07-28 |
| JP2578148B2 true JP2578148B2 (en) | 1997-02-05 |
Family
ID=11851182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63014082A Expired - Lifetime JP2578148B2 (en) | 1988-01-25 | 1988-01-25 | Semiconductor device with lead |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2578148B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04117462U (en) * | 1991-04-03 | 1992-10-21 | 株式会社三井ハイテツク | semiconductor equipment |
| KR940007757Y1 (en) | 1991-11-14 | 1994-10-24 | 금성일렉트론 주식회사 | Semiconductor package |
| JP2778506B2 (en) * | 1995-02-27 | 1998-07-23 | 日本電気株式会社 | Package for electronic device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61207043U (en) * | 1985-06-18 | 1986-12-27 |
-
1988
- 1988-01-25 JP JP63014082A patent/JP2578148B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01189149A (en) | 1989-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2578148B2 (en) | Semiconductor device with lead | |
| US5500786A (en) | Insulating element having height greater than heights of neighboring components | |
| JP2738772B2 (en) | Surface mount type electronic components | |
| JP4641762B2 (en) | Optical semiconductor device | |
| JP2947244B2 (en) | Semiconductor device | |
| JPS62262447A (en) | Semiconductor package and mounting thereof | |
| JP2555989B2 (en) | Resin-sealed semiconductor device and lead frame | |
| JP2632084B2 (en) | Emboss type carrier tape | |
| JP2885167B2 (en) | Semiconductor device | |
| JP2523606Y2 (en) | Chip type capacitors | |
| JP2692656B2 (en) | Surface mount type semiconductor device | |
| JPH0719872B2 (en) | Semiconductor device | |
| JP2570581B2 (en) | Vertical surface mount semiconductor package | |
| JPH02270354A (en) | Resin-sealed semiconductor device | |
| JP2879672B2 (en) | Test socket for semiconductor package | |
| JPH07262337A (en) | Fitting structure for semiconductor package and ic card | |
| JP2924078B2 (en) | IC card | |
| JPS626697Y2 (en) | ||
| JPH01161707A (en) | Chip component | |
| JPH01270256A (en) | Semiconductor device | |
| JPH0442934Y2 (en) | ||
| JP2591505B2 (en) | Printed wiring board | |
| JPH0427098Y2 (en) | ||
| JPH10289974A (en) | Lead frame and resin-sealed semiconductor device using it | |
| JPH0670226U (en) | Chip type electronic parts |