JP2567163B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a CMOS crystal oscillation circuit formed in a CMOS (complementary MOS) semiconductor integrated circuit and a frequency divider circuit on the same semiconductor substrate. Used in the formed integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a crystal oscillator in which a CMOS crystal oscillation circuit and a frequency dividing circuit for frequency-dividing the crystal oscillation output are formed on the same semiconductor substrate has an original oscillation frequency fo or a frequency-divided circuit according to an external signal. One signal of the frequency fo / 2 ⁿ is selected and taken out as an output.

FIG. 2 shows an example of the circuit. Here, CM
The original oscillator circuit 1 is formed by an external circuit 7 having an OS inverter 2 and a feedback resistor 3, and a crystal oscillator 4 and pull-down capacitors 5 and 6. Further, oscillation signal of the circuit (frequency fo) enters the clocked inverter CI1 via a CMOS inverter 8 and divider circuit 9 (in this case through an inverter 8 has a three-stage structure
, And outputs frequency signals fo / 2, fo / 4, fo / 8, respectively. Original oscillation frequency f
In order to perform signal selection of o, the divided frequencies fo / 2, fo / 4, and fo / 8, the control signals A and B are set to the decoder 10
The activated one of the outputs C, D, E, F selects the desired frequency signal by selectively operating one of the clocked inverters CI1 to CI4. This selected signal is output to the 3-state output circuit 1
It is taken out from the output section 12 through 1. Oscillation stop terminal 13 is normally pulled to "H" by pull-up resistor 14.
(High) level, that is, the power supply VDD level,
An "L" (low) level signal, that is, a ground level signal, is applied to the terminal 13
Input to the CMOS inverter 15
N-channel MOS transistor 16 for stopping oscillation through
Is turned on and the node 17 is set to the “L” level to stop the original oscillation of the oscillation circuit 1. Further, the signal at the terminal 13 is passed through the CMOS inverters 15 and 18 and the frequency dividing circuit 9
To the reset terminal R to stop the frequency dividing operation of the frequency dividing circuit 9, and to enter the control terminal Co of the 3-state output circuit 11 to put the 3-state output circuit 11 in a high impedance state.

The circuit of FIG. 2 is a clocked inverter CI.
Even when the original oscillation output is selected in 1, the frequency dividing circuit 9 is operating, so the switching circuit generated from the frequency dividing circuit 9
The grayed noise, there is a problem that the primary drawer force of noise increases. The reason is that the frequency dividing circuit 9 affects the power supply current during the switching operation in the frequency dividing operation, so that noise is likely to occur in the power supply VDD. Particularly in an integrated circuit, the frequency divider circuit 9 and the oscillator circuit 1, and the inverter 8 and the like between them have a common power source VDD, so that the power source noise of the frequency divider circuit 9 affects the power source of the oscillator circuit 1 and the like. , Inverter 8, clocked inverter CI1,
The oscillation signal output through the output circuit 11 also has noise. These problems are due to noise being transmitted through the board.
It happens because it is easy to get. However, the output of the frequency dividing circuit 9 is
Since the frequency divider circuit itself has a waveform shaping function, noise is extremely small.

[0005]

SUMMARY OF THE INVENTION According to the present invention, an oscillation circuit and a frequency dividing circuit are formed on the same semiconductor substrate, and noise generated from the frequency dividing circuit is suppressed to obtain an original oscillation output with less noise. With the goal.

[0006]

According to the present invention, there is provided a semiconductor substrate having an oscillation circuit and a frequency divider circuit provided in an output line of the oscillation circuit built therein, an original oscillation frequency signal of the oscillation circuit, and A signal selection unit that selectively passes the output of the frequency dividing circuit, an output circuit that outputs the signal selected by the signal selection unit, and the oscillation circuit outputs the original oscillation frequency signal from the output circuit. The semiconductor integrated circuit is provided with an operation stopping means for stopping the operation of the frequency dividing circuit. With such a configuration, when the original oscillation signal is selected and output, by stopping the operation of the frequency dividing circuit that is the noise generation source, the noise in the original oscillation signal can be significantly reduced.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram for explaining the same embodiment, but this is an example of a case corresponding to that of FIG. 2, so the same reference numerals are used for overlapping portions. In FIG. 1, C
An original oscillation signal (frequency fo) is generated by the oscillation circuit 1 formed by the MOS inverter 2, the feedback resistor 3, the crystal oscillator 4, and the external circuit 7 of the capacitors 5 and 6. This original oscillation signal is amplified by the inverter 8 at the subsequent stage, and then enters the clocked inverter CI1 and the frequency dividing circuit 9. The 1/2 frequency-divided output of the frequency dividing circuit 9 is the clocked inverter CI2.
The 1/4 frequency division output is to the clocked inverter CI3,
The 1/8 frequency division output is input to the clocked inverter CI4. The clocked inverters CI1 to CI4 are controlled by the output signals C, D, E, and F from the control signals A and B through the decoder 10, and the original oscillation frequency, the 1/2 frequency division frequency, the 1/4 frequency division frequency, 1 Any one of the / 8 frequency division signals is selected, and this signal is put into the output circuit 11 and taken out from the terminal 12 as an output signal.

Here, when the original oscillation frequency signal is selected by the clocked inverter CI1, the output C of the decoder 10 becomes "H" level and the outputs D, E, F are "L".
Level, and therefore clocked inverter CI1
By operating only as an ordinary inverter, the original oscillation frequency signal is output. At this time, the decoder 1
The “H” level of the output C of 0 and the “H” level of the signal passing from the oscillation stop terminal 13 through the inverters 15 and 18 enter the NAND circuit 21, and the output of the circuit 21 becomes the “L” level. Then, this enters the reset terminal R of the frequency dividing circuit 9, so that the operation of the frequency dividing circuit 9 is stopped. That is, when the original oscillation frequency signal is taken out from the terminal 12 as an output signal, the operation of the frequency dividing circuit 9 is stopped, the power supply is stabilized because there is no switching noise in the circuit, and the power source is generated from the frequency dividing circuit 9. The noise is gone. Therefore, the noise of the original oscillation output is almost eliminated, and the malfunction due to the noise is also eliminated.

The present invention is not limited to the above embodiment, but various applications are possible. For example, the CMOS crystal oscillation circuit of the embodiment may be replaced with another oscillation circuit, or the NAND circuit 21 as the frequency division operation stopping means may be replaced with another one.

[0010]

According to the as described the present invention, as described above, originating
A vibration circuit and a frequency dividing circuit formed on the same semiconductor substrate
When the original oscillation output is taken out from the oscillation circuit, since the frequency dividing circuit is stopped, there is no noise generated from the frequency dividing circuit , and the original oscillation output with very little noise can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Crystal oscillation circuit, 2, 8, 15, 18 ... CMOS inverter, 9 ... Frequency divider circuit, 10 ... Decoder, 11 ... Output circuit, 16 ... Oscillation stop transistor, 21 ... Frequency divider circuit control NAND circuit, CI1 ~ CI4 ... Clocked inverter.

Claims (5)

(57) [Claims] 1. A semiconductor substrate in which an oscillation circuit and a frequency dividing circuit provided on an output line of the oscillation circuit are incorporated together, and an original oscillation frequency signal of the oscillation circuit and an output of the frequency dividing circuit are selectively selected. A signal selecting means to be passed, an output circuit for outputting the signal selected by the signal selecting means, and while the oscillation circuit is outputting an original oscillation frequency signal from the output circuit,
A semiconductor integrated circuit comprising: an operation stopping unit that stops the operation of the frequency dividing circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the oscillation circuit and the frequency dividing circuit use the same power source. 3. The semiconductor integrated circuit according to claim 1, wherein a CMOS integrated circuit is formed on the semiconductor substrate. 4. The semiconductor integrated circuit according to claim 1, wherein the oscillation circuit is a CMOS crystal oscillation circuit. 5. The semiconductor integrated circuit according to claim 1, wherein the output circuit is a 3-state output circuit.