JP2557840B2 - Semiconductor device manufacturing method - Google Patents

Description

DETAILED DESCRIPTION [Overview] A polycrystalline silicon layer is provided on a single crystalline silicon layer, and impurities are ion-implanted into the polycrystalline silicon layer, so that the concentration at the interface between both layers is 10 ¹⁸ cm ^-3 or less. After that, the polycrystalline silicon layer is selectively removed without removing the single crystal silicon layer, thereby efficiently manufacturing a semiconductor device in which the internal base and the emitter are self-aligned.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a bipolar transistor in which a base extraction electrode, an internal base and an emitter are formed in a self-aligned manner with a single mask.

[Conventional technology]

A method for manufacturing a bipolar transistor in which a base extraction electrode, an internal base and an emitter are formed in a self-aligned manner with a single mask is known from Japanese Patent Laid-Open No. 55-1183.
The prior art will be described with reference to the description and drawings of this publication.

FIG. 2 is a drawing showing an intermediate stage of manufacturing a bipolar transistor. In FIG. 2, 10 is a P ⁻ type silicon substrate
Epitaxial layer formed on 12, 14 is sub-collector
n ⁺ region, 16 is a sub-collector conduction n ⁺ region, 18 is an oxide isolation region, 20 is a SiO ₂ layer, 24 is a B-doped P ⁺ type polycrystalline silicon layer (which serves as a contact for the bases 36 and 38), 26
Is a SiO ₂ layer, 28 is an Al ₂ O ₃ layer 32 is an emitter opening, 34 and 36 are external base P ⁺ regions, 38 is an internal base P region, and 40 is SiO ₂ thinned by reactive ion etching. Layers.

The following processing is performed until the stage shown in FIG. P ^-
Form a subcollector n ⁺ region 14 on a silicon substrate 12 of the type:
An epitaxial layer 10 is formed on this substrate 12, and an oxide isolation region 18 is formed therein: On the epitaxial layer 10.
An SiO ₂ layer 20 is selectively formed and an opening is provided in a non-selected area:
A B-doped P ⁺ -type polycrystalline silicon layer 24 is formed on the SiO ₂ layer 20 and the epitaxial layer 10 in the non-selected region: a mask for patterning the polycrystalline silicon layer 24 to form an emitter opening ( 26, 28): holes are provided in the polycrystalline silicon layer 20 using the mask (26, 28): P ⁺ -type polycrystalline silicon layers 24 to B in contact with the epitaxial layer 10 are transferred to the epitaxial layer Diffuse to 10 External Base P ⁺ Region 3
4,36 and simultaneously diffuse impurities from the openings to form internal base P regions 38: Si in the regions of the openings.
Form O ₂ layer 40: thin SiO ₂ layer 40 by reactive ion etching to limit the dimensions of the emitter (not shown).

Then, a series of processes are performed to manufacture a bipolar transistor as shown in FIG. In FIG. 3, B is a base, C is a collector, E is an emitter, 42 is an emitter n ⁺ region, 43 is an As-doped n ⁺ polycrystalline silicon layer (used as an emitter contact), 46 is a passivation film, and 48 is a metal. It is an electrode. In the process leading to Figure 3 from Figure 2 SiO ₂ film 40
An emitter opening is provided in the substrate, an n-type impurity is diffused from the opening, and a process such as lithography and vapor deposition is performed by a conventional method.

According to the above-mentioned conventional technique, since the external base regions 34 and 36 have low resistance, the base resistance is low, and the base contact 24
Is self-aligned to the emitter contact 43,
There are advantages such as extremely small emitter spacing.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, after opening the Al ₂ O ₃ layer 28 and the SiO ₂ layer 26,
The polycrystalline silicon layer 24 is removed by a selective etching solution containing HF: HNO ₃ : CH ₃ COOH (1: 3: 8 ratio) to form an opening, and then the inner base region 38 and the outer base regions 34, 36 are formed. P-type impurity diffusion for formation is performed. For B in the diffusion step must be avoided to diffuse the subcollector conductive n ⁺ region, covering the region with the SiO ₂ layer 20, the hole formed after the SiO ₂ layer 20 and aperture, the collector Metal electrode that is an electrode
There are 48. Therefore, it becomes a mask for B diffusion.
A step of opening the SiO ₂ layer 20 is required.

It is an object of the present invention to limit the opening process in the conventional method of forming the base extraction electrode and the internal base and the emitter in a self-aligned manner by using the impurity-doped polycrystalline silicon layer.

[Means for solving problems]

According to the present invention, (a) a step of forming a single crystal silicon layer on a semiconductor substrate, and (b) the surface of the single crystal silicon layer is selectively oxidized to collect a collector contact, a substrate contact, a base region, etc. And (c) the first non-doped polycrystalline silicon is used as a mask for forming all the conductive regions such as the collector contact, the substrate contact, and the base region. And (d) selectively introducing an impurity of one conductivity type into the first polycrystalline silicon layer formed on the surface of the base formation planned region. Forming a collector contact region by introducing an impurity of opposite conductivity type through the first polycrystalline silicon layer formed in the collector contact formation planned region A step of forming a substrate contact region by introducing an impurity of one conductivity type through the first polycrystalline silicon layer formed in the substrate contact formation region, and (e) collector contact region, substrate contact region And a step of forming an insulating layer so as to cover the polycrystalline silicon formed on the surface of the base formation planned region, and (f) the insulating layer and the first polycrystalline silicon layer on the base formation planned region. A step of removing a part of the single crystal silicon layer to expose the single crystal silicon layer to define an internal base formation planned region; and (g) the impurity introduced into the first polycrystalline silicon layer into the base formation planned region. Selectively diffusing into the single crystal silicon layer to form an external base region in the single crystal silicon layer, and (H) introducing an impurity of one conductivity type into the internal base formation planned region to form an internal base region. And that process,
(K) a step of forming a sidewall on the side wall of the insulating layer and the first polycrystalline silicon layer on the internal base region to define a region where an emitter is to be formed, and (C) the base region of the semiconductor substrate. Forming a second polycrystalline silicon layer thereon, and then selectively introducing an impurity of opposite conductivity type into the internal base region through the second polycrystalline silicon layer to form an emitter region; And a method for manufacturing a semiconductor device, the method including:

[Work]

In the present invention, by using a non-doped material as the polycrystalline silicon layer without using a doped material, a mask for preventing the doped impurities having one conductivity type from diffusing into the opposite conductivity type region of the single crystal layer is indispensable. I lost the prerequisite. A method of implanting impurities by ion implantation is adopted in order to provide the non-doped polycrystalline silicon layer with electric conductivity as an electrode that conducts to the active region of the semiconductor. After this impurity is doped, at least a part of the polycrystalline silicon layer (the part corresponding to the internal base formation planned region) is removed to expose the single crystal silicon layer. Then, an internal base, an external base, an emitter, etc. are formed by a known method. The interface concentration between the polycrystalline silicon layer and the single crystal layer of the base extraction electrode portion is 10 ¹⁸ cm ^-3 for the purpose of preventing the diffusion of impurities into the internal base region and being able to use the selective etching solution for the doped polycrystalline silicon. The following is preferable. 10 ¹⁸ cm ^-3
Since the electric conductivity of the following impurities is insufficient for an electrode, the polycrystalline silicon layer is formed into an electrode by forming a concentration gradient such that the impurity concentration on the surface of the polycrystalline silicon layer is higher than that at the interface. It can be used as.

Ion implantation of impurities having a concentration gradient as described above
It is realized by appropriately combining the ion implantation condition and the heat treatment condition. For example, the first-stage ion implantation under low energy conditions is performed so that the peak position of the impurity is located on the interface side, and in the subsequent second-stage ion implantation, the ion implantation is performed with high energy to deepen the high concentration portion. After the formation, the desired concentration gradient can be obtained by annealing under normal conditions.

 Hereinafter, the present invention will be described in more detail with reference to examples.

〔Example〕

The embodiment described below is an example of a bipolar transistor having an external base formed of a self-aligned polycrystalline silicon layer.

In FIG. 1A, the process proceeds to the stage where a nitride film for patterning the non-doped polycrystalline silicon layer is formed. By this stage, a part of the n ⁺ buried diffusion layer 51 of the P-type silicon substrate 50 is formed: the remaining part 50a is left as a P-type conductivity type, and then an n ^- epitaxial layer 52 is formed. A part of it is covered with a nitride film mask, and the rest is thermally oxidized to form a field oxide film (SiO ₂ film) 53: After removing the nitride film mask by etching: u groove cut and then the bottom part Then, P-type impurities are ion-implanted to form a channel stop 58: After forming an oxide film 59 on the surface of the u-groove, burying the polycrystalline silicon 56 in the u-groove: after coating the surface of the: A layer 54 is formed on the entire surface: and a nitride film 57 is formed on the surface thereof. The non-doped polycrystalline silicon layer 54 is usually 0.3-0.5 by the CVD method.
It is formed to a thickness of μm. The nitride film 57 is usually formed by the CVD method to a thickness of 700 to 1000Å. The non-doped polycrystalline silicon layer 54 is deposited on all the epitaxial layers 52 serving as base, collector, and emitter regions in the product, and the non-doped polycrystalline silicon layer 54 not deposited on the epitaxial layer 52 is the same film. It is deposited on the thick and thick oxide film 53.

In FIG. 1 (B), the polycrystalline silicon layer 54 is selectively oxidized, and the process proceeds until the collector contact and the substrate contact are formed. After the step shown in FIG. 1 (A), the nitride film 57 is selectively removed, and then the polycrystalline silicon layer 54 is selectively oxidized (LOCOS) at an appropriate position on the field oxide film 53. Forming 61: Subsequently, P type impurities are ion-implanted to form a substrate contact region 62: Ion implantation is performed to form a collect contact region 63.

Ion implantation into the polycrystalline silicon layer 54a forming the base extraction electrode, which is one of the features of the present invention, is performed by, for example, implanting B ions under the conditions of 80 keV, 1 × 10 ¹⁵ cm ^-2 (dose amount). , 30 keV, 8 × 10 ¹⁴ cm ^-2 (dose amount). Anneal 900 ~ 9
It is carried out under the conditions of 50 ° C, 20 to 30 minutes, preferably 900 ° C, 30 minutes. In this case, the impurity concentration at the interface is about 2 × 10 ¹⁷ cm ⁻³ , and the surface concentration is about 10 ²⁰ .

In FIG. 1 (C), the nitride film 57 is entirely removed, and
The process proceeds until the internal base and emitter openings are formed in the polycrystalline silicon layer 54a using the oxide film formed by CVD. In the steps after FIG. 1 (B), the nitride film 57 is removed by etching, and then the SiO ₂ layer 65 is formed on the entire surface by the CVD method and the opening 66 is formed. A method for forming the opening 66 is disclosed in
Same as the method described in No. 55-1183, and overhang occurs. By using the etching solution of HF: HNO ₃ : CH ₃ COOH (1: 3: 8), only the polycrystalline silicon layer 54a in which B is ion-implanted is removed, and the single crystal silicon thereunder is hardly removed. . If the concentration of the interface between the polycrystalline silicon layer 54a and the n ⁻ epitaxial layer 52 is about 10 ¹⁸ cm ⁻³ , the etching of the interface region of the polycrystalline silicon layer 54a will be delayed.

In FIG. 1 (D), the process proceeds until the internal / external base and emitter openings are formed. After the step shown in FIG. 1 (C), the silicon not covered with the SiO ₂ layer 65, that is, the exposed portions of the n ⁻ epitaxial layer and the polycrystalline silicon layer 54a, is thinly oxidized by thermal oxidation to 1000 Å or less, and insulation is performed. The SiO ₂ layer 65, which is a layer, is replaced with the polycrystalline silicon layer 54a.
Base oxide film 68 extending to the sidewalls of: 900-950
The P-type impurities are selectively diffused from the polycrystalline silicon layer 54a into the n ^- epitaxial layer 52 by annealing at a temperature of ℃.
0.4μm or less, the average concentration to 10 ²⁰ cm extrinsic base 70 ^-3 is formed (base oxide film 68 with the diffusion-annealing step is the internal base and emitter future n ^- epitaxial layer 52
Of the P type impurities by ion implantation.
It is implanted into the n ^- epitaxial layer 52 through the base oxide film 68 and annealed to form a P region 72 to be an internal base with a thickness of 0.3.
Formed to be less than or equal to μm: A sidewall is formed. As a method of forming the sidewall, for example, a CVD method is used to form SiO 2.
_{2 The} film 74 is deposited to a thickness of 2500 Å or less on the surface of the SiO ₂ layer 65 and the surface of the base oxide film 68 to form an opening (66) with a slightly narrowed window width: polycrystalline silicon by the CVD method. After depositing 75 so as to be embedded in the opening (66): The entire surface is reactively etched to remove the polycrystalline silicon 75, the SiO ₂ film 74 and the base oxide film 68, and an emitter opening is formed.

The P region 72 serving as an internal base formed by the above process
Is defined by the patterning mask of the polycrystalline silicon layer (base extraction electrode) 54a, and the base oxide film 68, SiO ₂
Since no mask is used to define the film 74 and the polycrystalline silicon 75 as shown in FIG. 1 (D), process conditions such as CVD, thermal oxidation and etching rate are used. The emitter whose lateral shape is substantially defined by these (68, 74, 75) is also defined by the polycrystalline silicon layer 54a and the patterning mask. D shown in FIG. 1 (D) is the element size, typically 4.5 μm, while d is the aperture size, typically 1.5 μm.

In FIG. 1 (E), an emitter electrode is formed and a bipolar transistor is completed. At the same time as the emitter electrode, the base electrode, collector electrode, substrate contact electrode,
Resistive contact electrodes are also made, but these electrodes are not shown because they are well known. After FIG. 1 (D), polycrystalline silicon 76 is buried in the emitter opening, and n-type impurities are ion-implanted into polycrystalline silicon 76 and annealed to a thickness of 0.2.
An emitter 84 having a thickness of less than μm and an average concentration of 10 ²⁰ to 10 ²¹ cm ⁻³ is formed, and then an oxide film (SiO ₂ film) 77 is formed by a CVD method to expose the above-mentioned polycrystalline silicon 76 and finally. Emitter electrode
Form 80. The internal base 82 is also formed by the process described above. When As is used as the n-type impurity, the ion implantation conditions are an energy of 80 to 100 kev, a dose amount of 10 ¹⁵ to 10 ¹⁶ cm ^-2 , and an annealing condition of 950 to 1000 ° C. for about 10 minutes.

It will be apparent that the method of the present invention can be carried out even when the conductivity type is opposite to the above description.

〔The invention's effect〕

According to the present invention, the step of forming an opening in the base mask of the polycrystalline silicon layer which will be the base extraction electrode can be omitted.

Furthermore, since the non-doped polycrystalline silicon is used as the starting material for the base extraction electrode, the P-type region and the n-type region can be freely selected by ion implantation.

[Brief description of drawings]

1 (A)-(E) are process drawings showing an embodiment of the present invention, and FIGS. 2 and 3 are process drawings showing a conventional technique. 50 …… P-type silicon substrate, 52 …… n ^- epitaxial layer, 53 …… Passivation (SiO ₂ ) film, 54 …… Non-doped polycrystalline silicon layer, 59 …… Isolation oxide film, 62 …… Substrate contact region , 65 …… SiO ₂ film, 66 …… opening, 68 …… base oxide film, 70 …… external base, 74 …… SiO ₂ film, 75 …… polycrystalline silicon, 80 …… electrode, 84 …… emitter .

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-60-81863 (JP, A) JP-A-58-154267 (JP, A) JP-A-53-5578 (JP, A) JP-A-60- 80274 (JP, A) JP 56-27965 (JP, A) JP 56-94770 (JP, A)

Claims (2)

(57) [Claims] 1. A process of forming a single crystal silicon layer on a semiconductor substrate, and (a) selectively oxidizing a surface of the single crystal silicon layer,
A step of defining a planned formation region of all conductive regions such as collector contact, substrate contact, base region, and (c) conducting the first non-doped polycrystalline silicon on all conductive regions such as the collector contact, the substrate contact and the base region. A step of forming the regions to be formed so that the regions to be formed are simultaneously defined by a single mask pattern, and (d) the first portion formed on the surface of the base formation region.
Selectively introducing an impurity of one conductivity type into the polycrystalline silicon layer, and introducing an impurity of the opposite conductivity type through the first polycrystalline silicon layer formed in the region for forming the collector contact. And a step of forming a substrate contact region by introducing an impurity of one conductivity type through the first polycrystalline silicon layer formed in the substrate contact formation region by: E) a step of forming an insulating layer so as to cover the polycrystalline silicon formed on the surfaces of the collector contact region, the substrate contact region and the base formation region, and (f) the insulation layer on the base formation region. And a step of removing a part of the first polycrystalline silicon layer to expose the single crystalline silicon layer to define a region where an internal base is to be formed. A step of selectively diffusing the impurities introduced into the first polycrystalline silicon layer into the region where the base is to be formed to form an external base region within the single crystal silicon layer; A step of introducing an impurity of one conductivity type into the region to form an internal base region, and (iv) forming a sidewall on the side wall of the insulating layer and the first polycrystalline silicon layer on the internal base region, Defining a region where an emitter is to be formed, and (co) forming a second polycrystalline silicon layer on the base region of the semiconductor substrate, and then, in the internal base region through the second polycrystalline silicon layer. And a step of selectively introducing an impurity of opposite conductivity type to form an emitter region, and a method of manufacturing a semiconductor device. 2. In the step of introducing an impurity into the first non-doped polycrystalline silicon layer, a concentration gradient of the impurity is high on the surface and low at the interface in the polycrystalline silicon layer, and the single crystal is formed. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity concentration at the interface with the silicon layer is 10 ¹⁸ cm ^-3 or less.