JP2550684B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a CMOS circuit.

[Conventional technology]

In general, it may be necessary to decode an internal clock signal that transitions from the ground potential to a potential equal to or higher than the power supply potential when activated by an address signal or other signal and transmit it to only a predetermined output of a plurality of output signals. is there. For example, a word drive signal is a typical example in a MOS dynamic RAM. In this case, the switching elements are N _n such as Q _n3 in FIG. ₃ and Q _n6 in FIG.
Type MOS transistors were generally used. For example, in FIG. 3, N-type MOS transistors Q _n3 , Q
_n4 are connected in series, the middle node is an output terminal (output signal is φ
₂ ), the source of the N-type MOS transistor Q _n4 is grounded, and the drain of the N-type MOS transistor Q _n3 is supplied with a drive signal φ ₁ that rises above the power supply potential when activated at the ground potential during standby. . A gate electrode is provided between the gate of the N-type MOS transistor Q _n3 and the output of the inverter circuit 3,
An N-type MOS transistor Q _n5 fixed to the power supply potential is inserted, and the input signals I _{1 to} I _m are input to the inverter circuit 3.
Is provided to the gate of the N-type MOS transistor Q _n4 . Normally, a plurality of circuits shown in FIG. 3 are provided, the drive signal φ ₁ is common, and the input signals I _{1 to} I _m are a combination of an address true complement signal and a circuit operation list signal. It is normal that Next, the operation will be described with reference to the waveform chart shown in FIG. In the initial state, the drive signal φ ₁ has a low potential (ground potential). It is assumed that the input signals I _{1 to} I _m are all low potential in the initial state. In this state, the output of the NAND gate 2 is at high potential, the node N ₂ is at low potential, the MOS transistors Q _n3 and Q _n4 are in non-conducting state and conducting state, respectively, and the output signal φ ₂ is in low potential state. is there. When the input signals I _{1 to} I _m rise at time t ₁ and transition to the power supply potential Vcc, the output of the NAND gate 2 is inverted and becomes low potential, and the MOS transistor Q _n4 becomes non-conductive. Meanwhile although the potential of the node N ₂ rises, the potential of the node N ₂ for MOS transistor Q _n5 is Vcc-V _T (V _T is the threshold voltage of the MOS transistor Q _n5) remain. At this time, the MOS transistor Q _n3 becomes conductive, but since the drive signal φ ₁ has a low potential, the output signal φ ₂ remains at a low potential, and between the channel of the MOS transistor Q _n3 and the node N ₂ (gate electrode). The existing capacity is charged. After that, if the drive signal φ ₁ rises at time t ₂ and transitions to a potential equal to or higher than the power supply potential, the potential at the node N ₂ becomes due to the capacitance between the channel of the MOS transistor Q _n3 and the gate electrode.
It is pushed up above the power supply potential. (So-called self-boot effect) As the drive signal φ ₁ rises, the node N ₂ becomes Vcc-
When rising from V _T , the MOS transistor Q _n5 becomes non-conductive, so that only the potential of the floating capacitance at the node N ₂ is pushed up, and the potential can be raised to a desired potential.
Therefore, the output signal φ ₂ also reaches a potential higher than the power supply potential. That is, in this conventional example, as described above, it is important that the gate capacitance of the MOS transistor Q _n2 is sufficiently charged, and the time from t ₁ to t ₂ is an important design item.

On the other hand, when at least one of the input signals I _{1 to} I _m remains at the low potential, the output of the NAND gate 2 remains at the high potential in the initial state, and the node N ₂ also remains at the low potential. , The MOS transistors Q _n3 and Q _n4 are in non-conducting and conducting states, respectively, and the output signal φ ₂ remains low potential as shown by the broken line in FIG. 4 (a) even if the driving signal φ ₁ rises. become.

A second conventional example is shown in FIG. Although it is basically similar in configuration to FIG. 3, it is the NOR gate 4 to which the input signals I _{1 to} I _m are input, the output of which is directly connected to the drain of the MOS transistor Q _n8. The inverted signal is
The difference is that the gate is connected to the MOS transistor Q _n7 . In the initial state, the drive signal φ ₁ is the same as in the example of FIG.
If all the input signals I _{1 to} I _m are at low potential, NOR
The output of gate 4 is a high-potential (power supply potential Vcc), node N ₃ is MOS transistor Q _n6 in the state of _{Vcc-V T '(V T} ' is the threshold voltage of the MOS Toranjiuta Q _n8) conductive,
On the other hand, the MOS transistor _Qn7 whose gate is _supplied with the signal inverted by the inverter circuit 5 is on standby in a non-conductive state. In this state, the drive signal φ ₁ has a low potential, and thus the output signal φ ₂ also has a low potential. Figure 6 Referring to the waveform diagram of (a), the input at time t ₁ signal I ₁ ~I When all _{without m} varies remains at low potential time t ₂
When the drive signal φ ₁ rises from the ground potential to a potential equal to or higher than the power supply potential, the MO signal is output in the same manner as described in the conventional example of FIG.
The gate capacitance of the S transistor Q _n6 pushes up the potential of the node N ₃ to reach the potential higher than the power source potential, and the output signal φ ₂ also rises to the potential higher than the power source potential. On the other hand, at time t ₁ , even one of the input signals I _{1 to} I _m rises (broken line), the output of the NOR gate 4 is inverted, the node N ₃ becomes low potential, and the MOS transistor Q _n6 becomes non-conductive. , The gate potential of the MOS transistor Q _n7 rises and the MOS transistor Q _n7 becomes conductive, and the output signal φ ₂ remains at a low potential even if the drive signal φ ₁ subsequently rises.

That is, FIG. 3, N-type MOS transistor to the two prior art examples both between the driving signals phi ₁ and the output signal phi ₂ of FIG. 5 Q _n3,
Switching is performed by inserting Q _n6 and applying the decoded signals of the input signals I _{1 to} I _m to the gate, and further MO
By providing the S transistors Q _n5 and Q _{n8, the same operation} is performed in that the self-boot effect is used to transmit the drive signal φ ₁ rising to the power supply potential or more to the output signal φ ₂ .
The difference is that in the initial state, the drive signal φ ₁
And the MOS transistors Q _n3 , Q inserted between the output signal φ ₂ and the output signal φ _2.
n6 is a non-conduction state and a conduction state, respectively. That is, there are multiple sets of such circuits,
When the MOS transistor Q _n3 or Q _n6 is in the conductive state by the input signals I _{1 to} I _m and the drive signal φ ₁ is directly transmitted to the output signal φ ₂ , the “selected state” MOS transistor Q _n3 or Q _n6 is non-conductive. A state in which the output signal φ ₂ remains at a low potential regardless of the drive signal φ ₁ is called a “non-selected state”.

In the example of FIG. 3 is a non-selected state of all in the initial state, thereby turning the subsequent input signal I ₁ ~I MOS transistor Q _n3 which is one selected by the change of _m. In the example of FIG. 5, all are initially in the selected state, and subsequent changes in the input signals I _{1 to} I _m lower the gate potentials of the MOS transistors Q _n6 other than the selected one to make them non-conductive. The point is the most different point.

[Problems to be Solved by the Invention]

In conventional MOS circuit described above, the interval of the input signal I ₁ ~I time time t ₁ and the driving signal phi ₁ which state is determined in _m begins to rise t ₂ has become a very important design element,
If t ₁ and t ₂ are shortened in order to realize the operation speed, the following various problems occur, and the stability of the operation is significantly deteriorated due to fluctuations in the manufacturing process and internal signal skew due to the layout on the chip. However, this results in a decrease in yield.

For convenience hereinafter the input signal I ₁ ~I _m Example for problems time t ₂ to time t ₁ and the driving signal phi ₁ is increased to be determined is reversed but the order is to the original description, for example, as a skew of the above internal signal Will be explained. In the example of FIG. 3, as shown in FIG. 4 (b), the driving signal φ ₁ is kept in the initial state with the node N ₂ having a low potential and the MOS transistor Q _n3 being non-conductive.
Rises, and then the input signals I _{1 to} I _m rise and the gate potential of the selected MOS transistor Q _n3 rises, the boot effect due to the gate capacitance of the MOS transistor Q _n3 cannot be expected. Node N ₂ is Vcc- _VT
(V _T is the threshold voltage of the MOS transistor Q _n5 ) and the output signal φ ₂ is Vcc−2V _T (MOS transistors Q _n3 , Q _n5
And the threshold voltage of V is set to V _T ), resulting in a significant potential shortage. In this case, 1-transistor type dynamic
If this conventional example is used for the word drive circuit of the RAM, the insufficient potential of the word line causes a shortage of the read signal, a write failure, etc., and the operation becomes extremely unstable.

On the other hand, in the example of FIG. 5, as shown in FIG.
If the drive signal φ ₁ rises _first , as described above,
In the initial state, all the MOS transistors Q _n6 are turned on in the selected state, so that all the output signals φ ₂ start rising. In other words, then the input signal rises once to the output signal phi ₂ the supposedly non-selected I ₁ ~I _m
When is decided, the phenomenon of falling occurs. Also in the example of the word drive circuit of the one-transistor type dynamic RAM, so-called "multiple selection" occurs, and words other than the word line to be originally accessed are raised or floated and the information in the memory cell is destroyed, resulting in a defect. Will end up.

[Means for solving the problem]

A semiconductor device of the present invention includes a P-type MOS transistor and a first
N-type MOS transistors are connected in series with each other with their drains as a common node, and are directly connected to the gate electrode of the first N-type MOS transistor and to the P-type MOS transistor
A control signal is supplied to each of the first N-type MOS transistors whose gate electrodes are at the power supply potential, and the first N-type MOS transistors are supplied with the control signals.
The source of the P-type MOS transistor is supplied with a ground potential, and the source of the P-type MOS transistor is supplied with a drive signal,
A capacitive element is formed between the source and gate of the MOS transistor, and the P-type MOS transistor is formed on the main surface of an independent N-type well region which is not shared with other MOS transistors in the same semiconductor chip. The N-type well and the source of the P-type MOS transistor are connected to each other.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. As in the conventional example, I _{1 to} I _m are input signals, φ ₁ is a drive signal, φ ₂ is an output signal, Q _P1 is a P-type MOS transistor, Q _n1 and Q _n2 are N-type MOS transistors, and C is a capacitive element. In some cases, the gate capacitance of the P-type MOS transistor Q _P1 can be substituted. The input signals I _{1 to} I _m are input to the NAND gate 1 and its output is N
To the gate of the P-type MOS transistor Q _n1 and also to the gate of the P-type MOS transistor Q _P1 via the N-type MOS transistor Q _n2 whose gate is supplied with the power supply potential. The source of the N-type MOS transistor Q _n1 is the ground potential, and the drain thereof is the output signal φ ₂ and the P-type MOS transistor Q _P1.
The input signal φ ₁ is applied to the source of the, and the output signal φ ₂ is connected to the drain. P-type MOS transistor Q
_P1 is formed in an independent N-type well that is not shared with other P-type MOS transistors, and this N-type well is connected to the input signal φ ₁ .

A description will be given with reference to FIGS. 2 (a) and 2 (b). Regarding the initial state, as in the conventional example, the input signals I _{1 to} I _m and the drive signal φ ₁ are in the low potential state. At this time, the output of the NAND gate 1 is at a high potential, the N-type MOS transistor Q _n1 is in the conductive state, the node N ₁ is Vcc-V _T (V _T is the N-type MOS transistor Q
The threshold voltage of _n2 ), and the P-type MOS transistor Q _P1 is non-conductive because of the low voltage of the input signal φ ₁ . Therefore, the output signal φ ₂ has a low potential. FIG. 2A shows a case where the input signals I _{1 to} I _m are first determined (time t ₁ ) and then (time t ₂ ) the drive signal φ ₁ rises. When all the input signals I _{1 to} I _m rise and reach the power supply potential, the “selected state” is set, the output of the NAND gate 1 is inverted, the potential becomes low, the N-type MOS transistor Q _n1 becomes non-conductive, and the node N The potential of ₁ also drops to the ground potential. After that, when the drive signal φ ₁ rises from the ground potential to a potential equal to or higher than the power source potential at time t ₂ , the P-type MOS transistor Q _P1 becomes conductive, the output signal φ ₂ follows the input signal φ _1, and the Reach the potential. At this time, since the N-type well is connected to the source of the P-type MOS transistor Q _P1 , the drive signal φ ₁
Current flows to the well even if voltage rises above the power supply potential,
The threshold of the P-type MOS transistor does not change.
Further, even if there is a capacitance between the channel and gate of the P-type MOS transistor Q _P1 or a capacitance element, the potential of the node N ₁ is not pushed up because the N-type MOS transistor Q _n2 is in the conductive state.

Next, if at least one of the input signals I _{1 to} I _m remains at a low potential, it is in a “non-selected state” (broken line), and the output of the NAND gate 1 does not invert and remains at a high potential. The node N ₁ is the potential of Vcc-V _T. Then, when the drive signal φ ₁ rises at time t ₂ , the potential of the node N ₁ is pushed up by the coupling capacitance C to a potential higher than the power supply potential, and the P-type MOS transistor Q _P1 is never turned on. Therefore, the output signal φ ₂ remains at the low potential.

FIG. 2 (b) shows that after the drive signal φ ₁ rises, the input signal I ₁
~ I _m is determined. Node N ₁ in the initial state is charged to a potential of Vcc-V _T. First, when the drive signal φ ₁ rises, the node N ₁ is pushed up by the coupling capacitance C, both of which should be selected and which should not be selected, and reach a potential higher than the power supply potential. At this point, all the P-type MOS transistors Q _P1 are non-conductive and the output signal φ ₂ remains at a low potential. After that, at time t ₁ , the input signals I _{1 to} I _m are determined and all become high potential, and when “selected”, the output of the NAND gate 1 is inverted and becomes low potential, and the potential of the node N ₁ is lowered. . Therefore, at this time, P
Type MOS transistor Q _P1 becomes conductive, and output signal φ ₂
Can rise to a potential above the power supply.

Further, if even one of the input signals I _{1 to} I _m remains at a low potential, the output of the NAND gate 1 does not invert and remains at a high potential, and the potential at the node N ₁ is the power supply potential. The above potential is maintained. Therefore, the P-type MOS transistor Q _P1 is non-conductive, and the output signal φ ₂ in the "non-selected state" remains at a low potential and does not rise.

〔The invention's effect〕

As described above, according to the present invention, by using the P-type MOS transistor and the bootstrap capacitance, it is possible to switch the drive signal that rises to the power supply potential or higher by the decode signal of the input signal. "Multiple selection" of output signals due to skew with
Therefore, high-speed and stable operation can be expected because the output potential does not significantly decrease.

[Brief description of drawings]

1 is a circuit diagram of an embodiment of a semiconductor device of the present invention, FIGS. 2 (a) and 2 (b) are operation waveform diagrams of this embodiment, and FIG. 3 is a circuit diagram of a conventional example 1, FIG. (A) and (b) are operation waveform diagrams of Conventional Example 1, FIG. 5 is a circuit diagram of Conventional Example 2, and FIG. 6 (a).
(B) shows the operation waveform diagram of the conventional example 2, respectively. 1,2 ...... NAND gate, 3,5 ...... Inverter, 4 ...... NOR gate, I _{1 to} I _m ...... Input signal, φ ₁ ...... Drive signal, φ ₂ ...
... output _{signal, N 1, N 2, N} 3 ...... node, Q _n ...... N-type MOS transistor, Q _P ...... _P-type MOS transistor.

Claims (1)

(57) [Claims] 1. A first terminal for receiving a first input signal, a second terminal for receiving a second input signal having a voltage amplitude different from that of the first input signal, and the second input signal. An output terminal to which the second input signal should be selectively output according to the first input signal when being supplied, and a source and a gate are connected to the first and second terminals, respectively, and Depending on the voltage amplitude of the second input signal when the second input signal is supplied between the P-type transistor having a drain connected to the output terminal and the source and the gate of the P-type transistor And a capacitor for driving the gate.