JP2542590B2 - Decoding method and decoding device for data on data channel - Google Patents

Abstract

Method of decoding data making it possible on the one hand to correct certain errors, e.g. in synchronization and transmission, and, on the other, to require only one compact and universal processing unit, where a device for implementing the method consists of a radio receiver (21), a microprocessor (22) for its control and a universal decoder (11) consisting on the one hand of a demodulation (13) and clock regeneration (12) component, the imput of which is connected to the multiplex output of the radio receiver (21) and, on the other, of a broadcast data processing microprocessor (14), the output of which is connected to said microprocessor (22) for controlling the radio receiver.

Description

Description: FIELD OF THE INVENTION The present invention relates to a method of decoding data transmitted on a data channel. The data is arranged in groups. Each group contains a fixed number N of blocks.
Each block (J) includes an information word MJ of n1 bits, the information word being a linear error protection code.
code) is used to extend (n1 + n2) bit errors into protected blocks. In this method, a predetermined offset word (off-set word) WJ is added to each error protected block by a bitwise exclusive OR operation EXCLUSIVE ORING, and the offset word is added to the inside of the group. Shows the position of the block in question.

[Conventional technology]

The above-mentioned data coding system is known from the European Broadcasting Union (EBU) publications, and the technical data of the Union Tec
The configuration of the decoder is described in hn.3244-F, appendix2, part2.2.

[Problems to be Solved by the Invention]

It is an object of the present invention to provide a decoding method that meets the coding specifications, so that certain errors, especially synchronization errors and transmission conditions of the decoding station, can be maintained with a simple device in a basic setting. It is to be able to correct a transmission error in a poor environment. To put it a little further: the device for implementing the system of the present invention is simple, and since the linear error protection code is an elementary coding, a complicated decoding process is unnecessary, and especially the coded block If is short, the mathematical formula for it is also simple.

[Means for solving the problem]

To achieve the object of the invention, the decoding method comprises the following steps: (a) in the initialization phase: (i) a sequence of (n1 + n2) data bits from the channel. A step of receiving; (ii) 1 using an incremental operation that increments the count by 1 from the sequence of the (n1 + n2) data bits
The step of generating a first syndrome, in which each incremental operation is
tly) including exactly one data bit received, whereby the first syndrome has a plurality of bits; (iii) a standard syndrome (position-indicating) indicating the respective positions of the first syndrome. s
tandard syndromes), which corresponds to all possible offset words with the standard syndrome that indicates the position; (iv) no comparison is obtained (non-corresponde)
nce): (A) excluding the most recently received data bit from the (n1 + n2) data bits above; and (B) still more recently received 1 Updating the first syndrome by including data bits; (v) the step () until a match with a standard syndrome indicating a position corresponding to one of the predetermined offset words is obtained. iii) and above step (i
v) and so that synchronization is established; (b) In the user phase following the steps in the initialization phase (a): (i) the next (n1) received through the data channel.
+ N2) generating an associated syndrome for each of the blocks of n bits; (ii) comparing the associated syndrome with a standard syndrome indicating at least one suitable position, , Each of the next blocks has a position that is considered to be the next-following position in the sequence of groups; (iii) the first one, if a match is obtained, Outputting strategy controlling signal values and outputting information words of blocks to the user; (iv) if no match is found, associate (associat)
ed) Protected against errors that do not have an offset word (n1 + n
2) a step of performing an error correction operation on a block of a number of bits and outputting a second strategy control signal value representing it; (c) the first strategy in a predetermined time sequence. If the control signal value and the second strategy control signal value have occurred, the step of the initialization phase (a) is restarted so that the initialization phase is restarted when the number of errors becomes too large. Steps to start;

Through some kind of encoding process or algorithm, when the n1 bit information word is protected by n2 so-called redundant bits, it is exactly the same again at the receiving end. , The n2 bits are generated one more time, the two results are compared, and the actual difference at that time is
It is called the received (n1 + n2) -bit syndrome. Generally, the syndrome has the same format as the redundant part of the received information. The word syndrome has a broader meaning, but in this particular case it is used to mean the above.

In certain cases it may not be clear where the block of (n1 + n2) bits begins. Therefore (n1
Even when we mistakenly catch the start of the + n2) bit, it is often possible to have some idea to figure out whether the received information is correct or not. The syndrome can represent the following: If the information received is correct, one can tell where the detection started. At that time, the first strategy control signal value is issued. On the contrary, if the information received is incorrect, then the syndrome is rarely applied. If the same syndrome as before is received, it can lead to false conclusions. The second strategic control signal value is used to indicate that the information received is certainly incorrect. So, if the first strategy control signal value and the second strategy control signal value are received in a certain order, the probability of a correct answer is much higher. For example, three OK signals (1
The second strategic control signal value) means that the chance that an error actually occurs is sufficiently small. Note that error protection can detect errors. Mismatches (= non-zero syndromes) can result from a combination of false synchronization and detectable errors.

As described above, it became clear that the OK signal (that is, the first strategy control signal value) of the specific sequence is necessary in order to be able to trust the correct synchronization. Furthermore, a non-OK signal (that is, the second strategic control signal value)
Occurrence of is also acceptable up to a certain amount. Only when that amount is exceeded will synchronization be disabled, at least temporarily.

The invention will be especially useful as a system for wireless data transmission, especially in the FM band. With such a system,
Well-known as RDS (Radio Data System), it is possible to insert data without the listener being aware of it, especially by tuning radio receivers, mono or stereo audio radio broadcasts. Helps identify the program. A receiver with a display screen will display the name and format of the program with which the receiver is tuned, the decoder, wireless text etc. and other more specific information,
For example, it becomes possible to identify road information for car enthusiasts who have a car radio onboard.

Still further, the present invention is directed to point-to-poin in one direction.
It can be used in the t) channel, in another type of modulation scheme, or in a completely different application environment.

The principle of this decoding is that synchronization can only be initiated if a certain number of blocks are sequentially received without error, but once synchronization has been established, there is some error protection inside each block. Therefore, some amount of error is tolerated. In the encoding specification quoted above,
One group contains four blocks, each block contains one 16-bit information word, error protection is performed using a systematic code and 10-bit redundancy. This redundancy can correct single bit errors and burst errors up to 5 bits long. It is known per se to use a certain amount of redundancy to implement various different error protection strategies. For example, one such strategy is to abandon the possibility of complete error correction for a code and instead increase the likelihood of error detection. Also, for example, a minimum of 4 bitwise Hamming (Hammin
g) If a code with a distance is used, either single error correction / double error detection or triple error detection is possible. Even simple applications may treat some code blocks differently than other code blocks. The advantage of linear error protection codes is that the sum of two code blocks again constitutes one code block. The code may be either bit-level systematic or bit-level non-systematic. In the systematic case, the information word is contained in n1 specific bit positions. In the unsystematic case, the information word must be retrieved from a larger number of bit positions (up to (n1 + n2) bit positions).

The user phase begins after the initialization or synchronization phase has been successfully completed. In some cases, the amount of user-phase error can increase to the point where one must consider loss of synchronization.
If so, the system returns to the synchronization phase. Correctable or detectable errors can occur especially when a vehicle with an on-board radio passes under a bridge, for example.
The protection against this is a variety of predetermined (spaced by (n1 + n2) bits) in the stream of bits.
Comparing the syndromes actually generated at a position with the corresponding standard canonical syndromes can be quite effective. If the comparison shows equality, synchronization is considered correct and transmission is error free. If this comparison does not equal, error protection operations are performed. The result of the operation is the detection of one error, two errors or more errors (which seem to be uncorrectable), the correction of one bit error or more bit errors, or a combination thereof. Become. The type of error is stored in the error register means. The system keeps track of these error types and makes a decision about the expected value of the transmission quality after processing each block. This criterion can be adjusted for some applications. One particular idea is that each block that has an error (correctable or not) has an error score.
Add one point. And when a certain limit is reached, the system considers it to be out of sync. When the correct block is received, the error point is reset to 0. Other ideas will be described later.

The European Broadcasting Union's specification for RDS systems promises that all the information words in the first block of each group will be the same. The present invention takes advantage of this special convention to detect and correct any ± 1 bit slip that may occur within a group. This is why, in one embodiment of the invention, the user phase also includes a bit-slip error search and correction phase if the first block is the same on the data channel. Therefore, the possibility of slip detection is maintained while the point of synchronization is shifted by 0 bit cells, +1 bit cells or -1 bit cells after this first block is detected without error. This approach results in a much lower probability of uncorrectable errors in the second and subsequent blocks.

The present invention is advantageous in that it does not require large scale processing means. In particular, a limited memory capacity (less than 4K bytes) is sufficient.

The invention also relates to a device for carrying out the method described above.
Such a device includes a universal decoder consisting of a demodulation component and a clock recovery component. Its input is the multiple output of the radio receiver (mu
ltiplex output). The device also includes a microprocessor for processing broadcast data. Its output is connected to another microprocessor which controls the radio receiver. The output from the general-purpose decoder is applied to various uses, and the uses are determined by the surrounding conditions to which the data is applied, the contents of the data, the target quality level, the safety level, and the like.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings and examples.

"Structure on which the present invention is based" FIG. 1 is a diagram showing a structure of a data channel. The largest component is, for example, one group with N = 4 blocks. Each block J (J = 1 to J = 4) has an n1 bit information word MJ and an n2 bit control word
Composed of CJ. The European Broadcasting Union RDS system recommendations include 16-bit information words and 1
It is stated that a 0-bit control word, and therefore one block has n1 + n2 = 26 bits.

FIG. 2 is a diagram showing the generation of the syndrome SJ for one block of (n1 + n2) bits. This generation is performed by multiplying a parity check matrix whose size is (n1 + n2) × n2 bits. As a result, the syndrome becomes an n2-bit bit string. The syndrome calculations for non-systematic codes are done in a corresponding manner.

"Description of Decoding" FIG. 3 is a flowchart showing the decoding process of the present invention. This process is based on the control word CJ of each block on the transmitter side.
It is possible to add a so-called offset word to (EXCLUSIVE ORED which performs an exclusive OR operation for each bit). The content of each offset word has a one-to-one correspondence with the position of the control word (hence the block) within the group. For the structure of FIG. 1, four different offset words are sufficient. However, for structural reasons the above RD
The S system has 7 different offset words.
Therefore, some of these offset words could be used for other purposes besides indicating the position of the block within the group, for example to indicate the type of block or the type of the group. But that information is not used at the level of the present invention.

The flowchart of FIG. 3 begins at input 60. Although the data bit is received in the air, its relative position within the block or group of blocks is not yet clear. The part above the broken line 62 in this figure is the initialization phase, that is, the synchronization phase. In other words, the decrypted data is not yet considered to be reliable as long as the system is in this synchronization process. Box 42 represents the initialization phase. By the way, the syndrome SJ of the block composed of the first (n1 + n2) bits and the offset word added to this are calculated. In order to limit the time and memory capacity for this calculation, the incremental calculation which increments the count of the syndrome SJ by 1 is made as follows: for each data bit received, a preliminary syndrome
Bit string s the bit string incremented by this
updated by i, the most recent data bit is the last (u
ltimate) Contributing towards the data bit string SJ. This continues until the main counter counting the data bits reaches position (n1 + n2). It is possible in principle to realize synchronization in this respect. So the system is a frame
Proceed to 44, which has two exits. In box 44, a comparison is made between the syndrome SJ actually generated and the standard syndrome SW, provided that each of the standard syndromes SW is generated only on the basis of a specific offset word WJ.
Note that the offset word is a pseudo error word (quasi
-Error word). These pseudo error words are present in the comparison register means RC. Thus, in the setting of Figure 1 there will be at least four such standard syndromes. If the comparisons are all negative, there are two possibilities: the position of the block window is incorrect, or the received data is incorrect. On a no output (0 side), the system goes to box 40 and attempts to correct the position of the block window. Each next following (next-following)
The syndrome is further updated for the data bit b (n1 + n2 + k). This wipes out the contribution of the data bit b (k), and the data bit b (n1 + n2 +
It is performed by adding the contribution of k) to the syndrome bit string, and this operation is symbolically shown in the box. If the value of k reaches (n1 + n2), then the position of the window should have been correct; in that case the result of the comparison was definitely wrong, but the third The illustrated system continues repositioning the block window, which in principle could be infinite. More sophisticated measures, such as setting timeouts (signaling unavailable connections), etc., are outside the scope of the invention. Due to the linearity of the code (the sum of two code blocks again representing one code block), bit errors outside the block window do not contribute to the syndrome. Also, due to the linearity of this code, in frame 42, the incremental generation of the syndrome SJ, that is, each next bit plays its role with respect to the syndrome, the contribution of the previous bit is less than recomputation. , Can be done.

Thus, if the number of errors is small enough, in some cases the comparison in box 44 will give a positive result (on the one side) and the system will proceed to box 46. We assume that the previous window is in the correct position and that the previous standard syndrome identity is known. Therefore, the standard syndrome (s) for the next expected offset word (s) are selected from the compare register means. It should be noted that this prediction is in the exceptional case (in the case of exactly N different offset words), otherwise it is unknown. For example, if N = 4 and there are 7 offset words, the expected number of offset word syndromes may vary from 1 to 4. In box 46, the next syndrome S (J + 1) is then calculated in exactly the same way as it did in box 42. At the end of the calculation, box 50 is contrasted with the syndrome (s) in which the new syndrome S (J + 1) was selected from the comparison register means. The result is an affirmation or denial of the match, as was done in Box 44. If the result is negative, the system considers that there is no synchronization in box 42.
Return to If the result is positive, the system assumes that the synchronization is correct and the original data processor or dashed line 62
Proceed to the lower user phase. The degree of safety can be further increased if the process of boxes 46 and 50 can be repeated one or more times, while a secondary counter keeps track of the number of this repetition and it is predetermined. If the level is reached, the broken line 62 can be exceeded. For some applications, it is sufficient if only one comparison in box 44 is correct and the output goes immediately to box 48. Below the dashed line 62, the two most recently received blocks are considered correct (more blocks are considered correct if the secondary counter described above is used). The system can then send the data word (s) of one (most recent) block or more of these correct blocks to the user. This operation is shown in box 48 labeled "BUS": this is done at the bus 23 indicated by the thick arrow in the decoding device shown in FIG. The details of the apparatus shown in FIG. 5 will be described later. Between the microprocessor 14 integrated with the clock generator and the demodulator and the microprocessor 22 for controlling the receiver, an 8-bit wide bus is provided.
It is this bus 23 that receives the correct code information extracted from the signal received by the antenna 20. Next frame 46
The / 50 operation is repeated in box 52/54. In box 54 each time the same comparison is made as in box 50 for the appropriate syndrome (s). If the comparison shows that there is no error, the system goes via box 68 to box 48 where the information word can be sent to the user. A frame 68 called an "error strategy block" will be described later. In principle, the loop of frames 48, 52, 54 and 68 can be executed continuously. However, in contrast to box 50, error protection is also taken into account here. Therefore, if a discrepancy exists (0 side of box 54), the system proceeds to box 56. In box 56, an error protection operation is performed on a block of (n1 + n2) bits that are error protected without an associated offset word, and the original syndrome is used. The offset word is ignored by subtracting it (similar to the bitwise exclusive or operation EXCLUSIVE ORING).
Various signal forms can occur in RDS systems as a particular application: they have a single bit error in the signal, the data word is corrected; b. There is a compound error in the signal, and possibly with it. The error burst length is shown; c. There is an uncorrectable error in the signal (two or more bit errors not in a single burst, or burst error greater than 5). Is. Box 58 analyzes whether these signal forms can be corrected. When the answer is "correctable" (side of 1), it goes to the frame 48 via the frame 70 which is the "error handling strategy block", and the information word can be sent to the user there. In principle, as before, the loops of frames 48, 54, 52, 58, 70 can be executed continuously. If box 58 determines that the error is uncorrectable, the system proceeds to box 66. Box 66 assesses the actual status of the error protection strategy. This actual state is represented by a numerical value. If this number is low (on the 1 side),
The system proceeds to box 64. With Mushroom, the first message can be sent to the user. This first message would signal "information word cannot be retrieved".
The system then proceeds to box 72, which is the "Error Handling Strategy Block". From there the system proceeds to box 52. Therefore, no synchronization error is said to have occurred, but the information word was not ready to be sent to the user and box 48 is bypassed. However, if the numerical value is found to be high (on the side of 0) in the box 66, it is considered that it is lost in synchronization, and the system proceeds to the box 74. 2 with mushrooms
The second message can be sent to the user.
This second message would signal "sync lost". After that, the synchronization process restarts. As a variation of the setting of FIG. 3, the test frame 66 could be connected directly to the negative output of frame 54, with the two outputs of frame 66 being connected to frame 74 and frame 56, respectively. Various other interconnection schemes have been successful. Let's think about the “Error Handling Strategy Blocks” 68,70,72.

Error handling strategy blocks 68, 70, 72 relate to updating the values in the error register. The first possibility of this measure is to increase the value by one if there is one uncorrectable error (box 72), or if there is no error (box 68) or one correctable error. There is a method to reset the numerical value to 0 if it is in a state. The second possibility of this measure is to increase the number by 2 if there is one uncorrectable error, increase the number by 1 if there is one correctable error, and if there are no errors. For example, there is a thing to return the value to 0. Other measures that take into account the amount of error in a block can be used, for example increasing the number by 1 for a 1-bit error and 2 for a correctable burst error. If there is one uncorrectable error, the value is increased by 5, and if it is the correct block, it is returned to 0. It is likewise possible to use further measures that take into account the history of recent errors.

The critical value (crit that determines when synchronization is lost in box 66).
ical value) depends on various criteria. As a general rule, this value will also increase if the number of blocks that should continue to be received without error in the synchronization phase increases. For example, if the reception conditions are good, then two subsequent blocks in the synchronization phase must be received without error (as in Figure 2). Then the critical value would be between 16 and 64. On the other hand, if the reception condition is bad, it can be said that there is synchronization if only one block has no error in the synchronization phase. Then, the critical value can be lowered, for example, only 4. The reception condition should be determined dynamically, for example, based on only the amplitude or the so-called received broadcast electric field strength, or the well-known multipath condition (mu).
lti-pass condition-the coexistence of various transmission lines due to reflection of buildings, etc.), or alternatively based on the past transition between the synchronization phase and the user phase.

In some channel configurations, the first block of a group always has the same information word. Therefore all blocks incremented by only one offset word are always the same. In this regard, FIG. 4 illustrates the detection and correction of bit slip errors. Once the first block (of any group) is decoded without error (box 54 in Figure 3)
As soon as it is done, it is stored in the other register as it was originally received. When the first block of any subsequent group is received, it is compared with the stored block. This comparison is done by bitwise exclusive-or operation, and at a position once estimated to be correct (80 in FIG. 4), with a 1-bit offset in each of the two possible directions ( 82,8 in Fig. 4
4) is executed. If the comparison shows that the correct position should be wrong, but either of the other two positions is good, then the sync window (windo
w) is shifted in the corresponding direction. Another strategy is to perform slip detection only after the first block is found uncorrectable, and box 58 also takes the block number into account. Since various operations in the flow chart are time-consuming, it may be necessary to time-share the processing functions of the microprocessor or the microcontroller, for example. Such may occur if the error correction operation is not yet ready before box 52 needs to take into account the first bit of the next block. Therefore, the calculation for determining the time shift may take a considerable amount of time to produce a result, which may occur after the processing of the second block has already started. Therefore, it is very unlikely that the second block will be error free or "correctable error" if there is a bit slip.
By the way, in the above-mentioned RDS system, the second block of words is crucial: if it is lost, the rest of the group is considered lost. In FIG. 3, in order to deal with this, the frame 66 takes into account the block number as well.
If the “block number” cannot be corrected, the calculation of the frame 48 is temporarily stopped for the remaining blocks of the group. However, in order to avoid the second block becoming uncorrectable in the case of forward slip, at that time 2
Delay the calculation for the th block by one bit position. This means, in one way, to exclude the first bit: the first bit actually received is then the second bit of the block and the calculation also adapts to this slip. When multiplying the parity check matrix, the first multiplication is therefore performed on the second row, and so on. This will cause the slip to be translated as "always 0" for the first data bit. If this bit is 0 then no problems occur. If this bit was a 1, it means (and yet another) single bit error, which is almost always correctable. A higher level solution is to actually advance the syndrome calculation for block 2 to consider the last bit of block 1 (assuming slip is 0) for both block 1 and block 2. For the 2nd block, only one bit position represents a negative slip. The actual slip of block 1 is known after the (n1 + n2) bits have been taken into account for block 2. This slip is
When taking values of 1 bit, 0 bit, and +1 bit, the system must execute the operation of the frame 40 in FIG. 3 0 times, 1 times, and 2 times, respectively. Similar considerations apply to block # 1.

[Explanation of the Embodiment of the Apparatus] FIG. 5 is a schematic view of an apparatus for executing the decoding method of the present invention. The element 20 is a broadcast signal receiving antenna.
Element 21 is a conventional radio receiver or tuner. The radio receiver is bidirectionally connected to its controlling microprocessor or microcomputer 22. Such controls are commonplace in today's systems. Element 15 performs low frequency decoding and audible signal amplification. Elements 16 are left channel and right channel loudspeakers, respectively. The rest of the device is used for digital data processing. First of all, another small microprocessor or microcomputer 14 is provided. This is a clock generator 12 in a small component 11
And is easily integrated with the demodulator 13. The clock generator and demodulator are fed by the multiple outputs of the radio receiver 21. The information word is retrieved from the broadcast signal according to the invention and sent to the microprocessor 22 on an 8-bit wide bus 23. The component 11 operates in a completely independent manner from the microprocessor 22. Microprocessor
The programming of 22 can be configured independently of the functionality of component 11. In this way, the component 11 outputs the user word, the block number, the error data for each block, and if necessary, the accumulated error data indicating the actual state of the error recovery procedure. The bus data format is irrelevant to the present invention and one of several known general purpose bus formats may be employed accordingly. The microprocessor 22 processes the user word, i.e. stores it in the non-volatile RAM 17, and displays it on a visible display, not shown in the drawing.
It is converted into an audio signal output or used as a control signal for the radio receiver 21.

FIG. 6 is a schematic view for further functionally explaining a part of the device according to FIG. Input 100 is the radio receiver 21 shown in FIG.
Supplied by Element 102 is the hearing device (int
errogation device), checking input 100 at regular time intervals signaled by control signals on line 104. Element 106 receives the binary encoded input value from element 102, determines the optimum position of the bit cell boundary, and from there determines the intent of the inquiry position to be signaled on line 104. Furthermore, element 106 demodulates the channel bits and the sequence of data bits is output on line 108.
Element 110 performs the incremental matrix multiplication shown in boxes 40, 42, 46 and 52 of FIG. 3, while the increments are added to the accumulator registers. Elements 112 represent memory for standard syndromes, each of which corresponds to a predetermined offset word. Element 116 is a selection section, which activates either the full standard syndrome or only some of them selected for comparison with the actual syndrome. Element 114 is the actual comparator,
The preferred embodiment operates on 10-bit syndromes received in parallel. The result evaluation element 118 is notified whether the result is positive or negative. The evaluation result element 118 provides a signal to the element 110 that conveys the positive output of box 44 or the negative output of box 44 (indicating the calculation of the next syndrome or the update of the syndrome, respectively). Element 118 also signals in boxes 50 and 66 whether the next syndrome is calculated synchronously or asynchronously. Element 118 selects whether to open all standard syndromes for comparison, or only specific subgroups of one or more standard syndromes.
Signal to. Element 118 to element 122, line
Signals that the block received from 108 must be evaluated for error correction. Thereby error correction is undertaken in element 112, the corrected information word is sent to element 124 and the correction result (single error corrected, burst error corrected, no error, uncorrectable) is passed to element 118. Sent. So element 118 holds element 120, which holds a number that shows the history of past errors.
To consult. This number is updated and put back in place. Based on these results, output gate 124 is ready to send or an appropriate user message is output 126.
Either it is sent up. Bitslip detection is performed with appropriate delays in various comparison operations.

[Brief description of drawings]

FIG. 1 is a diagram showing the basic structure of a data channel, FIG. 2 is a diagram showing how to calculate the syndrome of a data channel, and FIG. 3 is a decoding process according to the present invention. FIG. 4 is a diagram illustrating a flowchart of FIG. 4, FIG. 4 is a diagram illustrating detection and correction of a slip error, FIG. 5 is a schematic diagram of a device that executes the decoding method of the present invention, and FIG. FIG. 3 is a schematic diagram further functionally explaining a part of the device. 12 ... Clock generator 13 ... Demodulator 14 ... Microprocessor or microcomputer 15 ... Low frequency decoding and audio signal amplification section 16 ... Left channel and right channel loudspeakers 17 ... Non-volatile RAM 20 ... Antenna for receiving broadcast signals 21 ... Radio receiver or tuner 22 ... Microprocessor or microcomputer for controlling receiver 23 ... 8-bit wide bus

Claims (14)

(57) [Claims] 1. A method for decoding data transmitted on a data channel, the data being arranged in a series of groups, N, n1 and n2.
Where and are positive integers, each group contains a fixed number N of contiguous blocks, each block contains an n1-bit information word, the information word being (n1 + n2) by applying a linear error protection code. Bit errors are expanded into protected blocks, and each error protected block in the group is added with a predetermined offset word by bitwise exclusive OR operation (EXCLUSIVE ORING). , The offset word indicates the position of the error protected block within the group, the decoding method comprising the following steps: (a) in the initialization phase: (i) a sequence Receiving a sequence of (n1 + n2) data bits from the channel; (ii) incrementing from the sequence of (n1 + n2) data bits A step of generating a first syndrome using an operation that increments the side-by-side count, each increment operation including exactly one data bit received most recently, whereby the first Is a step of having a plurality of bits; (iii) a step of comparing the first syndrome with a standard syndrome indicating each position, and the standard syndrome indicating the position includes all possible offset words. (Iv) if the comparison yields no match: (A) excluding the earliest received data bit from the (n1 + n2) number of data bits; and (B) ) Including one more recently received data bit to update the first syndrome; (v) Serial to match the standard syndrome showing a position corresponding to one of the predetermined offset word is obtained, the step (iii) and step (i
v) and thus the synchronization is established; (b) In the user phase following the steps in the initialization phase (a): (i) The next (n1) received through the data channel.
+ N2) generating an associated syndrome for each of the blocks of + n2 bits; (ii) comparing the associated syndrome with a standard syndrome indicating at least one suitable position, wherein Each of the blocks has a position that is considered to be the next following position in the series; (iii) If a match is obtained, output the first strategy control signal value that represents it; In addition, a step of outputting the information word of the block to the user; (iv) If a match cannot be obtained, perform an error correction operation on the block of (n1 + n2) bits protected from the error without the associated offset word. , And a step of outputting a second strategy control signal value representing it; (c) the first strategy control signal value and the first strategy control signal value in a predetermined time sequence. Note that if the second strategy control signal value occurs, the step of restarting the initialization phase (a) is restarted, thereby restarting the initialization phase when the number of errors becomes too large; A decoding method comprising the steps of: 2. The decoding method according to claim 1, wherein the step of the initialization phase (a) and the user
An initialization phase step is further added between the steps of phase (b), which are the following steps: (d) generating a syndrome upon receiving a data block of the channel; (e) step (d). ) Is compared with the standard syndrome associated with it to indicate the position; (f) If the comparison result of step (e) is negative, the step of initialization phase (a) is restarted. Step; (g) repeating steps (d) and (e) until a successive repeating comparison yields a positive result and the comparison reaches a predetermined number of times; (h) comparison is predetermined. When the number of times reached is reached, the steps of advancing to the step of the user phase (b); Decoding method to be. 3. A device for decoding data transmitted on a data channel, said data being arranged in a series of groups, N, n1 and n2.
Where and are positive integers, each group contains a fixed number N of contiguous blocks, each block contains an n1-bit information word, the information word being (n1 + n2) by applying a linear error protection code. Bit errors are expanded into protected blocks, and each error protected block in the group is added with a predetermined offset word by bitwise exclusive OR operation (EXCLUSIVE ORING). , The offset word indicates the position of the error protected block within the group, in a decoding device: (a) receiving means for receiving a stream of data bits from the data channel; ) Multiply each received data bit by a parity check matrix that increments a 1-bit string to generate a syndrome bit string (C) selecting means for indicating a position; (d) comparing an arbitrary syndrome bit string with a standard syndrome bit string for indicating the position under the control of the selecting means for indicating a position. Compare register means for: (e) deactivate said selection means in the initialization phase, but activate said selection means under the control of a sequence of a predetermined length of positive comparison result. Initialization phase / use phase control means for switching to the user phase, (f) outputting the information word contained in the associated channel block under the control of the positive comparison result in the user phase, and Under the control of the negative comparison result in the user phase, which has the first state for outputting the first strategy control signal. An error evaluation device having a second state for activating an error protection device that executes an error protection operation and outputting a second strategy control signal; (g) the first strategy control signal and the second strategy Error register means for switching the initialization phase / user phase control means to the initialization phase under the control of the predetermined time sequence supplied with a control signal; Decoding device. 4. The initialization phase / user phase control means is for counting means for counting an uncorrupted sequence of at least two positive comparisons predetermined before switching to the user phase. Decoding device according to claim 3, characterized in that: and all negative comparison results in said initialization phase serve to bring the initialization phase back to its starting point. . 5. The second strategy control signal is for controlling the error register means depending on the type of error.
4. The decoding device according to claim 3, characterized in that the type of error actually found is specified. 6. A bit-slip detection means for comparing a predetermined block of channel data, when stored, with various shifted positions of the subsequently received predetermined block of channel data. 4. The decoding device according to claim 3, wherein the decoding device comprises an output of the bit slip detecting means for controlling the comparison output so as to compensate for the bit slip. 7. The bit-slip detecting means operates on a predetermined block within one group, and a bit-slip correcting means is provided for the next block in the same group. The decoding device according to claim 6, characterized in that: 8. The error register means includes a counter capable of returning to zero, the counter incrementing by one due to an uncorrectable error, but all other first and second counters.
8. Returning to 0 by the th strategy control signal; and a predetermined position of the counter controlling the switching to said initialization phase; The decoding device according to any one of 1. 9. The invention of claim 8 wherein the predetermined counter position is adjustable.
The decoding device according to the item. 10. The error register means includes a counter capable of returning to zero, the counter incrementing by one by an arbitrary second strategy control signal and returning to 0 by an arbitrary first strategy control signal. The decoding device according to any one of claims 3 to 7, wherein a predetermined position of a counter controls switching to the initialization phase. 11. A broadcast receiver for receiving a broadcast signal and for deriving the data bit sequence from the broadcast signal, the broadcast receiver further measuring a quality level of the broadcast signal and measuring the quality level of the broadcast signal. Measuring means for deriving a switching control signal from a level; said switching control signal being either said predetermined length of said predetermined time sequence or said predetermined time during said initialization phase / user phase. Decoding device according to any one of claims 3 to 7, characterized in that it acts to adjust either of the critical values of the defined time sequence. 12. A radio receiver and a first microcomputer for controlling the radio receiver, comprising a demodulation component and a clock recovery component, the inputs of which are connected to multiple outputs of the radio receiver. And a second microcomputer for processing broadcast data, the output of which is connected to the data input of the first microcomputer. The decoding device according to any one of claims 3 to 7. 13. The first microcomputer outputs at least one further piece of data relating to a state of error protection or a block configuration in addition to the information word of the block, as claimed in claim 12. The decoding device according to the item. 14. The decoding device according to claim 12, wherein the data input is a general-purpose bus connection.