JP2024134681A - Wiring board and method for manufacturing the same - Google Patents

Abstract

[Problem] To provide a multilayer wiring board capable of reducing parasitic inductance and parasitic resistance of components constituting a high-frequency circuit formed on a core board. [Solution] The multilayer wiring board of the present invention is a wiring board having a core board having a first surface and a second surface, and an insulating resin layer formed on the first surface of the core board, the core board has a through electrode formed between the first surface and the second surface, the first surface of the core board has components constituting a high-frequency circuit, the components constituting the high-frequency circuit have a lower electrode and a dielectric formed above the lower electrode, the insulating resin layer has an interlayer via part at a position where it overlaps with the dielectric on the surface above the dielectric, the lower electrode and the dielectric have an overlapping part with the through electrode on the first surface, and a capacitor is formed by an upper electrode consisting of the lower electrode, the dielectric and the interlayer via part. [Selected Figure] Fig. 17

Description

The present invention relates to a wiring board and a method for manufacturing a wiring board.

In recent years, mobile communication devices have become more and more sophisticated, and there is a demand for greater density and miniaturization of the electronic components and multilayer wiring boards used in these devices. At the same time, there is also a growing demand for higher-frequency characteristics.

To date, materials such as ceramics, glass, and insulating organic resins have been used for the multilayer wiring boards used in mobile communication devices. Of these, glass materials have excellent flatness, smoothness, and electrical insulation properties, so they are expected to be in high demand as a material for multilayer wiring boards for high-frequency applications using millimeter waves from 5G onwards.

(Glass core substrate)
Packaging technologies that use glass include multilayer wiring boards that use glass as the core substrate material, form conductive layers on the front and back surfaces of the core substrate, and form through electrodes in the core substrate to connect the front and back surfaces of the core substrate.
Such multilayer wiring boards have conductive layers and insulating layers provided on the front and back surfaces, and the respective wiring patterns are formed by a subtractive method or a semi-additive method.

In addition, by creating and combining passive elements such as capacitors (symbol C) and coils (symbol L) on the front and back of the glass or inside the core board, the board can be given a function with frequency response characteristics. This makes it possible to obtain high-frequency components with LC circuits. Examples of high-frequency components obtained in this way include low-pass filters, band-pass filters, antenna couplers, diplexers, and baluns, and can be used in high-frequency circuits.

(passive elements/coils)
Here, the coil, which is one of the passive elements, is formed into a solenoid, helical, or spiral shape by patterning a conductor on the front and back of the core substrate or in the through holes, and by arranging it on a laminated section using the front and back of the core substrate and other insulating layers, a coil with any desired inductance value (unit: H) can be obtained.
In recent years, the self-inductance of the wiring itself is also sometimes used as part of a passive element in a circuit.

(passive elements/capacitors)
Capacitors, which are passive elements, are commonly used to obtain capacity, or capacitance (unit: F), by forming a metal-insulator-metal (MIM) structure consisting of a conductor-dielectric-conductor on the front and back of a core glass.

(Resonance of inductors and capacitors)
In addition, in high-frequency circuit design, LC circuits can be used in combination with other passive and active components and can also be employed as impedance matching, tuning circuits, and resonant circuits.

In particular, there is a trend toward using even higher frequencies in high-frequency circuits, and passive circuit elements are required to have small inductance and capacitance values and high Q values. The Q value is the impedance of an element divided by the parasitic resistance component, and therefore it is necessary to take into consideration the structure and materials that may become parasitic resistance components in the element. In particular, when it comes to structure, it is necessary to consider, for example, the configuration of the lead-out wiring for connecting elements and the connection parts between pads and vias, and it is desirable to reduce the parasitic components of the elements themselves.

In order to obtain a low-capacitance capacitor using conventional methods, the thickness of the dielectric has been increased or the electrode area has been reduced to reduce the capacitance of the capacitor, but in order to make the dielectric thicker, the deposition time for the dielectric must be increased, which reduces productivity.

Patent Document 1 discloses the following technology for a wiring board on which a capacitive element that suppresses capacitance variation is mounted. "The wiring board 100 has a substrate 102 having a through hole 104, a first wiring 110 that continuously covers the sidewall of the through hole, the first surface of the substrate, and the second surface of the substrate, a first dielectric film 116-1 on the first wiring, a first insulating film 118 on the first dielectric film that has an opening overlapping the first dielectric film, and a second wiring 122-1 located on the first insulating film and overlapping the first wiring. The wiring board may further include a metal layer 132 between the first dielectric film and the second wiring, which contacts the first dielectric film and the second wiring."

JP 2019-016636 A

In general, high-frequency circuits formed on a glass substrate are often formed by utilizing a part of a conductor layer connected to a through hole provided in the glass substrate. Therefore, components constituting the high-frequency circuits formed on the glass substrate may have unintended parasitic inductance and parasitic resistance. These parasitic components may degrade the filter characteristics of the resonant circuit.
However, in Patent Document 1, the positional relationship between the core substrate and the passive elements is not fully considered, and there is a need to comprehensively consider the components that make up the high-frequency circuit to further improve the high-frequency characteristics and to further improve the efficiency of the manufacturing method for multilayer wiring substrates.

The present invention aims to provide a multilayer wiring board that can reduce parasitic inductance and parasitic resistance for components that make up a high-frequency circuit formed on a core substrate.

The present invention has been made in consideration of these problems, and one representative multilayer wiring board of the present invention is a wiring board having a core substrate having a first surface and a second surface, and an insulating resin layer formed on the first surface of the core substrate, wherein the core substrate has a through electrode formed between the first surface and the second surface, and the first surface of the core substrate has components that constitute a high-frequency circuit.
The components constituting the high-frequency circuit have a lower electrode and a dielectric formed above the lower electrode, and the insulating resin layer has an interlayer via portion on the upper surface of the dielectric at a position where it overlaps with the dielectric.
Furthermore, on the first surface, the lower electrode and the dielectric have an overlapping portion with the through electrode, and a capacitor is formed by the lower electrode, the dielectric, and an upper electrode made up of the interlayer via portion.

Moreover, one representative multilayer wiring board of the present invention is a method for producing the multilayer wiring board described above,
a first step of forming a pattern of the first conductive layer on the first surface;
a second step of forming a dielectric over the pattern of the first conductive layer;
a third step of forming a photosensitive resin layer so as to cover the pattern of the first conductive layer and the dielectric, and forming an interlayer via above the dielectric by photolithography;
A fourth step is provided of forming a second conductive layer that becomes the upper electrode on a surface of the interlayer via, and forming a capacitor by the lower electrode, the dielectric and the upper electrode.

The present invention provides a multilayer wiring board that can reduce parasitic inductance and parasitic resistance for components that make up a high-frequency circuit formed on a core substrate.

Cross-sectional view showing a state in which a support is attached to a glass substrate. Cross-sectional view showing a state in which a laser modified portion is formed on a glass substrate. FIG. 1 is a cross-sectional view illustrating a state in which a first conductive layer is formed on a glass substrate. FIG. 2 is a cross-sectional view showing a state in which the first conductive layer is patterned. FIG. 1 is a cross-sectional view showing a state in which a dielectric layer is formed on a first conductive layer. FIG. 1 is a cross-sectional view of a conventional example showing a state in which an upper electrode is formed on a first conductive layer. FIG. 1 is a cross-sectional view of a conventional example showing a state in which an insulating resin layer is formed and an interlayer via is formed. FIG. 1 is a cross-sectional view of a conventional example showing a state in which a conductive film is formed in an interlayer via and a second conductive layer is formed. FIG. 1 is a cross-sectional view of a conventional example showing a state in which a support is attached to the upper side and a support is peeled off from the lower side. FIG. 1 is a cross-sectional view of a conventional example showing a state in which a through hole is formed in a glass substrate. Cross-sectional view of a conventional multilayer wiring board A cross-sectional view showing a state in which an insulating resin layer and an interlayer via are formed. Cross-sectional view showing the state in which supports are bonded to the top and bottom of the glass substrate 1 is a cross-sectional view showing a state in which the support below the glass substrate has been peeled off; 1 is a cross-sectional view showing a state in which a through hole is formed in a glass substrate. FIG. 11 is a cross-sectional view showing a state in which a third conductive layer is formed in the through hole. 1 is a cross-sectional view of a multilayer wiring board according to an embodiment of the present invention; Graph showing inductance comparison with the conventional example

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the present invention is not limited to this embodiment. In addition, in the description of the drawings, the same parts are denoted by the same reference numerals.

Note that the positions, sizes, shapes, ranges, etc. of components shown in the drawings may not represent their actual positions, sizes, shapes, ranges, etc., in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, etc., disclosed in the drawings.

Furthermore, in this disclosure, "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Also, "upper surface" and "lower surface" refer to the surface shown at the top or bottom on the drawing when the plate-shaped member or a layer contained in the plate-shaped member is illustrated.

Further, the term "side surface" refers to a surface of a plate-like member or a layer included in a plate-like member, or a cross-sectional portion of a layer.
Furthermore, a portion of the surface and the opposite downward direction may be referred to as the +Z-axis direction and the -Z-axis direction, and the horizontal direction may be referred to as the "X-axis direction" and the "Y-axis direction."

In the present disclosure, a "core substrate" is a substrate that has electrical insulation properties and is made of a material with a linear expansion coefficient close to that of silicon, for example, a substrate made of an inorganic material such as glass or glass ceramic.
It is desirable for the core substrate to have a loss factor (tan δ) of 70×10 −4 or less in a frequency band exceeding 1 GHz, and a loss factor (tan δ) of 50×10 −4 or less in a frequency band of 40 GHz or less.
In the present disclosure, a glass substrate may be used as the core substrate, and the glass substrate may have through holes formed therein and may be coated with a metal layer, a dielectric layer, an insulating layer, or the like.
Furthermore, the glass substrate typically has optical transparency, and the components of the glass material constituting the glass substrate and the compounding ratio thereof are not particularly limited. For example, glass containing silicate as a main component, such as alkali-free glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, and photosensitive glass, can be used as the glass substrate.
From the viewpoint of use in semiconductor packages and semiconductor modules, it is desirable to use alkali-free glass as the glass substrate 10. The content of alkali components contained in the alkali-free glass is preferably 0.1 mass % or less.
The thickness of the glass substrate is preferably 1 mm or less, and more preferably 0.1 mm to 0.8 mm in consideration of ease of handling during production.
Furthermore, the surface of the glass substrate may be treated by a method commonly used in the art, for example, the surface may be treated with hydrofluoric acid, or the surface of the substrate may be treated with silicon.

In the present disclosure, the conductive layer and the insulating layer formed in sequence on the upper and lower surfaces of the core substrate in the thickness direction (Z-axis direction) may be collectively referred to as a build-up layer. The insulating resin layer may be a single layer or multiple layers.
In the embodiments described below, an example in which one conductive layer is provided on each of the front and back sides of the core substrate will be described, but the number of laminated layers formed as the build-up layer can be determined arbitrarily.
The insulating resin layer does not necessarily have to be formed on both sides of the core substrate, but may be a single surface layer on either the front or back of the core substrate, and may be symmetric or asymmetric in the vertical direction around the core substrate.
In this disclosure, "upward" means in the positive direction of the Z axis in the drawings.
Furthermore, "components constituting a high frequency circuit" refers to components constituting an electronic circuit intended for use with high frequency signals of 0.1 GHz or higher, and includes capacitors, coils, etc.

In this disclosure, "having overlapping portions on a surface" means that there are overlapping portions on a plane when the surface is viewed from the normal direction of the surface. This includes cases where one area is entirely contained within the other area, as well as cases where they completely overlap.

In the present disclosure, a "through hole" generally refers to a hole that extends from a first surface of a glass substrate to a second surface opposite to the first surface, and does not necessarily need to completely penetrate from the first surface to the second surface of the glass substrate. In addition, after the through hole is formed, a conductive material is filled inside the hole, or a conductive layer is formed on the inner wall of the hole, and an insulating material such as a resin is filled in the center of the hole, thereby forming a through electrode.
The cross-sectional shape of the through hole formed in the glass substrate may be rectangular, X-shaped, i.e., a shape in which the diameter at the center is smaller than the diameter at one end and the diameter at the other end of the through hole, tapered, i.e., a shape in which the diameter at the one end and the diameter at the other end of the through hole are smaller than the diameter at one end of the through hole, O-shaped, i.e., a shape in which the diameter at the center is larger than the diameter at one end and the diameter at the other end of the through hole, or other shape. The shape of the opening of the through hole in the first surface or the second surface of the glass substrate may be circular, elliptical, or polygonal.

In the present disclosure, the "bottom" of a through hole means a surface of the through hole or a conductive film or insulating film in contact with the through hole that is in contact with the first surface or the second surface of the glass substrate.
Furthermore, when the cross section of a through hole is tapered, the end with a smaller diameter is sometimes referred to as the "Bottom" and the end with a larger diameter is sometimes referred to as the "Top."

In this disclosure, an opening that connects the upper and lower surfaces of an insulating layer is referred to as an "interlayer via," and in particular, when the insulating layer is made of a photosensitive resin, an opening formed in the photosensitive resin layer is referred to as a "columnar via." Therefore, a "columnar via" is a type of "interlayer via."

The conductive material used in the present disclosure can be formed using copper, silver, tin, gold, tungsten, conductive resin, etc. Copper is preferably used.
The conductive layer can be formed by a subtractive method, a semi-additive method, an inkjet method, screen printing, gravure offset printing, etc. A semi-additive method using a photobia method is preferable, but the method is not limited to these.

In the semi-additive method of the present disclosure, for example, (1) an insulating film is formed on a conductor circuit, and then vias for interlayer connection are processed by laser irradiation, and a desmear process is performed to remove resin residue. (2) Then, the substrate is subjected to a sputtering process or electroless copper plating process, and a pattern is formed with a dry film resist, and then electrolytic copper plating is performed to form a circuit pattern of a conductive layer. (3) Finally, the resist is stripped, and the sputtered layer or electroless layer is flash etched to form a circuit pattern of the conductive layer.
However, instead of via processing by laser irradiation, a photovia method may be used in which vias are formed in one step by photolithography.

In the present disclosure, the insulating resin layer can be formed using an epoxy resin-based material, an epoxy acrylate-based resin, a polyimide-based resin, or the like. These insulating materials may contain a filler. As the insulating material in the present disclosure, an epoxy-blended resin with a linear expansion coefficient in the range of 7 ppm/K or more and 130 ppm/K or less is generally easy to obtain and is preferable.

The insulating resin layer may be in a liquid state, a film state, a negative type, or a positive type. When the insulating material is in a liquid state, the insulating resin layer can be formed by a method such as a spin coating method, a die coater method, a curtain coating method, a rule coater method, a doctor blade method, or a screen printing method.
When the insulating material is in the form of a film, the insulating resin layer can be formed by, for example, a vacuum lamination method. The insulating resin layer thus formed may be cured by heating or light irradiation.
Furthermore, the insulating resin layer is desirably a photosensitive resin composition or a photovia material that has adhesion to a conductor, has excellent insulating reliability, and can form an interlayer insulating resin layer.

<Conventional Example>
First, a conventional multilayer wiring board and a method for manufacturing the same will be described with reference to FIGS.
(Note that Figs. 1 to 5 are common to the conventional example and the embodiment of the present invention.)
1 and 2 are diagrams showing a process of forming a modified portion by irradiating a laser onto a core substrate having a support.
1, a glass substrate 10 is used as a core substrate, and the respective surfaces of the glass substrate 10 are designated as a first surface 11 and a second surface 12. A glass carrier 80 is attached to the second surface 12 side of the glass substrate 10 as a support.
In FIG. 2, a laser is irradiated from a first surface of a glass substrate 10 to form a laser modified portion 13 .
The laser modified portion 13 is formed so as to penetrate the glass substrate 10, and the laser modified portion 13 reaches the inside of the glass carrier 80 which is the support body.

3 and 4 are diagrams showing a process for forming a conductive layer above the first surface 11 of the glass substrate 10. In this process, a hydrofluoric acid resistant film 14b is first formed on the exposed surface of the glass substrate 10 that has been subjected to laser modification, and then a conductive layer 14a is formed. The conductive layer 14a and the hydrofluoric acid resistant film 14b are collectively referred to as the first conductive layer 14. This first conductive layer is patterned as shown in FIG.
In FIG. 4, the conductive layer 91a and the hydrofluoric acid resistant metal film 91b formed above the central laser modified portion 13 constitute the lower electrode 91 of the capacitor.

Figure 5 shows the process of forming a dielectric 92 above a lower electrode 91. The dielectric 92 can be obtained by forming a dielectric layer over the entire surface using a known film formation method and then patterning it.

Figure 6 shows the process of forming the upper electrode 93. In this process, the upper electrode 93 of the capacitor is formed by forming a sputtered layer 93b and an electrolytic plating layer 93a on the dielectric.

Figure 7 is a cross-sectional view of an insulating resin layer 30 formed on the top surface of a layer on which an MIM capacitor is formed, which includes a first conductive layer 14, a lower electrode 91, a dielectric 92, and an upper electrode 93, and after protecting the circuit pattern, an opening for a columnar via 50 is provided in the insulating resin layer 30.

FIG. 8 is a diagram showing a process of forming an insulating resin layer 30 and a conductor layer in the holes of the columnar vias 50. As shown in FIG.
After the sputtered layer 15 a is formed, the electrolytic plating layer 15 b is formed, and the second conductive layer 15 is formed.

Figure 9 shows the process of attaching the glass carrier 80, which serves as the support, onto the second conductive layer and separating the support below the glass substrate 10.

Figure 10 shows the process of etching the laser modified portion 3. In this process, hydrofluoric acid etching is performed on the laser modified portion 3 to form a through hole 22 in the glass substrate 10.

11 is a cross-sectional view of a multilayer wiring board 100 in which a circuit pattern that is subjected to conductive treatment is formed in the through hole 22. Conductive treatment is performed on the through hole 22 and the lower surface of the glass substrate 10 described in FIG. 10, and a third conductive layer 16 is formed inside the through hole 22 and on the lower surface of the glass substrate 10. Thereafter, a circuit pattern can be formed as a build-up layer over any number of layers below. Specifically, a desired multilayer wiring can be constructed by repeating the formation of a circuit pattern by applying an insulating resin layer, forming an opening, and forming a conductive layer using a known technique.
Thereafter, the upper glass carrier 80 is peeled off, thereby obtaining the multilayer wiring substrate 100 .

<Embodiments of the present invention>
Next, a multilayer wiring board and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS.
The cross-sectional views shown in Figures 1 to 5 are the same as those of the conventional example, and the multilayer wiring board of the conventional example and the multilayer wiring board of this embodiment differ in that in the conventional example, an upper electrode 93 is formed on the top of a dielectric 92 as shown in Figure 6, whereas in this embodiment, an upper electrode 93 is not formed.
In the following description, components that are the same as or similar to those in the above-described conventional example are given the same reference numerals, and their description may be simplified or omitted.

In this embodiment, a glass substrate 10 is used as the core substrate. Glass is suitable as a core substrate in terms of its surface smoothness and dimensional stability.

<Method of Manufacturing a Multilayer Wiring Board>
Hereinafter, the method for manufacturing a multilayer wiring board according to this embodiment will be described with reference to FIGS. 1 to 5 and 12 to 17.

(Formation of modified portion)
First, a process of forming a modified portion 3 by a laser on a core substrate 1 will be described with reference to Figs. 1 and 3. Fig. 1 is a diagram showing a process of attaching a glass substrate 10, which will be a core substrate, to a glass carrier 80, which is a support. Here, the glass carrier 80 is attached to the second surface of the glass substrate 10. When attaching, an adhesive layer containing a hydroxyl group is formed between the glass carrier 80 and the glass substrate 10, and an adhesive force is generated between the glass carrier 80 and the glass substrate 10 by hydrogen bonding. In addition, a method of using an adhesive between the glass carrier 80 and the glass substrate 10 may also be adopted. In the following embodiment, a method of using an adhesive will be described, but the attaching method is not limited to this.

2 is a diagram showing a process of irradiating a laser to the glass carrier 80 and the glass substrate 10 to form the laser modified portion 13. Here, a laser is irradiated from the first surface 11 side of the glass substrate 10 to form the laser modified portion 13 on the glass substrate 10. The focus of the laser is set to stay within the glass carrier 80. In this manner, the laser modified portion 13 is formed uniformly from the first surface 11 side of the glass substrate 10 to just before reaching the glass carrier 80.
In addition, when the thickness (length in the Z-axis direction) of the glass substrate 10 is d1 and the thickness of the glass carrier 80 is T, d1 is preferably in the range of 0.5 mm to 1.5 mm in consideration of transportability after thinning. Furthermore, T may be appropriately set depending on the thickness of the glass substrate 10.
Furthermore, the glass substrate 10 and the glass carrier 80 may have the same thickness or different thicknesses.
The glass carrier 80 may be replaced with a support made of metal or resin.

(Laser processing conditions/wavelength)
The following describes the laser used to form the laser modified portion 13. The wavelength of the laser used is preferably 535 nm or less. The wavelength is more preferably in the range of 355 nm or more and 535 nm or less.
On the other hand, if the wavelength is greater than 535 nm, the irradiation spot becomes larger, and it may be difficult to control the position and size of the modified portion 3 to be formed. In addition, due to the influence of heat, the processing becomes ablation rather than modification processing, and microcracks occur in the core substrate, making it more likely to break. By increasing the energy of the laser pulse, it is possible to increase the length (depth) of the laser modified portion 13 in proportion to the energy.

(Formation of the first conductive layer)
3 to 5, a process for forming the first conductive layer 14 will be described. Here, a conductive layer is formed on the glass substrate 10. The first conductive layer includes a hydrofluoric acid resistant film, an electroless plating layer, a seed layer (not shown), and an electrolytic plating layer (not shown).
3, a hydrofluoric acid resistant film 14b is formed on the first surface 11 side of the glass substrate 10. The hydrofluoric acid resistant film 14b is formed to serve as an etching protection film when the laser modified portion 13 is etched to form an opening.

(Formation of hydrofluoric acid resistant film)
3 is a diagram showing a process for forming the hydrofluoric acid resistant film 14b. As shown in the figure, the hydrofluoric acid resistant film 14b is formed by a sputtering method or the like on the first surface 11 of the glass substrate 10. The hydrofluoric acid resistant film 14b is formed to a thickness in the range of 10 nm to 500 nm.

The material of the hydrofluoric acid resistant film 14b can be appropriately selected from, for example, chromium, nickel, and nickel chromium. This prevents the glass core substrate 1 from corroding during the etching process. This prevents the etching process from affecting the shape and dimensions of the through-holes, improving dimensional stability. In the following of this embodiment, a case where chromium is used as the material of the hydrofluoric acid resistant film 14b will be described.

(Plating Formation)
3, a process of laminating a conductive layer on the upper surface of the hydrofluoric acid resistant film 14b to form the first conductive layer 14 will be described. First, a copper film serving as a seed layer is formed on the hydrofluoric acid resistant film 14b by a sputtering method, an electroless plating method, or the like. The thickness of the seed layer is formed in the range of 100 nm to 500 nm.

Next, in FIG. 4, photoresist is patterned on the first conductive layer 14. As an example, a pattern is drawn on the first surface 11 side using a dry photoresist manufactured by Showa Denko Materials Co., Ltd., and then developed to expose the seed layer.

Next, power is supplied to the seed layer to form an electrolytic copper plating layer having a thickness of 2 μm or more and 10 μm or less. After that, the photoresist that is no longer necessary after electrolytic plating is dissolved and stripped, and the seed layer is flash etched. Furthermore, the hydrofluoric acid resistant film 14b is removed using a chrome etching solution, thereby forming a first conductive layer 14 consisting of the hydrofluoric acid resistant film 14b, the seed layer, and the plating layer having the pattern shown in FIG. 4.

(Formation of dielectric layer)
Next, referring to FIG. 5, a process for forming a dielectric 92 on the patterned first conductive layer using a plasma CVD process or the like will be described.
The dielectric 92 is formed on the pattern of the first conductive layer 14. Any known method can be applied for forming the dielectric, and for example, a method for forming SiN, SiO ₂ , TaOx, or the like by plasma CVD can be selected.

(Formation of Interlayer Insulation Layer)
Next, a method for manufacturing a multilayer wiring board specific to this embodiment will be described with reference to Fig. 12. In the conventional example, as shown in Fig. 6, after forming a dielectric 92, an upper electrode 93 is formed above the dielectric 92. However, in this embodiment, after forming the dielectric 92 on a lower electrode 91, which is a first conductive layer, an insulating resin layer 30 is formed as shown in Fig. 12.
In this case, the insulating resin layer 30 is preferably made of a photosensitive insulating resin material.
In this embodiment, a photosensitive insulating resin is formed by vacuum press lamination on a conductor circuit, which is a conductor layer of the substrate, and then the columnar vias 50 are processed by exposure and development.The photosensitive material is then cured by post-curing using post-UV curing and/or thermal curing, to form an insulating resin layer 30 that serves as an interlayer insulating film.

(Interlayer via formation)
When a photovia material is used, after the formation of the insulating resin layer 30, exposure to light (light exposure) is performed to form the columnar vias 50 on the dielectric layer. Development is used to form the columnar vias 50, and either wet development or dry development may be used.
The thickness of the columnar via 50 is, for example, 3 μm or more.

(Method of Exposing Photosensitive Insulating Resin Material)
The exposure method may be a direct imaging exposure method such as a mask exposure method, an LDI (Laser Direct Imaging) exposure method, or a DLP (Digital Light Processing) exposure method.

(developing)
The composition of the developer is appropriately selected depending on the composition of the photosensitive resin composition, and examples thereof include an alkaline aqueous solution such as an aqueous solution of tetramethylammonium hydroxide (TMAH) and an aqueous developer.

Next, vias are formed in the insulating resin layer 30 by photolithography, and then a desmear process is performed.
Next, as shown in FIG. 13, a seed layer is formed on the via, and then a columnar via 50 is formed using the semi-additive method described above (i.e., a series of processes including resist pattern formation, plating, resist stripping, seed layer removal, and insulating layer formation).
Finally, a necessary circuit layer is formed using a resist pattern, a seed layer is formed, and the second conductive layer 15 is formed by electrolytic plating. Thereafter, unnecessary portions of the seed layer are removed.

Flash etching is performed to remove any remaining seed layer between the wiring, and is carried out using an acidic, oxidizing solution such as sulfuric acid and hydrogen peroxide.

(Transferred to second support)
Next, with reference to FIG. 13, a process of transferring a laminate consisting of the glass substrate 10 and the lower glass carrier 80 to the upper glass carrier 80 will be described.
13 is a diagram showing a process of attaching the upper glass carrier 80 to the insulating resin layer 30 in which the columnar vias are formed. Here, an adhesive is applied to the upper surface of the second conductive layer 15 formed on the glass substrate 10. The upper glass carrier 80 is attached to the laminate via the adhesive.

FIG. 14 is a diagram showing a process of separating the lower glass carrier 80 from the glass substrate 10. As shown in FIG.
Here, the glass carrier 80 and the glass substrate 10 are peeled off from the interface therebetween. For example, a physical force is applied to the interface between the glass carrier 80 and the glass substrate 10 to perform a scribing process, and the interface between the glass carrier 80 and the glass substrate 10 is peeled off from the scribing as a starting point. Here, it is necessary to perform the process so that no residue is left on the second surface 12 of the glass substrate 10.
When there is a risk of residue remaining, laser ablation, chemical treatment, plasma cleaning, ultrasonic cleaning, or the like may be performed in combination with mechanical peeling, if necessary.

(Formation of through holes)
FIG. 15 is a diagram showing a process of etching the laser modified portion 13. As shown in FIG.
The glass substrate 10 is immersed in a hydrogen fluoride solution while the glass carrier 80 is attached. In this manner, the glass substrate 10 is thinned and the laser modified portion 13 is removed to form the through hole 22. In addition, the formation of a buried wiring groove, which is a groove formed in a portion where the buried wiring will be formed later, can also be performed simultaneously with the formation of the through hole 22 in the glass substrate 10.

The amount of etching with the hydrogen fluoride solution can be appropriately set depending on the thickness of the glass device. For example, when the thickness d1 of the glass substrate 10 used before thinning is 400 μm, the amount of etching is preferably in the range of 100 μm to 350 μm. The thickness d2 of the glass substrate 10 after thinning is preferably in the range of 50 μm to 300 μm.
According to the manufacturing method of this embodiment, the formation of the through holes 22 and the thinning of the glass substrate 10 are performed simultaneously, so that the substrate can be processed with high precision in a stable state that is close to flat. Therefore, even if the high-frequency circuit elements are formed above the through holes, it is possible to maintain high precision of the individual circuit elements.

(Conductive treatment of through holes/wiring grooves and formation of insulating resin)
Next, the conductive treatment process will be described with reference to FIG. 16. FIG. 16 is a diagram showing the process of conducting the through hole 22. First, seed layers 16a and 16b for power supply are formed from the second surface 12 side of the glass substrate 10 in which the through hole 22 is formed, and then a circuit pattern is formed using a dry film photoresist. Next, power is supplied to the seed layer to form an electrolytic plating 16c having a thickness of 2 μm to 10 μm. Then, the unnecessary dry film photoresist is dissolved and peeled off. In this way, the through electrode 20 formed on the inner surface of the through hole 22 and the third conductive layer 16 having a predetermined pattern formed on the second surface 12 of the glass substrate 10 are formed.
The seed layer exposed after dissolving the photoresist of the dry film is removed by etching. The material of 16a, 16b, and 16c can be selected from nickel, titanium, copper, etc. for the purpose of adhesion, or may be selected to change the magnetic permeability and control the inductance of the through electrode.
In addition, passive components such as capacitors can be formed as circuit elements of a high-frequency circuit directly above (vertically above) the through electrode 20. The thickness of the conductor layer inside the through hole can be appropriately selected in consideration of the thickness required for the conductor layer on the glass surface.

(Formation of insulating resin layer on the lower surface)
For the third conductive layer 16, the same method as that described in Fig. 11 in the conventional method can be adopted. After applying the insulating resin layer 30 to the glass substrate 10, desired build-up layers can be formed as a laminated structure having any number of layers using known techniques.

(Formation of lower insulating resin layer)
Fig. 17 is a cross-sectional view of the multilayer wiring board described in Fig. 16 after the glass carrier 80 is peeled off by a known method and a build-up layer including a third conductive layer is additionally formed. In the figure, the conductive layers formed in multiple layers are shown in a simplified manner in some places.
The insulating resin layer 30 used in the build-up layer can be formed from a thermosetting resin. The insulating resin used as the material for the insulating resin layer 30 preferably contains at least one of epoxy resin, polyimide resin, and polyamide resin, and a filler material of _SiO2 , and is a liquid or film-like material. In the case of liquid resin, the insulating layer can be formed by spin coating, and in the case of film-like resin, a vacuum laminator is used to heat and pressurize under vacuum.
The material of the insulating resin layer 30 can be appropriately selected according to need. However, when a photosensitive insulating resin material is used, it becomes difficult to fill the _SiO2 filler material in order to ensure photolithography, so it is preferable to use a non-photosensitive thermosetting resin, but a photosensitive insulating resin may be used for the insulating resin layer 30.

(Making interlayer vias conductive)
In FIG. 17, the columnar vias 50 and other interlayer vias 53 formed above the dielectric 92 may have conformal (along the inner circumferential surface) vias or may be completely filled with a conductor.

(series resonant circuit)
In this embodiment, the through electrode 20 is disposed in the negative Z-axis direction of the lower electrode forming the capacitor, and the self-inductance of the through electrode itself can be utilized to form a series resonant circuit. For example, by setting the inductance of the line of the through electrode to 0.06 to 1.4 nH, a series resonant circuit can be formed with the capacitor located above.

(effect)
The effects of this embodiment will be described below with reference to FIG.

In this embodiment, the columnar vias 50 are not formed on the upper electrode 93 as in the conventional example, but are formed on the dielectric 92, which has a larger area than the upper electrode 93. This has the advantage that it is easy to prevent the columnar vias from falling off due to misalignment, and there is no need to design the upper electrode 93 to be larger than necessary.

In addition, in this embodiment, by using a photosensitive material without a filler for the interlayer insulating resin, it is no longer necessary to form the upper electrode by a sputter seed layer and electrolytic plating, and a photovia can be used as the upper electrode.
This makes it possible to obtain a small, low-capacitance MIM capacitor with high precision.

Furthermore, when forming the upper electrode 93 as in the conventional example, a second conductive layer is formed above the upper electrode 93 by sputtering, electroless plating, or electrolytic plating, and then unnecessary resist used in forming the conductive layer is removed, and the exposed seed layer is removed by flash etching. At this time, the bottom of the upper electrode 93 may be eroded by the flash etching solution, causing a change in dimensions, making it difficult to control the area of the upper electrode in order to obtain a low-capacity capacitor. However, according to this embodiment, since there is no upper electrode 93, there is no risk of flash etching adversely affecting the accuracy of the capacitor.

Furthermore, in high-frequency boards, it is important to reduce parasitic inductance by shortening the wiring, reduce parasitic resistance, and minimize discontinuities where the diameter of the wiring changes in the main line through which the signal passes. According to this embodiment, the number of connections in the circuit element is reduced by two, on the top and bottom surfaces of the upper electrode, compared to the conventional example, which is also advantageous in terms of improving the accuracy of the high-frequency circuit. In other words, because the upper electrode portion is replaced with a photovia, it is possible to reduce impedance discontinuities that occur when setting a registration gap at the boundary between the electrode and the via, and to reduce parasitic inductance.

The graph in FIG. 18 shows a comparison of the simulation results between the present embodiment and the conventional example.
The main conditions on which the simulation was performed were as follows. The sample of the embodiment was a multilayer wiring board having the shape of FIG. 17. The thickness dimension d2 of the glass substrate 10 after the glass substrate 10 was thinned was set to 0.13 mm. The thickness of the insulating resin layer 30 was set to 0.02 mm, and one build-up layer was formed on the front and back sides of the glass substrate 10. The thickness of the glass carrier 80 was set to 1 mm.
On the other hand, the conventional sample is a multilayer wiring board having the shape shown in Fig. 11. The thickness of the core board and the thickness of the insulating resin are the same as those of the sample of the embodiment.

The high-frequency circuit models used in the simulation, which have through holes in the wiring board and have a bottom at the through holes, were prepared in the conventional example and the embodiment of the present invention. HFSS (ver. 2021 R1) manufactured by ANSYS, Inc. was used for the electromagnetic field simulation. The materials and analysis conditions were the same, except for the material of the insulating resin layer 30.
In addition, regardless of whether or not there is an electrode on the dielectric layer, the thickness of the insulating layer is fixed at 20 μm. The diameter of the upper electrode 93 formed by the photovia is 65 μm. The upper electrodes in the conventional example are also unified at 65 μm. The diameter of the columnar via in the conventional example is 40 μm.

In the model, at the self-resonant frequency, the impedance of the circuit becomes infinite and a sudden change occurs in the damping impedance, making it possible to compare the resonant frequency of the resonant circuit with the reduction in parasitic inductance, etc. The smaller the parasitic inductance, the higher the self-resonant frequency shifts to.
As is clear from the results of the comparison between the conventional example and this embodiment in FIG. 18, the attenuation at the resonance frequency can be increased in this embodiment as compared to the conventional example.
In addition, when a MIM capacitor with the same capacitance was used, resonance was confirmed at high frequencies. This is believed to be due to the improvement of the Q value and the reduction of parasitic inductance by eliminating the registration part between the upper electrode and the interlayer via.
18, comparing the conventional example and the present embodiment with a photovia diameter of 65 μm, it can be seen that the increase in inductance value occurs at a high frequency. The difference between the conventional method and the inventive method in the simulation model is the structure of the upper electrode, so in the structure of this embodiment, when the area of the interface in contact with the dielectric is the same, it is possible to design the resonance frequency to be about 3 GHz higher.
In this manner, according to the present invention, a high frequency circuit having a capacitor with small parasitic inductance can be obtained in a multilayer wiring board.

(Other inventions)
The present disclosure also includes the following inventions.
(Aspect 1)
A wiring board having a core substrate having a first surface and a second surface, and an insulating resin layer formed on the first surface of the core substrate,
the core substrate has a through electrode formed between the first surface and the second surface,
The core substrate has components that constitute a high-frequency circuit on a first surface thereof,
The component constituting the high frequency circuit has a lower electrode and a dielectric body formed above the lower electrode,
the insulating resin layer has an interlayer via portion at a position on an upper surface of the dielectric body where the insulating resin layer overlaps the dielectric body;
On the first surface, the lower electrode and the dielectric have an overlapping portion with the through electrode,
a capacitor is formed by the lower electrode, the dielectric, and an upper electrode including the interlayer via portion;
Multilayer wiring board.
(Aspect 2)
The multilayer wiring board according to aspect 1,
The inductance of the line of the through electrode is 0.06 to 1.4 nH, and the multilayer wiring board forms a series resonant circuit together with the capacitor.
(Aspect 3)
The multilayer wiring board according to aspect 1 or 2,
A multilayer wiring board in which the capacitance of the capacitor is controlled by the area of the bottom surface of the interlayer via portion.
(Aspect 4)
A multilayer wiring board according to any one of aspects 1 to 3,
A multilayer wiring board, wherein the bottom surface of the interlayer via portion has a circular or polygonal shape.
(Aspect 5)
A multilayer wiring board according to any one of aspects 1 to 4,
The thickness of the interlayer via portion in the Z-axis direction is 3 μm or more.
(Aspect 6)
A multilayer wiring board according to aspect 5,
The insulating resin layer of the multilayer wiring board is made of a photosensitive resin.
(Aspect 7)
A method for producing a multilayer wiring board according to any one of aspects 1 to 6, comprising the steps of:
a first step of forming a pattern of a first conductive layer on the first surface;
a second step of forming a dielectric over the pattern of the first conductive layer;
a third step of forming a photosensitive resin layer so as to cover the pattern of the first conductive layer and the dielectric, and forming a columnar via above the dielectric by photolithography;
A method for manufacturing a multilayer wiring board, comprising a fourth step of forming a second conductive layer that becomes the upper electrode on a surface of the columnar via, and forming a capacitor by the lower electrode, the dielectric and the upper electrode.
(Aspect 8)
In the method for producing a multilayer wiring board according to aspect 7,
the third step is a step of forming an interlayer via at the same time as a step of forming a columnar via above the dielectric;
The fourth step is a step of forming a second conductive layer also on the surface of the interlayer via, thereby enabling electrical conductivity between the first conductive layer pattern and the second conductive layer formed on the upper surface of the photosensitive resin layer.
A method for manufacturing a multilayer wiring board.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-mentioned embodiment, and various modifications are possible without departing from the gist of the present invention.

10: Glass substrate 11: First surface 12: Second surface 13: Laser modified portion 14: First conductive layer 15: Second conductive layer 16: Third conductive layer 20: Through electrode 21: Bottom portion 22: Through hole 23: Filling material 30: Insulating resin layer 40: Conductive layer 41: Internal wiring layer 42: External wiring 50: Columnar via 51: Pad portion 53: Interlayer via 60: Solder ball 80: Glass carrier 90: Capacitor 91: Lower electrode 92: Dielectric 93: Upper electrode 94: Hydrofluoric acid resistant metal film 95: Copper coating 96: Dry film resist 100: Multilayer wiring substrate

Claims (8)

A wiring board having a core substrate having a first surface and a second surface, and an insulating resin layer formed on the first surface of the core substrate,
the core substrate has a through electrode formed between the first surface and the second surface,
The core substrate has components that constitute a high-frequency circuit on a first surface thereof,
The component constituting the high frequency circuit has a lower electrode and a dielectric body formed above the lower electrode,
the insulating resin layer has an interlayer via portion at a position on an upper surface of the dielectric body where the insulating resin layer overlaps the dielectric body;
On the first surface, the lower electrode and the dielectric have an overlapping portion with the through electrode,
a capacitor is formed by the lower electrode, the dielectric, and an upper electrode including the interlayer via portion;
Multilayer wiring board. 2. The multilayer wiring board according to claim 1,
The inductance of the line of the through electrode is 0.06 to 1.4 nH, and the multilayer wiring board constitutes a series resonant circuit together with the capacitor. 2. The multilayer wiring board according to claim 1,
A multilayer wiring board in which the capacitance of the capacitor is controlled by the area of the bottom surface of the interlayer via portion. 2. The multilayer wiring board according to claim 1,
A multilayer wiring board, wherein the bottom surface of the interlayer via portion has a circular or polygonal shape. 2. The multilayer wiring board according to claim 1,
The thickness of the interlayer via portion in the Z-axis direction is 3 μm or more. 6. The multilayer wiring board according to claim 5,
The insulating resin layer of the multilayer wiring board is made of a photosensitive resin. 2. A method for manufacturing a multilayer wiring board according to claim 1, comprising the steps of:
a first step of forming a pattern of a first conductive layer on the first surface;
a second step of forming a dielectric over the pattern of the first conductive layer;
a third step of forming a photosensitive resin layer so as to cover the pattern of the first conductive layer and the dielectric, and forming a columnar via above the dielectric by photolithography;
A method for manufacturing a multilayer wiring board, comprising a fourth step of forming a second conductive layer that becomes the upper electrode on a surface of the columnar via, and forming a capacitor by the lower electrode, the dielectric and the upper electrode. 8. The method for manufacturing a multilayer wiring board according to claim 7,
the third step is a step of forming an interlayer via at the same time as a step of forming a columnar via above the dielectric;
The fourth step is a step of forming a second conductive layer also on the surface of the interlayer via, thereby enabling electrical conductivity between the pattern of the first conductive layer and the second conductive layer formed on the upper surface of the photosensitive resin layer.
A method for manufacturing a multilayer wiring board.

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