JP2024081161A - Clock recovery circuit, error rate measurement device, and error rate measurement method - Google Patents

Abstract

To provide a clock recovery circuit capable of reproducing a clock from an SSC modulation data signal of a large frequency shift, an error rate measurement device, and an error rate measurement method.SOLUTION: A clock recovery circuit 1 comprises: a reference clock generation section 10 for generating an SSC modulated reference clock; a clock recovery section 20 for reproducing an SSC modulated clock of a data signal, which is SSC modulated in a predetermined SSC modulation frequency, synchronously with the reference clock; an FM demodulation section 22 for generating an FM demodulated signal having the SSC modulation frequency by FM demodulating the SSC modulated clock reproduced by the clock recovery section 20. The reference clock generation section 10 generates the reference clock by SSC modulating a clock of a VCO 14 with the FM demodulated signal and feeds the SSC modulated reference clock back to the clock recovery section 20.SELECTED DRAWING: Figure 1

Description

The present invention relates to a clock recovery circuit, an error rate measurement device, and an error rate measurement method, and in particular to a clock recovery circuit, an error rate measurement device, and an error rate measurement method for recovering a clock from a data signal modulated by a spread spectrum clock.

In recent years, with the spread of IoT (Internet of Things) and cloud computing, communication systems have begun to handle huge amounts of data, and the interfaces of various communication devices that make up the communication systems are becoming faster and more serial in transmission. For example, standards for high-speed serial buses such as USB (registered trademark) (Universal Serial Bus) and PCI Express (registered trademark) (Peripheral Component Interconnect Express) employ SSC modulation using a spread-spectrum clock (SSC) that spreads the spectrum of the reference signal as a measure against Electro-Magnetic Compatibility (EMC).

The SSC modulated data signal (hereinafter also referred to as "SSC modulated data signal") is generated at a timing synchronized with a reference clock that is frequency swept by an SSC modulated wave having a predetermined modulation frequency as shown in FIG. 7(a). For example, an SSC modulated wave of the PCI Express standard has a triangular waveform shape with a period of 33 kHz as shown in FIG. 7(a).

By the way, one of the indicators for evaluating the quality of signals in communication devices is the bit error rate (BER), which is defined as the comparison between the number of bit errors that occurred in the received data and the total number of received data.

In recent years, many of the various communication devices that make up communication systems are designed to transmit only data signals without transmitting a clock for synchronization, and conventional error rate measurement devices that measure BER are equipped with a clock recovery device that recovers the clock from the received data signal.

General-purpose clock recovery devices for high-speed serial communication applications such as the 10G Ethernet (registered trademark) standard are usually designed to handle frequency deviations or bit rate deviations of about ±100 ppm. However, when an SSC modulated data signal of the PCI Express standard, which has a frequency deviation of up to 5,300 ppm, for example, is input to such a clock recovery device, the clock recovery device may unlock or malfunction. In addition, even if the clock recovery device is operating, it may not be able to keep up with the frequency deviation of the SSC modulation.

In such a case, the SSC modulated wave obtained by FM (Frequency Modulation) demodulation of the output of the clock recovery device will have a distorted waveform in which the peak of the original triangular wave shown by the dashed line has been removed, as shown by the solid line in Figure 7(b).

Generally, the loop bandwidth of clock recovery devices for high-speed serial communication is on the order of several MHz to several tens of MHz, which is sufficient to handle modulation frequencies of around 33 kHz for SSC modulation. In other words, conventional clock recovery devices are considered to have insufficient resistance to the SSC modulation of the PCI Express standard because the allowable bit rate deviation for reliably locking to the target frequency is restricted for design reasons.

As shown in Fig. 8, a phase-locked loop circuit PS1 is known that has a phase comparator 51a, a loop filter 52a, a voltage-controlled oscillator 53a, a signal input terminal 57a, a signal output terminal 59a, and a voltage tracking circuit VT1 that is an additional loop, and can be used as a clock recovery device (see, for example, Patent Document 1). The voltage tracking circuit VT1 is composed of a reference voltage generator 58a, a differential amplifier 54a, a filter 55a, and an adder 56a.

The voltage tracking circuit VT1 controls the average value of the output voltage of the phase comparator 51a so that it coincides with the output voltage _VR of the reference voltage generator 58a. Since the voltage tracking circuit VT1 performs feedback control so as to maintain the duty ratio of the output voltage of the phase comparator 51a, the lock range of the phase locked loop circuit PS1 is significantly expanded compared to a phase locked loop without the voltage tracking circuit VT1.

JP 2002-84189 A

However, the phase-locked loop circuit PS1 disclosed in Patent Document 1 has a limit to the expansion of the lock range, and is not suitable for clock recovery corresponding to a maximum frequency deviation or bit rate deviation of 5,300 ppm in SSC modulated data signals.

The present invention has been made to solve these problems in the past, and aims to provide a clock recovery circuit, an error rate measurement device, and an error rate measurement method that can recover a clock from an SSC modulated data signal with a large frequency deviation.

In order to solve the above problems, the clock recovery circuit of the present invention uses SSC (Spread Spectrum The reference clock generating unit generates a reference clock modulated by FM (FM Clock), a clock recovery unit reproduces an SSC-modulated clock of a data signal SSC-modulated at a predetermined SSC modulation frequency in synchronization with the reference clock, and an FM demodulation unit FM demodulates the SSC-modulated clock reproduced by the clock recovery unit to generate an FM demodulated signal having the SSC modulation frequency. The reference clock generating unit has a voltage-controlled oscillator that outputs an output signal having a frequency according to an input control voltage, a reference clock source having a predetermined frequency, a phase comparator that outputs a phase difference signal according to the phase difference with the output signal of the voltage-controlled oscillator, a charge pump that generates a charge/discharge current according to the phase difference signal, a loop filter that outputs a signal obtained by removing high-frequency components from the charge/discharge current, and a signal synthesis unit that adds the FM demodulated signal generated by the FM demodulation unit and the output of the loop filter. The voltage-controlled oscillator is configured to modulate the reference clock with the output signal by inputting the output of the signal synthesis unit as the control voltage.

With this configuration, the clock recovery circuit of the present invention generates an FM demodulated signal that is an SSC modulated wave obtained by FM demodulating the output of the clock recovery section, SSC modulates the clock of the voltage controlled oscillator with the FM demodulated signal to generate a reference clock, and feeds back the SSC modulated reference clock to the clock recovery section. With this configuration, the clock recovery circuit of the present invention uses a general-purpose clock recovery device for conventional high-speed serial communication applications as the clock recovery section, but can improve the durability of the clock recovery section and reproduce the SSC modulated clock by making the frequency of the reference clock follow the frequency of the SSC modulated data signal so as to minimize the frequency deviation between the SSC modulated data signal, which has a large frequency deviation, and the reference clock.

The clock recovery circuit according to the present invention may further include a divider that divides the SSC modulated clock reproduced by the clock recovery unit and outputs the clock to the FM demodulation unit, and a division ratio control unit that controls the division ratio of the divider. The FM demodulation unit may include a delay unit that delays and outputs the SSC modulated clock divided by the divider, an exclusive OR circuit that calculates the exclusive OR of the output of the divider and the output of the delay unit, and a low-pass filter that smooths the output of the exclusive OR circuit to generate the FM demodulated signal. The division ratio control unit may be configured to control the division ratio based on the bit rate of the data signal so that the maximum frequency of the SSC modulated clock input to the exclusive OR circuit is equal to or less than 1/4 of the upper operating frequency limit of the exclusive OR circuit.

With this configuration, the clock recovery circuit of the present invention can recover an SSC modulated clock from an SSC modulated data signal with a large frequency deviation while maintaining the demodulation resolution of the exclusive OR circuit.

The error rate measurement device according to the present invention is an error rate measurement device including a signal receiving unit that receives a data signal SSC modulated at a predetermined SSC modulation frequency, and an error rate calculation unit that calculates the bit error rate of bit string data that constitutes the data signal received by the signal receiving unit, and the signal receiving unit has any of the clock recovery circuits described above, and is configured to extract the bit string data that constitutes the data signal at the timing of the SSC modulated clock recovered from the data signal by the clock recovery circuit.

With this configuration, the error rate measurement device according to the present invention can receive an SSC modulated data signal transmitted from the device under test, and generate an SSC modulated clock from the SSC modulated data signal using any of the clock recovery circuits described above. Furthermore, the error rate measurement device according to the present invention can extract bit string data constituting the SSC modulated data signal at the timing of the generated SSC modulated clock, and measure the BER of this bit string data.

The error rate measurement method according to the present invention includes a signal receiving step of receiving a data signal SSC modulated at a predetermined SSC modulation frequency, and an error rate calculation step of calculating a bit error rate of bit string data constituting the data signal received by the signal receiving step, and the signal receiving step is configured to extract bit string data constituting the data signal at the timing of the SSC modulated clock recovered from the data signal by any one of the clock recovery circuits described above.

The present invention provides a clock recovery circuit, an error rate measurement device, and an error rate measurement method that can recover a clock from an SSC modulated data signal with a large frequency deviation.

1 is a block diagram showing a configuration of a clock recovery circuit according to a first embodiment of the present invention; 4 is a diagram showing an example of a waveform of an SSC modulated clock output from a clock recovery unit included in the clock recovery circuit according to the first embodiment of the present invention; FIG. 1 is a block diagram showing a configuration of a delay detection circuit included in a clock recovery circuit according to a first embodiment of the present invention; 2 is a block diagram showing a configuration of a reference clock generating unit included in the clock recovery circuit according to the first embodiment of the present invention; FIG. FIG. 11 is a block diagram showing the configuration of an error rate measurement device according to a second embodiment of the present invention. 10 is a flowchart showing a process of an error rate measuring method according to a second embodiment of the present invention. FIG. 1A is a diagram showing an example of the waveform of an SSC modulated wave having a predetermined SSC modulation frequency, and FIG. 1B is a diagram showing an example of the waveform of an SSC modulated wave obtained by demodulating the output of a conventional clock recovery device. FIG. 1 is a block diagram showing a configuration of a conventional phase locked loop circuit.

The following describes embodiments of the clock recovery circuit, error rate measurement device, and error rate measurement method according to the present invention with reference to the drawings.

First Embodiment
1 includes a reference clock generating unit 10 that generates an SSC modulated reference clock, a clock recovery unit 20, a frequency divider 21, an FM demodulating unit 22, an amplifier 25, an analog switch 26, an operation unit 27, and a control unit 30. The control unit 30 includes a frequency division ratio control unit 31, a gain control unit 32, a switching control unit 33, and a frequency correction control unit 34.

The following mainly describes the configuration and operation of each part when the analog switch 26, which will be described later, is set to the on state (hereinafter also referred to as "enabled") by the switching control unit 33.

The clock recovery unit 20 reproduces the SSC-modulated clock of the SSC-modulated data signal SSC-modulated at a predetermined SSC modulation frequency in synchronization with the reference clock generated by the reference clock generation unit 10. In other words, the clock reproduced by the clock recovery unit 20 from the SSC-modulated data signal is a clock SSC-modulated like the data signal. A general-purpose clock recovery device for high-speed serial communication applications can be used as the clock recovery unit 20. Here, the SSC modulation frequency is specified for each communication standard, and is, for example, a frequency in the range of 30 to 33 kHz. For example, the SSC-modulated clock output from the clock recovery unit 20 has a pulse rise (or fall) interval and pulse width that change according to the frequency shift of the SSC modulation and the SSC modulation frequency, as shown in FIG. 2.

The frequency divider 21 divides the SSC modulated clock reproduced by the clock recovery unit 20 to a frequency that is easy to handle in the downstream FM demodulation unit 22, and outputs it to the FM demodulation unit 22. If the FM demodulation unit 22 can directly FM demodulate the output of the clock recovery unit 20, the frequency divider 21 may not be necessary.

The FM demodulation unit 22 performs FM demodulation on the SSC modulated clock reproduced by the clock recovery unit 20 to generate an FM demodulated signal having an SSC modulated frequency defined by the communication standard. For example, in the case of the PCI Express standard, the FM demodulated signal has a triangular waveform shape with a period of 33 kHz as shown in FIG. 7(a). There are many different methods for FM demodulation, but the clock recovery circuit 1 according to this embodiment employs a delay detection method that is advantageous for wideband in order to realize wideband (wide bit rate range) clock recovery that can be used in the error rate measurement device described later. That is, the FM demodulation unit 22 performs delay detection on the SSC modulated clock divided by the frequency divider 21, and includes a delay detection circuit 23 and a low pass filter (LPF) 24.

As shown in FIG. 3, the delay detection circuit 23 is composed of a delay unit 23a and a high-speed exclusive OR (EXOR) circuit 23b. In order to ensure the demodulation resolution in the EXOR circuit 23b, it is desirable to set the maximum frequency of the SSC modulated clock input to the EXOR circuit 23b to 1/4 or less of the upper operating frequency of the EXOR circuit 23b. For this reason, the division ratio control unit 31 controls the division ratio of the divider 21 based on the bit rate of the SSC modulated data signal so that the maximum frequency of the SSC modulated clock input to the EXOR circuit 23b is 1/4 or less of the upper operating frequency of the EXOR circuit 23b.

The delay unit 23a delays the SSC modulated clock divided by the frequency divider 21 by 1/4 period of its maximum frequency and outputs it. If the frequency of the SSC modulated clock input to the EXOR circuit 23b is low, the delay time by the delay unit 23a increases, resulting in a trade-off with implementation scale and delay stability, so it is desirable to set the frequency division ratio of the frequency divider 21 taking this into consideration.

The delay unit 23a can be configured, for example, by an element or device such as a fixed delay element or a variable delay device, or by extending the transmission path of a cable or a printed wiring board.

The EXOR circuit 23b is configured to perform an exclusive OR operation between the SSC modulated clock divided by the frequency divider 21 and the SSC modulated clock divided by the frequency divider 21 and delayed by the delay unit 23a. Since the maximum frequency of the SSC modulated clock input from the delay unit 23a is delayed by 1/4 period, the EXOR circuit 23b outputs a clock with twice the frequency of the SSC modulated clock input to the EXOR circuit 23b.

The LPF 24 smoothes the output of the EXOR circuit 23b to generate an FM demodulated signal having an SSC modulation frequency specified by the communication standard. At this time, if there is no error in the delay time added to the SSC modulation clock by the delay unit 23a at the highest frequency of the SSC modulation clock input to the EXOR circuit 23b, the duty ratio of the output waveform of the EXOR circuit 23b will be 50%, and the DC average level (hereinafter also referred to as "DC offset") of the output of the LPF 24 will be a voltage level that is half the output amplitude of the EXOR circuit 23b.

The LPF 24 can be suitably used to have a cutoff frequency in the range of, for example, 3 to 10 times the SSC modulation frequency of 33 kHz, depending on the noise of the FM demodulated signal. Since the cutoff frequency of the LPF 24 is relatively low in this way, it can be configured as a first-order RC low-pass filter. However, the LPF 24 is not limited to an RC low-pass filter and its order, and may be configured as an operational amplifier or an LC low-pass filter.

When the frequency range of the SSC modulated clock input to the EXOR circuit 23b changes, the duty ratio of the output waveform of the EXOR circuit 23b changes, and the DC average value level of the EXOR circuit 23b output also changes. When the maximum frequency of the SSC modulated clock input to the EXOR circuit 23b becomes equal to or greater than 1/4 of the upper operating frequency of the EXOR circuit 23b, the division ratio control unit 31 controls the division ratio of the divider 21 based on the bit rate of the SSC modulated data signal so that the maximum frequency of the SSC modulated clock input to the EXOR circuit 23b becomes equal to or less than 1/4 of the upper operating frequency of the EXOR circuit 23b again.

If the delay amount of the delay unit 23a is a fixed delay amount, when the frequency of the SSC modulated clock input to the EXOR circuit 23b decreases, the DC offset and detection efficiency of the output of the EXOR circuit 23b after passing through the LPF 24 decrease.

For this reason, the amplifier 25 amplifies the FM demodulated signal generated by the FM demodulation unit 22 with a gain set by the gain control unit 32. For example, the gain control unit 32 sets a gain for the amplifier 25 according to the known frequency deviation of the SSC modulation of the SSC modulated data signal input to the clock recovery circuit 1. The gain control unit 32 adjusts the gain of the amplifier 25 to adjust the frequency deviation of the reference clock generated by the reference clock generation unit 10 in the subsequent stage, so that the frequency deviation between the SSC modulated data signal and the reference clock is as small as possible within the range in which the clock recovery unit 20 can lock.

The DC offset component that varies depending on the frequency range of the SSC modulated clock is not necessary in the downstream reference clock generating unit 10. For this reason, it is desirable to appropriately provide a capacitor or a known DC offset cancellation circuit between the FM demodulation unit 22 and the amplifier 25 so that the amplifier 25 can amplify only the AC component of the output of the LPF 24, i.e., the waveform of the SSC modulated wave.

Alternatively, a variable delay device with a variable delay amount can be used as the delay unit 23a to set the optimal delay amount that suppresses the DC offset of the output of the LPF 24 and the decrease in detection efficiency according to the frequency range of the SSC modulation clock.

The analog switch 26 switches between "enabled" and "disabled" feedback of the FM demodulated signal amplified by the amplifier 25 to the reference clock generating unit 10 in the subsequent stage according to the control of the switching control unit 33. For example, when the data signal input to the clock recovery circuit 1 is an SSC modulated data signal, the switching control unit 33 controls the analog switch 26 to be "enabled" in order to superimpose the FM demodulated signal on the reference clock in the reference clock generating unit 10. On the other hand, when the data signal input to the clock recovery circuit 1 is a signal that is not SSC modulated, the switching control unit 33 controls the analog switch 26 to be "disabled", which is the off state, in order to prevent an unnecessary FM demodulated signal from being superimposed on the reference clock in the reference clock generating unit 10.

Immediately after the analog switch 26 is switched from "disabled" to "enabled" by the switching control unit 33, the waveform of the FM demodulation signal output from the FM demodulation unit 22 is distorted, as shown by the solid line graph in Figure 7(b), with the apex of the triangular wave cut off. However, during the period when the triangular wave has its original slope, the frequency deviation between the SSC modulated data signal input to the clock recovery unit 20 and the reference clock becomes small, and the waveform of the FM demodulation signal becomes an ideal triangular waveform as shown in Figure 7(a). Note that the FM demodulation signal output from the FM demodulation unit 22 is a voltage signal, and Figures 7(a) and (b) show the voltage of the FM demodulation signal and the frequency shift proportional to that voltage in arbitrary units.

When the data signal input to the clock recovery circuit 1 is not SSC modulated, the analog switch 26 is set to "disabled" by the switching control unit 33, and the reference clock generating unit 10 generates a reference clock that is not SSC modulated.

As shown in FIG. 4, the reference clock generation unit 10 has a signal synthesis unit 11, a loop filter 12, and a PLL (Phase Locked Loop) unit 13. The PLL unit 13 has a VCO 14, programmable frequency dividers 15a to 15c, a phase comparator 16, and a charge pump 17.

The signal synthesis unit 11 is composed of, for example, an adder circuit using an operational amplifier, and is configured to add the FM demodulation signal generated by the FM demodulation unit 22 and the output of the loop filter 12. The output of the signal synthesis unit 11 is input to the VCO 14 as a control voltage.

The VCO 14 receives the output of the signal synthesis unit 11 as a control voltage, modulates the clock of the VCO 14, generates a reference clock with a frequency approximately proportional to the control voltage input from the signal synthesis unit 11, and outputs the generated reference clock as an output signal. The VCO 14 reduces the frequency deviation between the SSC modulated data signal input to the clock recovery unit 20 and the reference clock, and controls the frequency of the reference clock to follow the frequency of the SSC modulated data signal.

The frequency divider 15a divides the reference clock output from the VCO 14, for example, to a frequency of 1/Na of the baud rate of the SSC modulated data signal, and outputs the frequency to the clock recovery unit 20. The division ratio Na of the frequency divider 15a is set by the division ratio control unit 31 so that the frequency of the reference clock output from the VCO 14 becomes the frequency required by the clock recovery unit 20. Note that if it is sufficient to input the reference clock output from the VCO 14 directly to the clock recovery unit 20, the frequency divider 15a may not be necessary.

The frequency divider 15b sets the center frequency of the reference clock output from the VCO 14 so that it has a division and multiplication relationship with the reference clock source input from an external signal source to the frequency divider 15c. The frequency divider 15b divides the output signal from the VCO 14 as a feedback signal by a predetermined division ratio Nb, and matches the center frequency of the divided feedback signal with the frequency of the output of the frequency divider 15c. The division ratio Nb of the frequency divider 15b is set by the frequency correction control unit 34.

The frequency divider 15c divides the reference clock source input from an external signal source by a predetermined division ratio Nc and outputs the result to the phase comparator 16. The division ratio Nc of the frequency divider 15c is set by the frequency correction control unit 34. The reference clock source is a clock with a fixed frequency (e.g., 40 MHz) that is not SSC modulated.

The frequency correction control unit 34 is configured to set the division ratio Nb and the division ratio Nc so that the center frequency of the reference clock divided by the frequency divider 15b matches the frequency of the reference clock source divided by the frequency divider 15c.

The phase comparator 16 is configured, for example, with an exclusive OR (EXOR) circuit, and outputs a phase difference signal with a pulse width proportional to the phase difference between the reference clock divided by the frequency divider 15b and the reference clock source divided by the frequency divider 15c.

The charge pump 17 generates a charge/discharge current according to the phase difference signal input from the phase comparator 16 and supplies it to the loop filter 12.

The loop filter 12 converts the charge/discharge current supplied from the charge pump 17 into a voltage, removes high-frequency components from the converted voltage, and outputs a smoothed signal to the signal synthesis unit 11. The loop bandwidth of the PLL unit 13 including the loop filter 12 is set to a frequency narrower than the SSC modulation frequency of 30 to 33 kHz (for example, 10 kHz) in order to achieve both the objectives of SSC modulation of the clock of the VCO 14 and stabilization of the center frequency of the reference clock.

This allows the signal synthesis unit 11 to superimpose components outside the loop band of the PLL unit 13 onto the FM demodulated signal and perform SSC modulation directly on the VCO 14. If an attempt were made to perform SSC modulation within the loop band of the PLL unit 13, the modulation would be canceled out by feedback.

When the DC offset component of the FM demodulated signal output from the FM demodulation unit 22 has been removed by a DC offset cancellation circuit or the like, the reference clock generated by the reference clock generation unit 10 is subjected to SSC modulation equivalent to the center spread method. Therefore, when the SSC modulated data signal input to the clock recovery circuit 1 is subjected to SSC modulation of the downspread method or the upspread method, it is desirable to convert the frequency of the reference clock generated by the reference clock generation unit 10 to match the downspread method or the upspread method, for example, by a known method such as that disclosed in JP 2018-156647 A.

For this reason, the frequency correction control unit 34 controls to shift the center of the SSC modulation frequency deviation obtained from the sum of the FM demodulated signal by the signal synthesis unit 11 and the output of the loop filter 12, in other words, controls to shift the center frequency of the reference clock output from the VCO 14, according to the spread method of the SSC modulated data signal input to the clock recovery circuit 1. For example, the frequency correction control unit 34 controls the division ratio of the dividers 15b and 15c to control the center frequency of the reference clock to a frequency corresponding to the desired spread method.

The operation unit 27 is for accepting operation input by the user, and is configured, for example, as a touch panel equipped with a touch sensor for detecting the contact position by a touch operation on an input surface corresponding to the display screen of the display device. Alternatively, the operation unit 27 may be configured to include an input device such as a keyboard or a mouse. Operation input to the operation unit 27 is detected by the control unit 30.

By inputting operations into the operation unit 27 by the user, it is possible to set the setting information required for generating a reference clock from the SSC modulated data signal input to the clock recovery circuit 1, such as whether the data signal input to the clock recovery circuit 1 is an SSC modulated data signal, the bit rate of the SSC modulated data signal, and the selection of the spreading method.

The control unit 30 is composed of a microcomputer or a personal computer including, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), a HDD (Hard Disk Drive), an SSD (Solid State Drive), etc., and controls the operation of each of the above-mentioned components constituting the clock recovery circuit 1, and includes the above-mentioned division ratio control unit 31, gain control unit 32, switching control unit 33, and frequency correction control unit 34. In addition, the control unit 30 can configure at least a part of the division ratio control unit 31, gain control unit 32, switching control unit 33, and frequency correction control unit 34 in software by transferring a predetermined program stored in the ROM or the like to the RAM and executing it. In addition, at least a part of the division ratio control unit 31, gain control unit 32, switching control unit 33, and frequency correction control unit 34 can also be configured with digital circuits such as FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit). Alternatively, at least a portion of the division ratio control unit 31, the gain control unit 32, the switching control unit 33, and the frequency correction control unit 34 can be configured by appropriately combining hardware processing using digital circuits and software processing using a specified program.

As described above, the clock recovery circuit 1 according to this embodiment generates an FM demodulated signal, which is an SSC modulated wave obtained by FM demodulating the output of the clock recovery unit 20, SSC modulates the clock of the VCO 14 with the FM demodulated signal to generate a reference clock, and feeds back the SSC modulated reference clock to the clock recovery unit 20. With this configuration, the clock recovery circuit 1 according to this embodiment uses a general-purpose clock recovery device for conventional high-speed serial communication applications as the clock recovery unit 20, but can improve the durability of the clock recovery unit 20 and reproduce the SSC modulated clock by making the frequency of the reference clock follow the frequency of the SSC modulated data signal so as to minimize the frequency deviation between the SSC modulated data signal, which has a large frequency deviation, and the reference clock.

The clock recovery circuit 1 according to this embodiment controls the division ratio of the frequency divider 21 based on the bit rate of the SSC modulated data signal so that the maximum frequency of the SSC modulated clock input to the EXOR circuit 23b is equal to or less than 1/4 of the upper operating frequency limit of the EXOR circuit 23b. With this configuration, the clock recovery circuit 1 according to this embodiment can reproduce the SSC modulated clock from an SSC modulated data signal with a large frequency deviation while ensuring the demodulation resolution of the EXOR circuit 23b.

Second Embodiment
Next, an error rate measurement device and an error rate measurement method according to a second embodiment of the present invention will be described with reference to the drawings. Note that the same components as those in the first embodiment are given the same reference numerals and the description thereof will be omitted as appropriate. Also, the description of the same operations as those in the first embodiment will be omitted as appropriate.

As shown in FIG. 5, the error rate measurement device 100 according to the second embodiment measures the error rate of an SSC modulated data signal transmitted from a device under test (DUT) 200, and includes a data memory unit 41, a signal transmission unit 42, a signal reception unit 43, a synchronization detection unit 44, an error rate calculation unit 45, a display unit 46, and a control unit 47.

DUT 200 outputs an SSC modulated data signal that is SSC modulated at a predetermined SSC modulation frequency. Examples of standards that DUT 200 supports include PCI Express Gen1-6, USB3.1-4, and DP1.4-2.

The data storage unit 41 is configured with a memory such as a RAM, and stores reference bit string data in advance. Here, the bit string data is data corresponding to K levels, from 0 to K-1, that a PAM signal consisting of multiple values K (K is an integer equal to or greater than 2) of 2 or more values can take. For example, the bit string data of a PAM4 signal, which is a 4-value PAM signal, consists of a combination of bits "00", "01", "10", and "11".

The signal transmitting unit 42 generates a test signal by SSC-modulating the bit string data read from the data storage unit 41 at a predetermined SSC modulation frequency, and transmits the generated test signal to the DUT 200. At this time, the DUT 200 receives the test signal transmitted from the signal transmitting unit 42, and transmits the received test signal to the signal receiving unit 43 as an SSC-modulated data signal. In other words, the DUT 200 transmits a K-value PAM signal SSC-modulated at a predetermined SSC modulation frequency as an SSC-modulated data signal.

The signal receiving unit 43 receives the SSC modulated data signal transmitted from the DUT 200 and outputs the bit string data of the received SSC modulated data signal to the synchronization detection unit 44, and includes the clock recovery circuit 1 of the first embodiment and a bit string data extraction unit 48.

The clock recovery circuit 1 recovers the SSC modulated clock from the SSC modulated data signal transmitted from the DUT 200.

The bit string data extraction unit 48 is configured to extract bit string data constituting the SSC modulated data signal transmitted from the DUT 200 at the timing of the SSC modulated clock reproduced by the clock recovery circuit 1. For example, the bit string data extraction unit 48 has at least one 0/1 judger, and the SSC modulated clock from the clock recovery circuit 1 is input to each 0/1 judger, so that the level of the SSC modulated data signal transmitted from the DUT 200 can be judged at the timing of the SSC modulated clock. Note that the SSC modulated clock output from the clock recovery circuit 1 may be used as an operating clock not only for the bit string data extraction unit 48 but also for each unit constituting the error rate measurement device 100.

The synchronization detection unit 44 synchronizes the bit string data read from the data storage unit 41 with the bit string data of the SSC modulated data signal extracted by the bit string data extraction unit 48. Then, the synchronization detection unit 44 outputs the synchronized bit string data of the SSC modulated data signal to the error rate calculation unit 45.

The error rate calculation unit 45 sequentially compares the bit string data constituting the SSC modulated data signal output from the synchronization detection unit 44 with the bit string data stored in the data storage unit 41 to detect error bits in the bit string data constituting the SSC modulated data signal and calculate the BER of the bit string data constituting the SSC modulated data signal.

The display unit 46 is composed of a display device such as an LCD (Liquid Crystal Display) or a CRT (Cathode Ray Tube), and is configured to display various display contents such as the BER of the bit string data calculated by the error rate calculation unit 45 in response to a control signal output from the control unit 47. Furthermore, the display unit 46 is configured to display operation objects such as buttons, soft keys, pull-down menus, and text boxes for setting various conditions in response to a control signal output from the control unit 47.

The control unit 47 is configured in the same manner as the control unit 30 in the first embodiment, and controls the operation of each of the above-mentioned units constituting the error rate measurement device 100. The control unit 47 can also configure at least a part of the error rate calculation unit 45 in software by transferring a predetermined program stored in a ROM or the like to a RAM and executing it. At least a part of the error rate calculation unit 45 can also be configured with a digital circuit such as an FPGA or an ASIC. Alternatively, at least a part of the error rate calculation unit 45 can be configured by appropriately combining hardware processing by a digital circuit and software processing by a predetermined program. The control unit 47 in this embodiment may also serve as the control unit 30 in the first embodiment.

Below, an example of the process for measuring the error rate according to this embodiment will be described with reference to the flowchart in Figure 6.

First, the signal transmission unit 42 SSC-modulates the bit string data read from the data storage unit 41 at a predetermined SSC modulation frequency to generate a test signal, and transmits the generated test signal to the DUT 200 (step S1).

Next, the clock recovery circuit 1 receives an SSC modulated data signal that has been SSC modulated at a predetermined SSC modulation frequency from the DUT 200, and generates an SSC modulated clock (signal reception step S2).

Next, the bit string data extraction unit 48 extracts the bit string data constituting the SSC modulated data signal at the timing of the SSC modulated clock recovered from the SSC modulated data signal by the clock recovery circuit 1 (signal receiving step S3).

Next, the error rate calculation unit 45 calculates the BER of the bit string data constituting the SSC modulated data signal extracted in step S3 (error rate calculation step S4).

As described above, the error rate measurement device 100 according to this embodiment can receive the K-value PAM signal transmitted from the DUT 200 as an SSC modulated data signal, and generate an SSC modulated clock from the SSC modulated data signal using the clock recovery circuit 1 according to the first embodiment. Furthermore, the error rate measurement device 100 according to this embodiment can extract bit string data constituting the SSC modulated data signal at the timing of the generated SSC modulated clock, and measure the BER of this bit string data.

REFERENCE SIGNS LIST 1 Clock recovery circuit 10 Reference clock generation section 11 Signal synthesis section 12 Loop filter 13 PLL section 14 VCO
15a to 15c Frequency dividers 16 Phase comparator 17 Charge pump 20 Clock recovery section 21 Frequency divider 22 FM demodulation section 23 Delay detection circuit 23a Delay section 23b EXOR circuit 24 LPF
25 Amplifier 26 Analog switch 31 Division ratio control section 32 Gain control section 33 Switching control section 34 Frequency correction control section 41 Data storage section 42 Signal transmission section 43 Signal reception section 44 Synchronization detection section 45 Error rate calculation section 48 Bit string data extraction section 100 Error rate measurement device 200 DUT

Claims (4)

A reference clock generating unit (10) that generates a reference clock modulated by SSC (Spread Spectrum Clock);
a clock recovery unit (20) for recovering an SSC modulated clock of a data signal SSC modulated at a predetermined SSC modulation frequency in synchronization with the reference clock;
an FM demodulation unit (22) that FM demodulates the SSC modulated clock recovered by the clock recovery unit to generate an FM demodulated signal having the SSC modulation frequency;
The reference clock generating unit
a voltage controlled oscillator (14) that outputs an output signal having a frequency corresponding to an input control voltage;
a phase comparator (16) that outputs a phase difference signal corresponding to a phase difference between a reference clock source having a predetermined frequency and the output signal of the voltage controlled oscillator;
A charge pump (17) for generating a charge/discharge current according to the phase difference signal;
a loop filter (12) that outputs a signal obtained by removing high-frequency components from the charge/discharge current;
a signal synthesis unit (11) that adds the FM demodulated signal generated by the FM demodulation unit and an output of the loop filter,
The clock recovery circuit is characterized in that the voltage-controlled oscillator receives the output of the signal synthesis unit as the control voltage, modulates the clock of the voltage-controlled oscillator to generate the reference clock, and outputs the generated reference clock as the output signal. a frequency divider (21) that divides the SSC modulated clock reproduced by the clock recovery unit and outputs the divided clock to the FM demodulation unit;
A frequency division ratio control unit (31) that controls the frequency division ratio of the frequency divider,
The FM demodulation unit includes:
a delay unit (23a) that delays and outputs the SSC modulated clock frequency-divided by the frequency divider;
an exclusive OR circuit (23b) that calculates an exclusive OR between the output of the frequency divider and the output of the delay unit;
a low-pass filter (24) that smoothes the output of the exclusive OR circuit to generate the FM demodulated signal;
2. The clock recovery circuit according to claim 1, wherein the division ratio control unit controls the division ratio based on a bit rate of the data signal so that the maximum frequency of the SSC modulated clock input to the exclusive OR circuit is equal to or lower than 1/4 of an upper limit operating frequency of the exclusive OR circuit. A signal receiving unit (43) for receiving a data signal modulated by a predetermined SSC modulation frequency;
an error rate calculation unit (45) that calculates a bit error rate of bit string data that constitutes the data signal received by the signal receiving unit,
3. The error rate measuring device according to claim 1, wherein the signal receiving section has a clock recovery circuit according to claim 1 or 2, and extracts bit string data constituting the data signal at the timing of the SSC modulated clock recovered from the data signal by the clock recovery circuit. A signal receiving step (S2, S3) of receiving a data signal modulated by a predetermined SSC modulation frequency;
an error rate calculation step (S4) of calculating a bit error rate of bit string data constituting the data signal received by the signal receiving step,
3. The error rate measuring method according to claim 1, wherein the signal receiving step extracts bit string data constituting the data signal at the timing of the SSC modulated clock recovered from the data signal by the clock recovery circuit according to claim 1.

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