JP2023102411A - Serial interface circuit, control method thereof, program, communication module, and communication device - Google Patents

Abstract

To provide a serial interface circuit, a control method thereof, a program, a communication module, and a communication device capable of reducing a decrease in the amount of communication due to a decrease in communication speed on a communication line side.SOLUTION: A data communication unit of a serial interface circuit includes a timing control unit between a transmission-side reception unit and a transmission-side transmission unit, and a buffer for the timing control unit connected to the timing control unit. If communication speed on a communication line side is reduced, the timing control unit generates a trigger reference pulse for each predetermined amount of data determined based on the communication speed on the side of a user-side device such that data from the transmission-side transmission unit is taken in the buffer for the timing control unit. By using timing of the reference pulse, data of a transmittable data amount determined based on the decreased communication speed on the communication line side and the communication speed on the side of the user-side device is transmitted from the buffer for the timing control unit to the transmission-side reception unit.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a serial interface circuit, its control method, program, communication module, and communication device.

A communication device such as a router that mediates data communication between a communication line and a user-side device supports multiple communication speeds, and a speed difference may occur between the communication speed on the communication line side and the communication speed on the user-side device side.

In this case, conventionally, data communication between different communication speeds is made possible by absorbing this speed difference with buffers respectively provided on the transmitting side and the receiving side of the communication device (see, for example, Patent Document 1).

JP-A-2003-249954

The following analysis was made by the inventor.

However, especially in an interface used for high-speed serial communication such as an XFI interface, for example, a serial interface including a transmitting side transmitting section 11 for receiving data from a user side device 15, a transmitting side receiving section 12 for receiving data from the transmitting side transmitting section 11 and transmitting data to a communication line 16, a receiving side transmitting section 13 for receiving data from the communication line 16, and a receiving side receiving section 14 for receiving data from the receiving side transmitting section 13 and transmitting data to the user side device 15 as shown in FIG. When the communication speed (or communication protocol) on the line 16 side is changed from 10GBASE-T (10 Gbps) to 1000BASE-T (1 Gbps), the amount of data transmitted between the transmitting side transmitting unit 11 and the transmitting side receiving unit 12 may drop excessively from 1 Gbps, which is the maximum speed of 1000BASE-T.

This is considered to be based on the following: when the communication speed on the communication line 16 side is made slower than the communication speed between the transmission side transmission section 11 and the transmission side reception section 12, it is necessary to control the amount of packet data from the transmission side transmission section 11 to be equal to or lower than the communication speed on the communication line 16 side. 1 continues to transmit without properly operating, overflow occurs in the buffer provided in the transmitting side receiving section 12, so that the transmitting side transmitting section 11 suppresses transmission more than originally required. As a result, an excessive decrease in the amount of communication with respect to the communication speed on the communication line 16 side occurs.

An object of the present disclosure is to provide a serial interface circuit, its control method, a program, a communication module, and a communication device that contribute to reducing a decrease in communication traffic due to a decrease in communication speed on the communication line side.

According to a first aspect of the present disclosure, there is provided a serial interface circuit including a data communication section including a transmission-side transmission section that receives data from a user-side device, and a transmission-side reception section that receives data from the transmission-side transmission section and transmits data to a communication line. In the serial interface circuit,
The data communication unit further includes a timing control unit provided between the transmission side reception unit and the transmission side transmission unit, and a timing control unit buffer connected to the timing control unit,
When the communication speed on the communication line side is reduced, the timing control unit captures data from the transmission unit on the transmission side into the buffer for the timing control unit, generates a trigger reference pulse for each predetermined amount of data determined based on the communication speed on the user device side, and uses the timing of the reference pulse to extract data of a transmittable data amount determined on the basis of the reduced communication speed on the communication line side and the communication speed on the user device side from the buffer for the timing control unit. It is configured to transmit to the receiving unit on the transmitting side (form 1).
A second aspect of the present disclosure provides a control method for a serial interface circuit. However, the serial interface circuit includes a transmission-side transmission section for receiving data from a user-side device, a transmission-side reception section for receiving data from the transmission-side transmission section and transmitting data to a communication line, a timing control section provided between the transmission-side reception section and the transmission-side transmission section, and a data communication section including a timing control section buffer connected to the timing control section.
The control method is
when the communication speed on the communication line side is lowered, the step of capturing data from the transmission unit on the transmission side into the buffer for the timing control unit;
a step of generating a trigger reference pulse for each predetermined amount of data determined based on the communication speed of the user-side device;
using the timing of the reference pulse to transmit, from the buffer for the timing control unit, the amount of data that can be transmitted, which is determined based on the reduced communication speed of the communication line and the communication speed of the user-side device, to the transmission-side receiving unit;
(Form 6).
A third aspect of the present disclosure provides a program that causes a computer to execute the control method of the present invention (Mode 7).
A fourth aspect of the present disclosure provides a communication module including the serial interface circuit of the present invention (Mode 8).
A fifth aspect of the present disclosure provides a communication device including the communication module of the present invention (Mode 9).
The above program can be recorded in a computer-readable (non-transient) storage medium. That is, the present invention is typically embodied in hardware, but can also be embodied as a computer program product. A program is input to a computer device from an input device or an external communication interface, is stored in a storage device, drives a processor in accordance with predetermined steps or processes, and can display the processing results, including intermediate states, on a step-by-step basis via a display device, or can communicate with the outside via a communication interface. A computer device for this purpose typically includes, as an example, a processor, a storage device, an input device, a communication interface, and optionally a display device, all of which are connectable to each other via a bus.

In the serial interface circuit of form 1, the predetermined data amount can correspond to the maximum data amount of one packet for the communication speed of the user-side device (form 2).
In the serial interface circuit of mode 1 or 2, the amount of data that can be transmitted is
W= _WMAX *( _VN / _VU )
What is required in
However, W is the amount of data that can be transmitted, W _MAX is the maximum data amount of one packet for the communication speed on the side of the user-side device, _VN is the communication speed on the side of the reduced communication line, and _VU is the communication speed on the side of the user-side device (form 3).
In the serial interface circuit of any one of forms 1 to 3, the timing control unit may be further configured to allocate one or more packets to one pulse within a range not exceeding the transmittable data amount (form 4).
In the serial interface circuit according to any one of forms 1 to 4, the data communication unit may further include a reception-side transmission unit that receives data from the communication line, and a reception-side reception unit that receives data from the reception-side transmission unit and transmits the data to the user-side device (form 5).
The communication device of form 9 can be configured as a router (form 10).

The present disclosure or its respective viewpoints can contribute to reducing the decrease in communication traffic due to the decrease in communication speed on the communication line side.

An example of a configuration of an embodiment of a serial interface circuit of the present disclosure. 4 is a flow chart of an example of the operation of one embodiment of the serial interface circuit of the present disclosure; 4 is a timing image of an example of the operation of one embodiment of the serial interface circuit of the present disclosure; 4 is a timing image of another example of the operation of one embodiment of the serial interface circuit of the present disclosure; FIG. 2 is a block diagram schematically showing an example of the configuration of hardware resources; FIG. An example of the configuration of a conventional serial interface circuit.

The outline of the present disclosure will be described below. It should be noted that the drawing reference numerals added to this overview are solely for the purpose of helping understanding of the present disclosure, and are not intended to limit the present disclosure to the illustrated embodiments. Also, connecting lines between blocks in each figure include both bi-directional and uni-directional. Unidirectional arrows schematically indicate the flow of signals, information, data, etc., and do not exclude bidirectionality. Furthermore, connections between blocks in each figure can be wired or wireless. Furthermore, the program is executed via a computer device, and the computer device includes, for example, a processor, a storage device, an input device, a communication interface, and, if necessary, a display device.

Note that the "serial interface" in this disclosure includes any serial interface that can be used for high-speed serial communication, such as the XFI interface.

In addition, the “communication device” in the present disclosure is typically a broadband router, a home gateway device, etc., but is not limited to these, and includes any communication device that is connected to a “communication line” such as the Internet on one side and a “user device” on the other side, mediates data communication between these “communication lines” and the “user device”, and can change the communication speed or communication protocol at least on the “communication line” side.

Furthermore, the “user-side device” in the present disclosure is a relative concept in the sense that it is located on the user side of the communication device including the serial interface circuit or communication module when viewed from the “communication line”. For example, when the "communication device" is a wireless LAN (Local Area Network) device, a slave device or repeater may be included in the "user-side device".

Furthermore, in the present disclosure, "connection" may include both wireless and wired systems.

(embodiment)
FIG. 1 shows an example of a configuration of an embodiment of a serial interface circuit of the present disclosure. In this example, the serial interface circuit is embodied as hardware constituting a communication module incorporated in a communication device such as a router.

The serial interface circuit includes: a transmitting section 1 on the transmitting side that receives data from the user-side device 7; a receiving section 2 on the transmitting side that receives data from the transmitting section 1 on the transmitting side and transmits the data to the communication line 8; a timing control section 3 that is provided between the transmitting section 1 and the receiving section 2 on the transmitting side and is connected to the transmitting section 1 and the receiving section 2 on the transmitting side; 5 to receive data from the receiver-side transmitter 5 and to transmit data to the user-side device 7 including a receiver-side receiver 6 .

The transmitting side receiving section 2 and the receiving side transmitting section 5 can be configured as the same or separate PHY (PHYsical layer) devices or chips, for example.

The transmitting section 1 on the transmitting side, the timing control section 3 and the receiving section 6 on the receiving side can be configured as separate processors, for example. However, the transmitting section 1 on the transmitting side and the receiving section 6 on the receiving side can be configured as the same processor. As the processor, for example, a CPU (Central Processing Unit), MPU (Micro Processor Unit), GPU (Graphics Processing Unit), or the like can be used.

It should be noted that FIG. 1 omits the description of components generally provided in this type of serial interface circuit. For example, the description of the internal buffer provided in the transmitting side receiving section 2 is omitted.

(Operation example)
The operation of the present disclosure will be described below for an example in which the serial interface circuit is configured as an XFI interface circuit, with reference to FIGS. 1 to 4. FIG. FIG. 2 is a flowchart of an example of the operation of the serial interface circuit of the present disclosure, FIG. 3 is a timing image of an example of the operation of the serial interface circuit of the present disclosure, and FIG. 4 is a timing image of another example of the operation of the serial interface circuit of the present disclosure.

In this example, the communication speed on the user-side device 7 side is 10GBASE-X (10 Gbps), and the reduced communication speed on the communication line 8 side is 1000BASE-T (1 Gbps).

In this example, the timing control unit 3 internally generates one pulse as a trigger reference pulse for each maximum data amount (1518 bytes in the case of Ethernet (registered trademark)) of one packet of 10GBASE-X.

Furthermore, in this example, the memory size or capacity of the timing control buffer 4 is several packets to several tens of packets.

First, when the communication speed on the communication line 8 side is reduced to 1000BASE-T (1 Gbps) (see step S1 in FIG. 2), the timing control unit 3 takes the data from the transmitting unit 1 (see FIGS. 3(a) and 4(a)) into the timing control unit buffer 4 (see steps S2 in FIG. 2, FIG. 3(b), and FIG. 4(b)).

Then, the timing control unit 3 determines the amount of data that can be transmitted based on the reduced communication speed of the communication line 8 and the communication speed of the user device 7 (see step S3 in FIG. 2), and transmits the data of this transmittable data amount from the timing control unit buffer 4 to the transmitting side receiving unit 2 using the timing of the reference pulse (step S4 in FIG. 2, see FIG. 3(c) and FIG. 4(c)).

Here, the amount of data that can be transmitted is, for example,
W= _WMAX *( _VN / _VU )
can be calculated as However, W is the amount of data that can be transmitted, W _MAX is the maximum data amount of one packet for the communication speed on the side of the user-side device 7, _VN is the reduced communication speed on the side of the communication line 8, and _VU is the communication speed on the side of the user-side device 7.

In this example, 1/10 (1 Gbps/10 Gbps) of the data amount between reference pulses is a guideline for the amount of data that can be transmitted. Data is transmitted in one pulse within a range that does not exceed this transmittable data amount (in this example, 1/10 of the data amount between reference pulses), and if this range is exceeded, data transmission is stopped until the next pulse.

Specifically, the amount of transmittable data corresponds to the transmittable data range between reference pulses (see FIGS. 3(c) and 4(c)), and a plurality of packets buffered in the timing control unit buffer 4 are each assigned to one transmittable data range and sequentially transmitted to the transmitting side receiving unit 2 (see FIG. 3(c)). On the other hand, when a packet smaller than the transmittable data range is transmitted, a plurality of packets are allocated to one transmittable data range within a range that does not exceed the data amount, and are sequentially transmitted to the transmitting side receiving unit 2 (see FIG. 4(c)).

In FIGS. 3(c) and 4(c), the transmittable data area is longer than the transmittable data area between the reference pulses in order to better express the relationship between the amount of data that can be transmitted and the packet to be transmitted. However, in this example, the length of the former is actually 1/10 of the length of the latter.

As described above, according to the present disclosure, a serial interface circuit for high-speed serial communication, specifically, a timing control unit and a timing control unit buffer connected to the timing control unit are added between a transmission unit on the transmission side and a reception unit on the transmission side. By controlling data transmission, it is possible to suppress or improve a decrease in the amount of data communication caused by a decrease in communication speed on the communication line side.

Depending on the pulse, the communication speed of the communication line 8 may be temporarily exceeded. However, as described above, since the receiving unit 2 on the transmitting side normally has a receiving buffer for several packets to several tens of packets therein, the occurrence of overflow can be avoided. Even if the rate is temporarily exceeded, by reducing the amount of data transmitted by the next pulse to the amount of data that can be transmitted (1/10 of the amount of data between reference pulses in this example) or less, it is possible to adjust the total rate to the target rate when multiple pulses are considered together.

Further, if transmission from the transmission unit 1 on the transmission side continues at a rate that exceeds the communication speed of the communication line 8, the reception buffer of the reception unit 2 on the transmission side and the buffer 4 for the timing control unit will overflow. However, in this case, the timing control unit 3 transmits an interrupt signal to the transmission side transmission unit 1 (a control device such as a CPU) to forcibly stop data transmission from the transmission side transmission unit 1 temporarily, thereby suppressing overflow of these buffers.

Components related to control in the above embodiment can be configured by so-called hardware resources (information processing device, computer), and those having the configuration illustrated in FIG. 5 can be used. For example, hardware resource 100 includes processor 101 , memory 102 , network interface 103 , etc., which are interconnected by internal bus 104 .

Note that the configuration shown in FIG. 5 is not intended to limit the hardware configuration of the hardware resource 100 . The hardware resource 100 may include hardware not shown (for example, an input/output interface). Alternatively, the number of units such as the processors 101 included in the device is not limited to the illustration in FIG. For the processor 101, for example, a CPU (Central Processing Unit), MPU (Micro Processor Unit), GPU (Graphics Processing Unit), or the like can be used.

For the memory 102, for example, RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), etc. can be used.

For the network interface 103, for example, a LAN (Local Area Network) card, a network adapter, a network interface card, or the like can be used.

The functions of hardware resource 100 can be implemented by processing modules. The processing module is implemented by the processor 101 executing a program stored in the memory 102, for example. Also, the program can be downloaded via a network or updated using a storage medium storing the program. Furthermore, the processing module may be realized by a semiconductor chip. In other words, the functions performed by the above processing modules may be realized by executing software in some kind of hardware.

Although the transmission side of the data communication section of the serial interface circuit has been described above, the reception side of the data communication section can be similarly configured. Specifically, by providing a timing control unit to which a timing control unit buffer is connected between the reception-side transmission unit 5 and the reception-side reception unit 6 of the data communication unit, when the communication speed on the user-side device 7 side becomes lower than the communication speed on the communication line 8 side, data or data packets from the reception-side transmission unit 5 can be captured in the timing control unit buffer in the same manner as described above, thereby suppressing a decrease in the communication speed on the user-side device 7 side.

Some or all of the above embodiments may also be described in the following additional remarks, but are not limited to the following.
[Appendix 1] A serial interface circuit including a data communication unit including a transmission-side transmission unit that receives data from a user-side device, and a transmission-side reception unit that receives data from the transmission-side transmission unit and transmits data to a communication line.
The data communication section further includes a timing control section provided between the transmission side reception section and the transmission side transmission section, and a timing control section buffer connected to the timing control section.
When the communication speed on the communication line side is lower than that on the user device side, the timing control unit captures data from the transmission side transmission unit into the buffer for the timing control unit, generates a trigger reference pulse for each predetermined amount of data determined based on the communication speed on the user device side, and uses the timing of the reference pulse to enable transmission determined based on the reduced communication speed on the communication line side and the communication speed on the user device side. It is configured to transmit the amount of data from the buffer for the timing control section to the receiving section on the transmission side.
[Appendix 2] In the above serial interface circuit, the predetermined data amount corresponds to the maximum data amount of one packet for the communication speed of the user-side device.
[Appendix 3] In the above serial interface circuit, the amount of data that can be transmitted is
W= _WMAX *( _VN / _VU )
is required. However, W is the amount of data that can be transmitted, W _MAX is the maximum data amount of one packet for the communication speed on the side of the user-side device, _VN is the communication speed on the side of the reduced communication line, and _VU is the communication speed on the side of the user-side device.
[Appendix 4] In the above serial interface circuit, the timing control unit is further configured to allocate one or more packets to one pulse within a range not exceeding the transmittable data amount.
[Appendix 5] In the serial interface circuit described above, the data communication unit further includes a reception-side transmission unit that receives data from the communication line, and a reception-side reception unit that receives data from the reception-side transmission unit and transmits the data to the user-side device.
[Appendix 6] A method of controlling a serial interface circuit including a data communication unit including a transmission-side transmission unit that receives data from a user-side device, a transmission-side reception unit that receives data from the transmission-side transmission unit and transmits data to a communication line, a timing control unit provided between the transmission-side reception unit and the transmission-side transmission unit, and a timing control unit buffer connected to the timing control unit.
The control method is
when the communication speed on the communication line side is particularly lower than the communication speed on the user side device side, taking data from the transmission side transmission unit into the timing control unit buffer;
a step of generating a trigger reference pulse for each predetermined amount of data determined based on the communication speed of the user-side device;
using the timing of the reference pulse to transmit, from the buffer for the timing control unit, the amount of data that can be transmitted, which is determined based on the reduced communication speed of the communication line and the communication speed of the user-side device, to the transmission-side receiving unit;
including.
[Appendix 7] A program that causes a computer to execute the above control method.
[Appendix 8] A communication module including the above serial interface circuit.
[Appendix 9] A communication device including the communication module described above.
[Appendix 10] The above communication device is configured as a router.
[Appendix 11] In the above serial interface circuit, the receiving section on the transmitting side includes a receiving buffer therein.
[Appendix 12] A serial interface circuit including a data communication section including a reception-side transmission section that receives data from a communication line, and a reception-side reception section that receives data from the reception-side transmission section and transmits data to a user-side device.
The data communication section further includes a timing control section provided between the receiving side receiving section and the receiving side transmitting section, and a timing control section buffer connected to the timing control section.
When the communication speed on the user-side device side is lower than the communication speed on the communication line side, the timing control unit captures data from the reception-side transmission unit into the buffer for the timing control unit, generates a trigger reference pulse for each predetermined amount of data determined based on the communication speed on the communication line side, and uses the timing of the reference pulse to transmit transmittable data determined based on the lowered communication speed on the user-device side and the communication speed on the communication line side. A quantity of data is transmitted from the buffer for the timing control unit to the receiving unit on the receiving side.
[Appendix 13] In the above serial interface circuit, the predetermined data amount corresponds to the maximum data amount of one packet for the communication speed of the communication line.
[Appendix 14] In the above serial interface circuit, the amount of data that can be transmitted is
W= _WMAX *( _VU / _VN )
is required. where W is the amount of data that can be transmitted, W _MAX is the maximum amount of data per packet for the communication speed on the communication line side, _VN is the communication speed on the communication line side, and _VU is the reduced communication speed on the user side device side.
[Appendix 15] In the above serial interface circuit, the timing control unit is further configured to allocate one or more packets to one pulse within a range not exceeding the transmittable data amount.
[Appendix 16] A method of controlling a serial interface circuit including a data communication unit including a receiving-side transmitting unit that receives data from a communication line, a receiving-side receiving unit that receives data from the receiving-side transmitting unit and transmits data to a user-side device, a timing control unit provided between the receiving-side receiving unit and the receiving-side transmitting unit, and a timing control unit buffer connected to the timing control unit.
The control method is
When the communication speed on the user-side device side is particularly lower than the communication speed on the communication line side, the step of capturing data from the reception-side transmission unit into the timing control unit buffer;
a step of generating a trigger reference pulse for each predetermined amount of data determined based on the communication speed of the communication line;
using the timing of the reference pulse to transmit, from the buffer for the timing control unit, the amount of data that can be transmitted, which is determined based on the reduced communication speed of the user device and the communication speed of the communication line, to the receiving unit on the receiving side;
including.
[Appendix 17] A program that causes a computer to execute the above control method.
[Appendix 18] A communication module including the above serial interface circuit.
[Appendix 19] A communication device including the communication module described above.
[Appendix 20] The above communication device is configured as a router.
[Appendix 21] In the above serial interface circuit, the receiving section on the receiving side includes a receiving buffer therein.
[Appendix 22] A serial interface circuit including a data communication section including a receiving section that receives data from one of a communication line and a user-side device, and a transmitting section that receives data from the receiving section and transmits data to the other of the communication line and the user-side device.
The data communication section further includes a timing control section provided between the reception section and the transmission section, and a timing control section buffer connected to the timing control section.
When the communication speed on the transmission unit side is lower than the communication speed on the reception unit side, the timing control unit captures data from the reception unit into the buffer for the timing control unit, generates a trigger reference pulse for each predetermined amount of data determined based on the communication speed on the reception unit side, and uses the timing of the reference pulse to adjust the amount of data that can be transmitted, which is determined based on the reduced communication speed on the transmission unit side and the communication speed on the reception unit side. It is configured to transmit from the control unit buffer to the transmission unit.
[Appendix 23] A method of controlling a serial interface circuit including a data communication section including a receiving section that receives data from one of a communication line and a user-side device, a transmitting section that receives data from the receiving section and transmits data to the other of the communication line and the user-side device, a timing control section provided between the receiving section and the transmitting section, and a timing control section buffer connected to the timing control section.
The control method is
when the communication speed on the transmission unit side is lower than the communication speed on the reception unit side, taking data from the reception unit into the timing control unit buffer;
a step of generating a trigger reference pulse for each predetermined amount of data determined based on the communication speed of the receiving unit;
a step of using the timing of the reference pulse to transmit from the buffer for the timing control unit to the transmission unit a transmittable amount of data determined based on the lowered communication speed on the transmission unit side and the communication speed on the reception unit side;
including.

Within the framework of the full disclosure of the present invention (including the scope of claims), modifications and adjustments of the embodiments and examples are possible based on the basic technical concept thereof. In addition, various combinations or selections (including partial deletion) of various disclosure elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible within the framework of the full disclosure of the present invention. That is, the present invention naturally includes various variations and modifications that can be made by those skilled in the art according to the entire disclosure including claims and technical ideas.

REFERENCE SIGNS LIST 1 transmitting section on the sending side 2 receiving section on the transmitting side 3 timing control section 4 buffer for timing control section 5 transmitting section on the receiving side 6 receiving section on the receiving side 7 device on the user side 8 communication line

REFERENCE SIGNS LIST 11 transmitting unit on transmitting side 12 receiving unit on transmitting side 13 transmitting unit on receiving side 14 receiving unit on receiving side 15 device on user side 16 communication line

100 hardware resources 101 processor 102 memory 103 network interface 104 internal bus

Claims (10)

A serial interface circuit including a data communication section including a transmission side transmission section for receiving data from a user side device and a transmission side reception section for receiving data from the transmission side transmission section and transmitting data to a communication line,
The data communication unit further includes a timing control unit provided between the transmission side reception unit and the transmission side transmission unit, and a timing control unit buffer connected to the timing control unit,
When the communication speed on the communication line side is reduced, the timing control unit captures data from the transmission unit on the transmission side into the buffer for the timing control unit, generates a trigger reference pulse for each predetermined amount of data determined based on the communication speed on the user device side, and uses the timing of the reference pulse to extract data of a transmittable data amount determined on the basis of the reduced communication speed on the communication line side and the communication speed on the user device side from the buffer for the timing control unit. configured to transmit to a sender receiver,
Serial interface circuit. 2. The serial interface circuit of claim 1, wherein
The serial interface circuit, wherein the predetermined amount of data corresponds to the maximum amount of data for one packet with respect to the communication speed of the user-side device. 3. The serial interface circuit according to claim 1, wherein
The amount of data that can be transmitted is
W= _WMAX *( _VN / _VU )
What is required in
However, W is the amount of data that can be transmitted, _WMAX is the maximum data amount of one packet for the communication speed on the side of the user-side device, _VN is the communication speed on the reduced communication line side, and _VU is the communication speed on the side of the user-side device. The serial interface circuit according to any one of claims 1 to 3,
The serial interface circuit, wherein the timing control unit is further configured to allocate one or a plurality of packets to one pulse within a range not exceeding the transmittable data amount. The serial interface circuit according to any one of claims 1 to 4,
A serial interface circuit, wherein the data communication unit further includes a reception-side transmission unit that receives data from the communication line, and a reception-side reception unit that receives data from the reception-side transmission unit and transmits data to the user-side device. A control method for a serial interface circuit including a data communication unit including a transmission-side transmission unit for receiving data from a user-side device, a transmission-side reception unit for receiving data from the transmission-side transmission unit and transmitting data to a communication line, a timing control unit provided between the transmission-side reception unit and the transmission-side transmission unit, and a timing control unit buffer connected to the timing control unit,
when the communication speed on the communication line side is lowered, the step of capturing data from the transmission unit on the transmission side into the buffer for the timing control unit;
a step of generating a trigger reference pulse for each predetermined amount of data determined based on the communication speed of the user-side device;
using the timing of the reference pulse to transmit, from the buffer for the timing control unit, the amount of data that can be transmitted, which is determined based on the reduced communication speed of the communication line and the communication speed of the user-side device, to the transmission-side receiving unit;
including,
control method. A program that causes a computer to execute the control method according to claim 6. A communication module comprising the serial interface circuit according to any one of claims 1 to 5. A communication device comprising a communication module according to claim 8. 10. A communication device according to claim 9, characterized in that it is configured as a router.

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