JP2023183338A - Conductive pattern formation method - Google Patents

Abstract

An object of the present invention is to form a conductive pattern with suppressed plating thickness distribution by a semi-additive method while maintaining manufacturing efficiency. [Solution] A conductive pattern forming method in which a conductive pattern is formed by a semi-additive method, in which an insulating base material 11 having a seed layer 12 provided on its main surface is prepared, and a resist layer 13 is formed on the seed layer 12. a step of forming conductive pattern openings 13p and dummy pattern openings 13d in the resist layer 13, and plating on the seed layer 12 exposed in the conductive pattern openings 13p and dummy pattern openings 13d by electrolytic plating. a step of forming the resist layer 13, a step of removing the resist layer 13, and a step of removing the exposed seed layer 12e that is not covered with the plating layer of the seed layer 12 by etching. and removing the plated layer (dummy pattern 14d) together with the exposed seed layer 12e. [Selection diagram] Figure 1

Description

The present invention relates to a method for forming a conductive pattern, and more particularly, to a method for forming a conductive pattern on an insulating base material by a semi-additive method.

Conventionally, a semi-additive method is known as one of the methods for forming a conductive pattern on an insulating base material. In the semi-additive method, a substrate is prepared with a thin conductive layer called a seed layer on an insulating base material, and electrolytic plating is applied to the openings of a plating resist formed on top of the substrate to expose the openings in the openings. This is a technology for forming conductive patterns such as wiring, pads, and grounds on the seed layer. In electrolytic plating treatment, plating is deposited from the openings of the plating resist by applying electricity from any position on the substrate through the seed layer. In the semi-additive method, the shape of the opening in the plating resist becomes almost the same as the shape of the conductive pattern, so it is more advantageous in forming fine wiring than the subtractive method.

Note that Patent Document 1 describes a pattern plating method aimed at obtaining a wiring pattern with a uniform film thickness in pattern plating in a pattern plating area where single or multiple block wiring patterns with different pattern densities exist. ing.

Japanese Patent Application Publication No. 2004-263218

By the way, in the semi-additive method, the deposition behavior of plating is not uniform with respect to the surface to which it is deposited, and is greatly influenced by the aperture shape or aperture density of the plating resist. In areas with high opening density, the applied electric field diffuses, making the plating thinner, whereas in areas with low opening density, the electric field concentrates, making the plating thicker. As a result, when the non-uniformity of the opening density is large, the thickness of the conductive pattern becomes non-uniform. As described above, the semi-additive method has a problem in that the plating thickness distribution becomes large due to the influence of the density of the conductive pattern within the product (printed wiring board).

To solve the above problem, the plating thickness distribution can be suppressed by making the aperture density of the plating resist uniform over the deposition surface. However, printed wiring boards of actual products usually have conductive patterns of varying density, and it is difficult to make the density of the conductive patterns uniform.

Therefore, it is conceivable to provide openings for dummy patterns in the plating resist so as to avoid conductive patterns such as wiring, thereby making the opening density uniform over the entire deposition surface.

However, it is not always possible to provide openings for dummy patterns. For example, it is not desirable to arrange a metal dummy pattern in a region where mechanical properties such as bending are imparted. For example, in a flexible printed wiring board 100A shown in FIG. 8A, conductive patterns 120 and 130 are formed on a flexible insulating base material 110. That is, the conductive pattern 120 is formed in the conductive pattern formation area A, and the conductive pattern 130 is formed in the conductive pattern formation area B. The conductive pattern forming area A and the conductive pattern forming area B are connected via a connecting area C. This connection region C may be given mechanical properties such as bending, and in such a case, it is not preferable to arrange a dummy pattern in the connection region C.

Further, it is also not preferable to arrange a dummy pattern in a region where a signal line through which a high-speed signal propagates is arranged. In the flexible printed wiring board 100B shown in FIG. 8(b), the signal line 140 is formed on the insulating base material 110 in the connection area C. The signal line 140 is provided to propagate a high-speed signal (for example, a signal of several GHz or more used in high-speed wireless communication) between the conductive pattern forming area A and the conductive pattern forming area B. In this case, if a dummy pattern is placed in the connection region C, there is a risk that desired transmission characteristics may not be obtained.

The present invention has been made based on the above technical recognition, and an object of the present invention is to provide a conductive pattern forming method that can form a conductive pattern with suppressed plating thickness distribution by a semi-additive method while maintaining manufacturing efficiency. With the goal.

The conductive pattern forming method according to the present invention includes:
A conductive pattern forming method for forming a conductive pattern by a semi-additive method,
preparing an insulating base material provided with a seed layer on its main surface, and forming a resist layer on the seed layer;
forming an opening for a conductive pattern and an opening for a dummy pattern in the resist layer;
forming a plating layer on the seed layer exposed in the conductive pattern opening and the dummy pattern opening by electrolytic plating;
removing the resist layer;
A step of removing by etching an exposed seed layer that is not covered with the plating layer out of the seed layer, the step of removing the plating layer formed in the dummy pattern opening together with the exposed seed layer;
Equipped with

Further, in the conductive pattern forming method,
In the step of forming the conductive pattern opening and the dummy pattern opening, the dummy pattern opening may be formed so that the width of the dummy pattern is narrowed at the bottom thereof.

Further, in the conductive pattern forming method,
The step of forming the conductive pattern opening and the dummy pattern opening includes:
exposing the resist layer so that the size of the dummy pattern opening is equal to or less than the lower limit of the formable opening size based on the material of the resist layer and the performance of the exposure apparatus;
The method may further include the step of developing the exposed resist layer to form the conductive pattern opening and the dummy pattern opening.

Further, in the conductive pattern forming method,
When the resist layer is negative type, the step of forming the conductive pattern opening and the dummy pattern opening includes:
exposing the resist layer so that the amount of exposure around the area where the dummy pattern opening is planned to be formed is greater than the amount of exposure to other areas;
The method may further include the step of developing the exposed resist layer to form the conductive pattern opening and the dummy pattern opening.

Further, in the conductive pattern forming method,
The amount of exposure for the periphery of the area where the dummy pattern opening is to be formed may be 1.5 times or more the amount of exposure for the other area.

Further, in the conductive pattern forming method,
When the resist layer is positive type, the step of forming the conductive pattern opening and the dummy pattern opening includes:
exposing the resist layer so that the amount of exposure to the area where the dummy pattern opening is to be formed is smaller than the amount of exposure to other areas;
The method may further include the step of developing the exposed resist layer to form the conductive pattern opening and the dummy pattern opening.

Further, in the conductive pattern forming method,
The width of the dummy pattern opening is smaller than the width of the conductive pattern opening, and in the step of removing the exposed seed layer by etching, an etchant is used to preferentially etch the interface between the seed layer and the plating layer. You may also use

Further, in the conductive pattern forming method,
The shape of the dummy pattern opening may be circular, regular polygonal, or star-shaped.

Further, in the conductive pattern forming method,
The insulating base material has flexibility, and the dummy pattern opening is formed in a region where the insulating base material is bent, a region where a high-speed signal line is formed, and/or a region where external processing is performed. It is also possible to do so.

Further, in the conductive pattern forming method,
At least one of the above steps may be performed in a roll-to-roll manner.

According to the present invention, it is possible to provide a conductive pattern forming method that can form a conductive pattern with suppressed plating thickness distribution by a semi-additive method while maintaining manufacturing efficiency.

3 is a flowchart for explaining a conductive pattern forming method according to the first embodiment. FIG. 3 is a process cross-sectional view for explaining the conductive pattern forming method according to the first embodiment. 2A is a process cross-sectional view for explaining the conductive pattern forming method according to the first embodiment, following FIG. 2A. FIG. (a), (b), and (c) are all plan views showing examples of shapes of dummy patterns. 3 is a SEM image showing an example of a cross section of a dummy pattern in the middle of etching according to the first embodiment. 7 is a flowchart for explaining a conductive pattern forming method according to a second embodiment. FIG. 7 is a process cross-sectional view for explaining a conductive pattern forming method according to a second embodiment. FIG. 6A is a process cross-sectional view for explaining the conductive pattern forming method according to the second embodiment, following FIG. 6A. 7 is a SEM image showing an example of a cross section of a dummy pattern in the middle of etching according to the second embodiment. Both (a) and (b) are plan views of a flexible printed wiring board for illustrating an example of a case where a dummy pattern cannot be left.

Embodiments according to the present invention will be described below with reference to the drawings. Note that the drawings are schematic and mainly show the characteristic parts of each embodiment, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, etc. are different from the actual drawings.

(First embodiment)
The conductive pattern forming method according to the first embodiment will be described with reference to the flowchart in FIG. 1 and the process cross-sectional views in FIGS. 2A and 2B. This embodiment is a method of forming a conductive pattern on an insulating base material having a conductive layer formation region and a conductive layer formation prohibited region by a semi-additive method.

As shown in FIG. 2A(1), an insulating base material 11 having a seed layer 12 provided on its main surface is prepared (step S11). In this embodiment, the insulating base material 11 is made of a flexible material such as polyimide. Seed layer 12 is, for example, a 2 μm thick copper seed layer.

Note that the material of the insulating base material 11 is not limited to polyimide-based materials, and may be, for example, liquid crystal polymer (LCP) or fluorine-based materials (PFA, PTFE, etc.).

Next, as shown in FIG. 2A (2), a resist layer (plating resist) 13 is formed on the seed layer 12 (step S12). The resist layer 13 is made of a photosensitive material. In this embodiment, the resist layer 13 is negative type.

Next, as shown in FIG. 2A(3), a conductive pattern opening 13p and a dummy pattern opening 13d are formed in the resist layer 13 (step S13). In this step, the dummy pattern opening 13d is formed in a region where the insulating base material 11 is bent in a used state or a mounted state, a region where a high-speed signal line is formed, and/or a region where external processing is performed. The area where the external shape processing is performed is an area where punching and the like are performed, and is an area where metal such as a plating layer is not arranged. The dummy pattern openings 13d are formed so that the density of the openings in the resist layer 13 (the conductive pattern openings 13p and the dummy pattern openings 13d) is approximately uniform. For example, the width of the conductive pattern opening 13p is 20 μm, and the width of the dummy pattern opening 13d is 10 μm.

The process of step S13 is performed by a photolithography process. In this embodiment, a predetermined region of the resist layer 13 is exposed using a direct exposure device, and then the exposed resist layer 13 is developed to form a conductive pattern opening 13p and a dummy pattern opening 13d. In the exposure step, the resist layer 13 is exposed so that the size of the dummy pattern opening 13d is equal to or less than the lower limit of the formable opening size based on the material of the resist layer 13 and the performance of the exposure apparatus. For example, a region of the upper surface of the resist layer 13 other than the region where the dummy pattern opening 13d is to be formed is exposed. The area in which the dummy pattern opening 13d is scheduled to be formed is set to a size that is equal to or smaller than the lower limit of the formable opening size.

When using Asahi Kasei Corporation's dry film resist UFG158 as the material for the resist layer 13 and using Oak Seisakusho's laser direct exposure device DIIMPACT Extra 12 as the exposure device, at an exposure dose of 260 mJ, the lower limit of the practical plating resist aperture is It is 11 μm. In this case, for example, the exposure device is set to expose the resist layer 13 so that the size of the dummy pattern opening 13d becomes a smaller dot shape of φ10 μm. When the dummy pattern opening 13d was actually formed under these conditions, the opening size at the upper end of the dummy pattern opening 13d was 10 μm, but the opening size at the lower end was 5 μm due to hemming.

In addition, when the resist layer 13 is positive type, the area where the dummy pattern opening 13d is planned to be formed is exposed so that the area where the dummy pattern opening 13d is planned to be formed has a size equal to or smaller than the lower limit of the formable opening size.

Further, the photolithography process in step S13 may be performed using an exposure mask. In this case, first, an exposure mask (not shown) is placed over the resist layer 13. The exposure mask has a conductive pattern mask opening corresponding to the conductive pattern opening 13p and a dummy pattern mask opening corresponding to the dummy pattern opening 13d. Placed.

Thereafter, the resist layer 13 is exposed through an exposure mask (exposure step). After the exposure process, the exposure mask is removed and the exposed resist layer 13 is developed to form the conductive pattern opening 13p and the dummy pattern opening 13d.

The size of the conductive pattern opening 13p of the exposure mask (that is, the size of the conductive pattern opening 13p) is a size that is compatible with the resolution performance based on the material of the resist layer 13 and the exposure device (exposure amount) used in the exposure process. do.

On the other hand, the size of the dummy pattern mask opening of the exposure mask (that is, the size of the dummy pattern opening 13d) is set to be less than or equal to the lower limit of the formable opening size based on the material of the resist layer 13 and the exposure apparatus used in the exposure process. Thereby, the dummy pattern opening 13d is formed such that the opening width becomes narrower at the bottom. That is, as shown in FIG. 2A(3), the cross section of the opening of the resist layer 13 has a skirted shape. The exposed area of the seed layer 12 is smaller than the designed dimension.

After developing the resist layer 13 to form the conductive pattern openings 13p and the dummy pattern openings 13d as described above, the seed layer 12 exposed in the conductive pattern openings 13p and the dummy pattern openings 13d is electrolytically plated. A plating layer is formed on top (step S14). That is, plating is deposited inside the conductive pattern opening 13p and the dummy pattern opening 13d. As a result, as shown in FIG. 2B(1), a conductive pattern 14p is formed within the conductive pattern opening 13p, and a dummy pattern 14d is formed within the dummy pattern opening 13d. Since the dummy pattern openings 13d are formed so that the opening density of the resist layer 13 is substantially uniform, the conductive patterns 14p (and the dummy patterns 14d) are formed to have substantially the same thickness.

For example, copper plating is formed inside the conductive pattern opening 13p and the dummy pattern opening 13d by electrolytic copper plating. The thickness of the copper plating layer is, for example, 12 μm. Note that the type of copper plating is not particularly limited.

Although the shape of the dummy pattern 14d is not particularly limited, it is preferably a symmetrical shape. For example, as shown in FIGS. 3A and 3B, the shape of the dummy pattern opening is circular (dot-shaped) or star-shaped. Etching progresses isotropically in the subsequent process (step S16), so if the dummy pattern has a circular or star shape, it becomes easier to remove, and as a result, it can be removed with a small amount of etching, resulting in a fine pattern. This is advantageous for forming wiring.

In addition, the shape of the dummy pattern opening may be a regular polygon or may be a wiring shape as shown in FIG. 3(c).

When the shape of the dummy pattern opening is a star shape or a regular polygon, skirting is likely to occur, so the dummy pattern 14d can be removed with less etching in the subsequent etching process (step S16). Therefore, it is suitable for forming fine wiring.

Next, as shown in FIG. 2B (2), the resist layer 13 is removed (step S15). Since the dummy pattern opening 13d is formed so that the opening width becomes narrower at the bottom, the dummy pattern 14d has an undercut shape. FIG. 4 is a SEM image of a cross section of the actually formed dummy pattern 14d during etching.

Next, as shown in FIGS. 2B (2) and (3), the exposed seed layer 12e that is not covered with the plating layer (conductive pattern 14p and dummy pattern 14d) of the seed layer 12 is removed by etching (step S16). ).

In step S16, the copper seed layer is removed using, for example, a copper seed layer etchant. Although the etching solution is not particularly limited, for example, a sulfuric acid-hydrogen peroxide based etching solution containing FE-880 manufactured by JCU Corporation as an additive is used. Here, considering that the thickness of the seed layer 12 is 2 μm, the etching amount was set to 3 μm. Since the opening size at the lower end of the dummy pattern opening 13d is 5 μm, the dummy pattern 14d is removed from the insulating base material 11 by performing etching of 3 μm.

In this embodiment, since the dummy pattern 14d has an undercut shape, the dummy pattern 14d is removed together with the exposed seed layer 12e in the etching process. Thereby, the conductive pattern 14p with suppressed plating thickness distribution can be formed.

Note that at least one of the above steps may be performed by a roll-to-roll method (continuous conveyance). All of the above steps may be performed in a roll-to-roll manner. Thereby, it is possible to form a conductive pattern with suppressed plating thickness distribution while maintaining manufacturing efficiency of the flexible printed wiring board.

Further, in the exposure process, the dummy pattern opening 13d having a skirted cross section may be formed by exposing only the periphery of the region where the dummy pattern opening 13d is to be formed with a higher exposure amount than usual. That is, the resist layer 13 is exposed such that the amount of exposure to the area around the area where the dummy pattern opening 13d is planned to be formed is greater than the amount of exposure to the area other than the area (hereinafter referred to as "other area"). do. For example, the exposure amount for the area around the area where the dummy pattern opening 13d is to be formed is set to be 1.5 times or more (preferably twice or more) the exposure amount for other areas.

Actually, using a direct exposure device, the area around the area where the dummy pattern opening 13d is planned to be formed is drawn at 500 mJ, and the other area (including the area around the area where the conductive pattern opening 13p is planned to be formed) is drawn at 260 mJ. did. The width of the periphery of the region where the dummy pattern opening 13d is to be formed (for example, the width of the annular region) is not particularly limited, and is, for example, 1 to 5 μm. As a result, it was possible to form a dummy pattern opening 13d having an opening size of 10 μm at the upper end and 3 μm at the lower end. In this way, the skirting shape can be made more noticeable by adjusting the exposure amount.

Note that the exposure amount may be increased by increasing the amount of exposure per time, or may be increased by performing multiple exposures.

In addition, when the resist layer 13 is positive type, the resist layer 13 is exposed so that the amount of exposure to the area where the dummy pattern opening 13d is to be formed is smaller than the amount of exposure to other areas. Thereby, it is possible to form the dummy pattern opening 13d whose opening cross section has a skirted shape.

Further, the above-mentioned adjustment of the exposure amount may be used in combination with a method of setting the size of the dummy pattern opening 13d to be equal to or less than the lower limit of the achievable opening size.

As described above, in the conductive pattern formation according to the first embodiment, the dummy pattern 14d having an undercut shape is formed by forming the dummy pattern opening 13d so that the opening width becomes narrow at the bottom thereof. Thereby, the dummy pattern 14d can be removed in the process of etching away the exposed seed layer 12e. Therefore, a separate step of removing the dummy pattern 14d is not necessary. Therefore, according to this embodiment, a conductive pattern with suppressed plating thickness distribution can be formed by a semi-additive method while maintaining manufacturing efficiency.

(Second embodiment)
The conductive pattern forming method according to the second embodiment will be described with reference to the flowchart in FIG. 5 and the process cross-sectional views in FIGS. 6A and 6B. One of the differences between this embodiment and the first embodiment is that the opening for the dummy pattern does not have an opening with a skirted cross section, but in the etching process of the exposed seed layer. The point is that the dummy pattern is removed together with the exposed seed layer by using an etchant that preferentially etches the interface between the plating layer and the plating layer.

First, an insulating base material 11 having a seed layer 12 provided on its main surface is prepared (step S21), and a resist layer 13 is formed on the seed layer 12 (step S22). Steps S21 and S22 are similar to steps S11 and S12 described in the first embodiment, so a detailed explanation will be omitted.

Next, as shown in FIG. 6A(1), a conductive pattern opening 13p and a dummy pattern opening 13d are formed in the resist layer 13 (step S23). The dummy pattern opening 13d is formed so that its width is smaller than the width of the conductive pattern opening 13p. In this step, the dummy pattern opening 13d is formed in a region where the insulating base material 11 is bent, a region where a high-speed signal line is formed, and/or a region where contour processing is performed. The dummy pattern openings 13d are formed so that the opening density of the resist layer 13 is substantially uniform, as in the first embodiment. However, unlike the case of the first embodiment, the opening cross section of the dummy pattern opening 13d is not a skirted shape but a straight shape like the conductive pattern opening 13p.

Next, as shown in FIG. 6A(2), a plating layer is formed on the seed layer 12 exposed in the conductive pattern opening 13p and the dummy pattern opening 13d by electrolytic plating (step S24). As a result, a conductive pattern 14p is formed within the conductive pattern opening 13p, and a dummy pattern 14d is formed within the dummy pattern opening 13d. Thereafter, as shown in FIG. 6A(3), the resist layer 13 is removed (step S25). Steps S24 and S25 are the same as steps S14 and S15 described in the first embodiment, so detailed explanation will be omitted.

Next, the dummy pattern 14d is removed together with the exposed seed layer 12e using an etchant (seed layer etchant) that preferentially etches the interface between the seed layer 12 and the plating layer (conductive pattern 14p and dummy pattern 14d). (Step S26). In this step, since a seed layer etchant is used, as shown in FIG. 6B, the interface between the seed layer 12 and the plating layers 14p and 14d is preferentially etched, and as a result, undercutting progresses, and as a result, the conductive pattern 14p The dummy pattern 14d, which is smaller than the dummy pattern 14d, is removed together with the exposed seed layer 12e.

As the etchant for the seed layer, for example, SE-300 manufactured by Meltex Corporation can be used. FIG. 7 is a SEM image showing an example of a cross section of the dummy pattern 14d during etching. By setting the etching amount to 3.5 μm, the dummy pattern 14 d and the seed layer 12 thereunder are separated, and as a result, the dummy pattern 14 d is removed from the insulating base material 11 .

As described above, also in the case of the second embodiment, since the dummy pattern 14d is removed in the process of removing the exposed seed layer 12e, the conductive pattern with suppressed plating thickness distribution can be formed without increasing the number of processes. 14p can be formed.

Note that at least one of the above steps may be performed by a roll-to-roll method (continuous conveyance). All of the above steps may be performed in a roll-to-roll manner.

As explained above, in the conductive pattern formation according to the second embodiment, the dummy pattern opening 13d is formed in the same manner as the conductive pattern opening 13p, but in the process of etching away the exposed seed layer 12e, the seed layer An etchant that preferentially etches the interface with the plating layer is used. Thereby, the dummy pattern 14d can be removed together with the exposed seed layer 12e. Therefore, according to this embodiment, a conductive pattern with suppressed plating thickness distribution can be formed by a semi-additive method while maintaining manufacturing efficiency.

Based on the above description, those skilled in the art may be able to imagine additional effects and various modifications of the present invention, but aspects of the present invention are not limited to the individual embodiments described above. . Components from different embodiments may be combined as appropriate. For example, in the etching step (step S16) of the first embodiment, an etchant that preferentially etches the interface between the seed layer 12 and the plating layer may be used.

Various additions, changes, and partial deletions are possible without departing from the conceptual idea and gist of the present invention derived from the content defined in the claims and equivalents thereof.

11 Insulating base material 12 Seed layer 12e Exposed seed layer 13 Resist layer (plating resist)
13d Dummy pattern opening 13p Conductive pattern opening 14p Conductive pattern 14d Dummy patterns 100A, 100B Flexible printed wiring board 110 Flexible insulating base materials 120, 130 Conductive pattern 140 Signal lines A, B Conductive pattern forming area C Connection area

Claims (10)

A conductive pattern forming method for forming a conductive pattern by a semi-additive method,
preparing an insulating base material provided with a seed layer on its main surface, and forming a resist layer on the seed layer;
forming an opening for a conductive pattern and an opening for a dummy pattern in the resist layer;
forming a plating layer on the seed layer exposed in the conductive pattern opening and the dummy pattern opening by electrolytic plating;
removing the resist layer;
A step of removing by etching an exposed seed layer that is not covered with the plating layer out of the seed layer, the step of removing the plating layer formed in the dummy pattern opening together with the exposed seed layer;
A method of providing. 2. The method according to claim 1, wherein in the step of forming the conductive pattern opening and the dummy pattern opening, the dummy pattern opening is formed so that the opening width becomes narrower at the bottom thereof. The step of forming the conductive pattern opening and the dummy pattern opening includes:
exposing the resist layer so that the size of the dummy pattern opening is equal to or less than the lower limit of the formable opening size based on the material of the resist layer and the performance of the exposure apparatus;
3. The method of claim 2, further comprising developing the exposed resist layer to form the conductive pattern opening and the dummy pattern opening. When the resist layer is negative type, the step of forming the conductive pattern opening and the dummy pattern opening includes:
exposing the resist layer so that the amount of exposure around the area where the dummy pattern opening is planned to be formed is greater than the amount of exposure to other areas;
3. The method of claim 2, further comprising developing the exposed resist layer to form the conductive pattern opening and the dummy pattern opening. 5. The method according to claim 4, wherein the amount of exposure to the periphery of the area where the dummy pattern opening is planned to be formed is 1.5 times or more the amount of exposure to the other area. When the resist layer is positive type, the step of forming the conductive pattern opening and the dummy pattern opening includes:
exposing the resist layer so that the amount of exposure to the area where the dummy pattern opening is to be formed is smaller than the amount of exposure to other areas;
3. The method of claim 2, further comprising developing the exposed resist layer to form the conductive pattern opening and the dummy pattern opening. The width of the dummy pattern opening is smaller than the width of the conductive pattern opening, and in the step of removing the exposed seed layer by etching, an etchant is used to preferentially etch the interface between the seed layer and the plating layer. The method according to any one of claims 1 to 6, wherein the method uses: The method according to claim 1, wherein the shape of the dummy pattern opening is circular, regular polygonal, or star-shaped. The insulating base material has flexibility, and the dummy pattern opening is formed in a region where the insulating base material is bent, a region where a high-speed signal line is formed, and/or a region where external processing is performed. 2. The method according to claim 1, wherein: A method in which at least one of the steps of claim 1 is performed in a roll-to-roll manner.

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