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JP2022147359A - Film formation method for silicon oxynitride film and manufacturing method for thin film transistor - Google Patents

Film formation method for silicon oxynitride film and manufacturing method for thin film transistor Download PDF

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JP2022147359A
JP2022147359A JP2021048568A JP2021048568A JP2022147359A JP 2022147359 A JP2022147359 A JP 2022147359A JP 2021048568 A JP2021048568 A JP 2021048568A JP 2021048568 A JP2021048568 A JP 2021048568A JP 2022147359 A JP2022147359 A JP 2022147359A
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film
gas
silicon oxynitride
flow rate
nitrogen gas
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敏彦 酒井
Toshihiko Sakai
靖典 安東
Yasunori Ando
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Nissin Electric Co Ltd
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Priority to PCT/JP2022/007958 priority patent/WO2022202100A1/en
Priority to KR1020237031266A priority patent/KR20230138552A/en
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Abstract

To provide a film formation method for forming a silicon oxynitride film on an oxide semiconductor for improving film formation stability as well as reducing cost.SOLUTION: In a film formation method for a thin film transistor 1 in which a fluorine-containing silicon oxynitride film is formed as a protection layer 8 on a semiconductor layer 5 formed of oxide semiconductor, the fluorine-containing silicon oxynitride film is formed by a plasma CVD method in which SiF4 gas, nitrogen gas, oxygen gas, and hydrogen gas are supplied as process gas. The process gas to be supplied contains the nitrogen gas by 93% or more in flow rate relative to the total flow rate of the nitrogen gas and the oxygen gas.SELECTED DRAWING: Figure 1

Description

本発明は、シリコン酸窒化膜の成膜方法及び当該成膜方法を用いた薄膜トランジスタの製造方法に関するものである。 The present invention relates to a method for forming a silicon oxynitride film and a method for manufacturing a thin film transistor using the film forming method.

近年、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系（ＩＧＺＯ）の酸化物半導体を半導体層（チャネル層）に用いた薄膜トランジスタの開発が活発に行われている。このような薄膜トランジスタとしては、フッ素含有酸化シリコン膜からなる保護層やゲート絶縁層等の絶縁層を酸化物半導体に隣接させるように形成するものが知られている。例えば、特許文献１には、ＳｉＣｌ４ガスとＳｉＦ４ガスと酸素ガスとをプロセスガスとして用いたプラズマＣＶＤ法により、フッ素含有酸化シリコン膜からなる絶縁層を酸化物半導体の上に形成するものが記載されている。 In recent years, thin film transistors using an In--Ga--Zn--O-based (IGZO) oxide semiconductor for a semiconductor layer (channel layer) have been actively developed. As such a thin film transistor, a thin film transistor is known in which a protective layer made of a silicon oxide film containing fluorine and an insulating layer such as a gate insulating layer are formed so as to be adjacent to an oxide semiconductor. For example, in Patent Document 1, an insulating layer made of a fluorine-containing silicon oxide film is formed on an oxide semiconductor by a plasma CVD method using SiCl 4 gas, SiF 4 gas, and oxygen gas as process gases. Have been described.

特開２０１８－１９５６１０号公報JP 2018-195610 A

しかしながら、特許文献１に開示される製造方法は、比較的高価なＳｉＣｌ４ガスをプロセスガスとして用いるため製造コストが高くつくという問題がある。そこでプロセスガスとして高価なＳｉＣｌ４を用いず、ＳｉＦ４ガスと酸素ガスのみを用いて絶縁層を成膜することにより製造コストを低減することも考えられるが、この場合には、酸化物半導体上への酸窒化シリコン膜の成膜が不安定になる（すなわち膜付きが悪い）という問題がある。 However, the manufacturing method disclosed in Patent Document 1 has the problem of high manufacturing costs because it uses relatively expensive SiCl 4 gas as the process gas. Therefore, it is conceivable to reduce the manufacturing cost by forming an insulating layer using only SiF 4 gas and oxygen gas without using expensive SiCl 4 as a process gas. There is a problem that the formation of the silicon oxynitride film on the substrate becomes unstable (that is, the film adhesion is poor).

本発明は上記した課題を一挙に解決すべくなされたものであり、酸化物半導体の上に酸窒化シリコン膜を成膜する成膜方法において、低コスト化を図るとともに、成膜安定性を向上させることを主たる課題とするものである。 The present invention has been made to solve the above-described problems at once, and in a film formation method for forming a silicon oxynitride film on an oxide semiconductor, the cost is reduced and the film formation stability is improved. The main task is to

すなわち本発明の成膜方法は、酸化物半導体の上に酸窒化シリコン膜を成膜する成膜方法であって、前記酸窒化シリコン膜を、ＳｉＦ４ガス、窒素ガス、酸素ガス及び水素ガスをプロセスガスとして供給して行うプラズマＣＶＤ法により成膜し、前記供給するプロセスガスにおいて、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合が９３％以上であることを特徴とする。
このような成膜方法であれば、プラズマＣＶＤ法におけるプロセスガスとして、高価なＳｉＣｌ４を用いることなく比較的な安価なガスを用いるので、材料コストを低減できる。さらに、プロセスガスとして供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合を９３％以上とし、その割合を非常に高くすることにより、絶縁性の良好な酸窒化シリコン膜を酸化物半導体上に安定して成膜することができる。これにより歩留まりが向上し、製造コストをより一層低減させることができる。 That is, the film forming method of the present invention is a film forming method for forming a silicon oxynitride film on an oxide semiconductor. It is characterized in that the film is formed by a plasma CVD method by supplying a process gas, and in the supplied process gas, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas is 93% or more.
With such a film forming method, a relatively inexpensive gas is used as the process gas in the plasma CVD method without using expensive SiCl 4 , so material costs can be reduced. Further, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied as process gases is set to 93% or more. A film can be stably formed on a semiconductor. As a result, the yield can be improved and the manufacturing cost can be further reduced.

本発明の成膜方法により酸化物半導体膜上に酸窒化シリコン膜を安定して成膜できる理由については未だ不明な点もあるが、現在までに得られている知見を基に、本発明者らが考えるメカニズムについて説明する。すなわち、本発明の成膜方法では、プロセスガスとして供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合を９３％以上とすることにより、酸素ガス（結合エネルギー：５．１６ｅＶ）より結合エネルギーが大きく、分解されにくいＳｉ－Ｆ（結合エネルギー：５．７２ｅＶ）の分解が促進され、シリコン原子を起点とした酸窒化シリコン膜の成膜が進みやすくなると考えられる。また、酸素ガスは電気陰性度が高く、フッ素（Ｆ）を含むガスの添加ガスとして作用し、基板の最表面がエッチングされやすくなると考えられる。ＣＶＤプロセスにおいては、成膜およびエッチングの両表面反応が並行して進行するが、窒素ガスの比率を高めることによって相対的にエッチングが進みにくくなるため、絶縁性の良好な酸窒化シリコン膜を酸化物半導体上に安定して成膜することができると考えられる。なお、このメカニズムについての説明は本発明の技術的範囲を制限することを目的とするものではないことに留意されたい。 Although there are still some unclear points as to why a silicon oxynitride film can be stably formed on an oxide semiconductor film by the film forming method of the present invention, the inventors of the present invention have I will explain the mechanism considered by them. That is, in the film forming method of the present invention, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied as process gases is 93% or more, so that oxygen gas (binding energy: 5.16 eV) It is believed that the decomposition of Si—F (bond energy: 5.72 eV), which has a large bond energy and is difficult to decompose, is promoted, and the formation of a silicon oxynitride film starting from silicon atoms is facilitated. In addition, oxygen gas has a high electronegativity and acts as an additive gas for gas containing fluorine (F), which is thought to facilitate etching of the outermost surface of the substrate. In the CVD process, both surface reactions of film formation and etching progress in parallel, but since etching becomes relatively difficult by increasing the ratio of nitrogen gas, the silicon oxynitride film, which has good insulating properties, is oxidized. Therefore, it is thought that the film can be stably formed on the material semiconductor. Note that the description of this mechanism is not intended to limit the technical scope of the present invention.

また前記成膜方法は、前記供給するプロセスガスにおいて、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合が９６％以上であることが好ましい。
このようにすれば、酸窒化シリコン膜の絶縁性能をより一層向上することができる。 Further, in the film forming method, it is preferable that, in the supplied process gas, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas is 96% or more.
By doing so, the insulating performance of the silicon oxynitride film can be further improved.

また前記成膜方法により成膜される酸窒化シリコン膜の具体的態様として、リーク電流密度が１×１０－５Ａ／ｃｍ２以下であり、絶縁破壊電界強度（最大電界強度）が３ＭＶ／ｃｍ以上のものが挙げられる。 Further, as a specific embodiment of the silicon oxynitride film formed by the film forming method, the leakage current density is 1×10 −5 A/cm 2 or less, and the dielectric breakdown electric field strength (maximum electric field strength) is 3 MV/cm. The above are mentioned.

本発明の成膜方法の効果をより顕著に奏する前記酸化物半導体の具体的態様として、Ｉｎ－Ｇａ－Ｚｎ－Ｏにより構成されているものが挙げられる。 As a specific embodiment of the oxide semiconductor that exhibits the effect of the film forming method of the present invention more remarkably, one made of In--Ga--Zn--O can be mentioned.

また本発明の成膜方法の効果をより顕著に奏する態様としては、プラズマＣＶＤ法による前記酸窒化シリコン膜の成膜を３００℃以下で行うものが挙げられる。
このような低温であれば、本発明の成膜方法を、樹脂等の融点が低い基板を用いた薄膜トランジスタの製造に利用することができる。本発明の成膜方法を用いれば、このような低温処理においても良好な絶縁性能を発揮する絶縁層を備える薄膜トランジスタを製造できる。 In addition, as a mode in which the effect of the film forming method of the present invention is exhibited more remarkably, there is a case in which the silicon oxynitride film is formed by plasma CVD at a temperature of 300° C. or lower.
At such a low temperature, the film forming method of the present invention can be used to manufacture a thin film transistor using a substrate having a low melting point such as a resin. By using the film forming method of the present invention, it is possible to manufacture a thin film transistor having an insulating layer exhibiting good insulating performance even in such a low-temperature treatment.

また本発明の薄膜トランジスタの製造方法は、Ｉｎ－Ｇａ－Ｚｎ－Ｏからなる酸化物半導体をチャネル層とする薄膜トランジスタの製造方法であって、スパッタリングにより前記酸化物半導体を形成する半導体層形成工程と、前記した成膜方法により前記酸化物半導体の上に酸窒化シリコン膜から成る絶縁層を成膜する絶縁層形成工程とを有することを特徴とする。
このような薄膜トランジスタの製造方法によれば、前記した本発明の成膜方法と同様の作用効果を奏することができる。 Further, a method for manufacturing a thin film transistor according to the present invention is a method for manufacturing a thin film transistor having an oxide semiconductor made of In--Ga--Zn--O as a channel layer, comprising: a semiconductor layer forming step of forming the oxide semiconductor by sputtering; and an insulating layer forming step of forming an insulating layer made of a silicon oxynitride film on the oxide semiconductor by the film forming method described above.
According to such a method for manufacturing a thin film transistor, it is possible to obtain the same effect as the film forming method of the present invention described above.

このように構成した本発明によれば、酸化物半導体の上に酸窒化シリコン膜を成膜する成膜方法において、低コスト化を図るとともに、成膜安定性を向上させることができる。 According to the present invention configured as described above, in a film forming method for forming a silicon oxynitride film on an oxide semiconductor, cost reduction can be achieved and film forming stability can be improved.

本実施形態のボトムゲート型の薄膜トランジスタの構成を模式的に示す図。FIG. 2 is a diagram schematically showing the configuration of a bottom-gate thin film transistor according to this embodiment; 同実施形態の薄膜トランジスタの製造工程を模式的に示す図。FIG. 4 is a diagram schematically showing a manufacturing process of the thin film transistor of the same embodiment; 同実施形態の薄膜トランジスタのプラズマ処理工程で用いられるプラズマ処理装置の構成を模式的に示す図。FIG. 4 is a diagram schematically showing the configuration of a plasma processing apparatus used in the plasma processing step of the thin film transistor of the same embodiment; 他の実施形態のトップゲート型の薄膜トランジスタの構成を模式的に示す図。FIG. 10 is a diagram schematically showing the configuration of a top-gate thin film transistor according to another embodiment; 実験例における、窒素ガス流量の割合と成膜の安定性との関係を示すグラフ。4 is a graph showing the relationship between the ratio of nitrogen gas flow rate and the stability of film formation in an experimental example. 実験例における、窒素ガス流量の割合と成膜レート及び屈折率との関係を示すグラフ。7 is a graph showing the relationship between the ratio of the nitrogen gas flow rate, the film formation rate, and the refractive index in the experimental example. 実験例における、窒素ガス流量の割合と絶縁性との関係を示すグラフ。4 is a graph showing the relationship between the ratio of nitrogen gas flow rate and insulating properties in an experimental example.

以下に、本発明の一実施形態に係る薄膜トランジスタ及びその製造方法について説明する。 A thin film transistor and a method for manufacturing the same according to an embodiment of the present invention will be described below.

＜１．薄膜トランジスタ＞
本実施形態の薄膜トランジスタ１は所謂ボトムゲート型のＴＦＴであり、酸化物半導体をチャネルに用いたものである。具体的には図１に示すように、基板２と、ゲート電極３と、ゲート絶縁層４と、半導体層５と、ソース電極６及びドレイン電極７と、保護層８とを有しており、基板２側からこの順に形成されている。なおこの実施形態では、保護層８が特許請求の範囲でいう“絶縁層”に相当する。以下、各部について詳述する。 <1. Thin film transistor>
The thin film transistor 1 of this embodiment is a so-called bottom gate type TFT, and uses an oxide semiconductor for the channel. Specifically, as shown in FIG. 1, it has a substrate 2, a gate electrode 3, a gate insulating layer 4, a semiconductor layer 5, a source electrode 6 and a drain electrode 7, and a protective layer 8, They are formed in this order from the substrate 2 side. In this embodiment, the protective layer 8 corresponds to the "insulating layer" in the claims. Each part will be described in detail below.

基板２は光を透過できるような任意の材料から構成されており、例えば、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレナフタレート（ＰＥＮ）、ポリエーテルサルフォン（ＰＥＳ）、アクリル、ポリイミド等のプラスチック（合成樹脂）等の樹脂材料やガラス材料によって構成されてよい。 The substrate 2 is made of any material that allows light to pass through. ) or a glass material.

ゲート電極３は、薄膜トランジスタ１に印加されるゲート電圧によって半導体層５中のキャリア密度を制御するものである。このゲート電極３は、高い導電性を有する任意の材料から構成されており、例えばＳｉ、Ａｌ、Ｍｏ、Ｃｒ、Ｔａ、Ｔｉ、Ｐｔ、Ａｕ、Ａｇ等から選択される１種以上の金属から構成されてよい。また、Ａｌ－Ｎｄ、Ａｇ合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫（ＩＴＯ）、酸化亜鉛インジウム（ＩＺＯ）、Ｉｎ－Ｇａ－Ｚｎ－Ｏ（ＩＧＺＯ）等の金属酸化物の導電性膜から構成されてよい。ゲート電極３は、これらの導電性膜の単層構造又は２層以上の積層構造から構成されてもよい。 The gate electrode 3 controls the carrier density in the semiconductor layer 5 according to the gate voltage applied to the thin film transistor 1 . The gate electrode 3 is made of any material having high conductivity, and is made of one or more metals selected from, for example, Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, and the like. may be In addition, the conductivity of metal oxides such as Al-Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), zinc indium oxide (IZO), In-Ga-Zn-O (IGZO) It may consist of a membrane. The gate electrode 3 may be composed of a single layer structure or a laminated structure of two or more layers of these conductive films.

ゲート絶縁層４は高い絶縁性を有する任意の絶縁材料から構成されており、例えば、ＳｉＯｘ、ＳｉＮｘ、ＳｉＯＮ、Ａｌ２Ｏ３、Ｙ２Ｏ３、Ｔａ２Ｏ５、Ｈｆ２等から選択される１つ以上の酸化物を含む絶縁膜であってよい。ゲート絶縁層４は、これらの導電性膜を単層構造又は２層以上の積層構造としたものであってよい。 The gate insulating layer 4 is made of any insulating material having high insulating properties, and is selected from, for example, SiOx , SiNx , SiON, Al2O3 , Y2O3 , Ta2O5 , Hf2 , and the like. It may be an insulating film that includes one or more oxides that are The gate insulating layer 4 may have a single-layer structure or a laminated structure of two or more layers of these conductive films.

半導体層（チャネル層）５は、ソース電極６とドレイン電極７間を流れる電流を通過させるものである。本実施形態の半導体層５は、酸化物半導体からなるものであり、例えばＩｎ、Ｇａ、Ｚｎ、Ｓｎ、Ａｌ、Ｔｉ等から選択される少なくとも１種の元素の酸化物を主成分として含んでいる。半導体層５を構成する材料の具体例としては、例えば、Ｉｎ－Ｇａ－Ｚｎ－Ｏ（ＩＧＺＯ）、Ｉｎ－Ａｌ－Ｍｇ－Ｏ、Ｉｎ－Ａｌ－Ｚｎ－Ｏ又はＩｎ－Ｈｆ－Ｚｎ－Ｏ等が挙げられる。この半導体層５は非晶質（アモルファス）の酸化物半導体膜により構成されている。本実施形態の半導体層５は単層構造であるが、これに限らず、組成や結晶性が互いに異なる複数の層を重ねて構成した積層構造であってもよい。 The semiconductor layer (channel layer) 5 passes the current flowing between the source electrode 6 and the drain electrode 7 . The semiconductor layer 5 of the present embodiment is made of an oxide semiconductor, and contains, as a main component, an oxide of at least one element selected from, for example, In, Ga, Zn, Sn, Al, Ti, and the like. . Specific examples of materials constituting the semiconductor layer 5 include In--Ga--Zn--O (IGZO), In--Al--Mg--O, In--Al--Zn--O, In--Hf--Zn--O, etc. is mentioned. The semiconductor layer 5 is composed of an amorphous oxide semiconductor film. The semiconductor layer 5 of the present embodiment has a single-layer structure, but is not limited to this, and may have a laminated structure in which a plurality of layers having different compositions and crystallinities are laminated.

ソース電極６及びドレイン電極７は、半導体層５の表面を部分的に覆うように、互いに離間して形成されている。ソース電極６及びドレイン電極７は、ゲート電極３と同様に、電極として機能するように高い導電性を有する材料から構成されている。ソース電極６及びドレイン電極７は、単一の材料からなる単層構造でよく、互いに異なる材料からなる複数の層を重ねた積層構造であってもよい。 The source electrode 6 and the drain electrode 7 are formed apart from each other so as to partially cover the surface of the semiconductor layer 5 . Like the gate electrode 3, the source electrode 6 and the drain electrode 7 are made of a highly conductive material so as to function as electrodes. The source electrode 6 and the drain electrode 7 may have a single-layer structure made of a single material, or may have a laminated structure in which a plurality of layers made of different materials are laminated.

保護層（パッシベーション層）８は、ソース電極６とドレイン電極７の間から露出する半導体層５の表面（チャネル領域）を覆って保護するものであり、絶縁性の材料により構成されたものである。保護層８は、少なくとも半導体層５の表面に接触して設けられている。本実施形態の保護層８は、ソース電極６及びドレイン電極７の表面を更に覆うように設けられている。 The protective layer (passivation layer) 8 covers and protects the surface (channel region) of the semiconductor layer 5 exposed between the source electrode 6 and the drain electrode 7, and is made of an insulating material. . The protective layer 8 is provided in contact with at least the surface of the semiconductor layer 5 . The protective layer 8 of this embodiment is provided so as to further cover the surfaces of the source electrode 6 and the drain electrode 7 .

具体的にこの保護層８は、フッ素含有酸窒化シリコン膜（ＳｉＯＮ：Ｆ）により構成されている。このフッ素含有酸窒化シリコン膜は、リーク電流密度が１×１０－５Ａ／ｃｍ２以下であり、絶縁破壊電界強度が３ＭＶ／ｃｍ以上のものであることが好ましく、リーク電流密度が１×１０－７Ａ／ｃｍ２以下であり、絶縁破壊電界強度が８ＭＶ／ｃｍ以上のものであることがより好ましい。 Specifically, the protective layer 8 is composed of a fluorine-containing silicon oxynitride film (SiON:F). This fluorine-containing silicon oxynitride film preferably has a leakage current density of 1×10 −5 A/cm 2 or less and a dielectric breakdown field strength of 3 MV/cm or more. −7 A/cm 2 or less, and a dielectric breakdown field strength of 8 MV/cm or more is more preferable.

なお保護層８の上には、例えばフッ素含有シリコン酸化膜（ＳｉＮ：Ｆ）、フッ素含有シリコン酸化膜（ＳｉＯ：Ｆ）、シリコン窒化膜（ＳｉＮｘ）、シリコン酸化膜（ＳｉＯｘ）等からなる第２の保護層が、必要に応じて更に設けられてもよい。 On the protective layer 8, a second film made of, for example, a fluorine-containing silicon oxide film (SiN:F), a fluorine-containing silicon oxide film (SiO:F), a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like is formed. A protective layer of may be further provided as required.

＜２．薄膜トランジスタの製造方法＞
次に、上述した構造の薄膜トランジスタ１の製造方法を、図２を参照して説明する。
本実施形態の薄膜トランジスタ１の製造方法は、ゲート電極形成工程、ゲート絶縁層形成工程、半導体層形成工程、ソース・ドレイン電極形成工程、プラズマ処理工程及び保護層形成工程を含む。なおこの実施形態では、保護層形成工程が特許請求の範囲でいう“絶縁層形成工程”に相当する。以下、各工程について説明する。 <2. Method for manufacturing a thin film transistor>
Next, a method for manufacturing the thin film transistor 1 having the structure described above will be described with reference to FIG.
The method of manufacturing the thin film transistor 1 of this embodiment includes a gate electrode forming process, a gate insulating layer forming process, a semiconductor layer forming process, a source/drain electrode forming process, a plasma treatment process, and a protective layer forming process. In this embodiment, the protective layer forming step corresponds to the "insulating layer forming step" in the claims. Each step will be described below.

（１）ゲート電極形成工程
まず図２の（ａ）に示すように、例えばＰＥＴ等の樹脂材料からなる基板２を準備し、基板２の表面にゲート電極３を形成する。ゲート電極３の形成方法は特に制限されず、例えば真空蒸着法等の既知の方法により形成してよい。 (1) Gate Electrode Forming Step First, as shown in FIG. The method of forming the gate electrode 3 is not particularly limited, and may be formed by a known method such as a vacuum deposition method.

（２）ゲート絶縁層形成工程
次に、図２の（ｂ）に示すように、基板２及びゲート電極３の表面を覆うようにゲート絶縁層４を形成する。ゲート絶縁層４の形成方法は特に限定されず、既知の方法により形成してよい。 (2) Gate Insulating Layer Forming Step Next, as shown in FIG. 2B, the gate insulating layer 4 is formed to cover the surfaces of the substrate 2 and the gate electrode 3 . A method for forming the gate insulating layer 4 is not particularly limited, and it may be formed by a known method.

（３）半導体層形成工程
次に、図２の（ｃ）に示すように、ゲート絶縁層４上に半導体層５を形成する。この半導体層５は、既知の方法により形成してよい。例えば、誘導結合型のプラズマを用いて、ＩｎＧａＺｎＯ等の導電性酸化物焼結体をターゲットとしてスパッタリングすることにより半導体層５を形成してよい。なおこれに限らず、他の方法により酸化物半導体からなる半導体層５を形成してもよい。 (3) Semiconductor Layer Forming Step Next, as shown in FIG. 2C, the semiconductor layer 5 is formed on the gate insulating layer 4 . This semiconductor layer 5 may be formed by a known method. For example, the semiconductor layer 5 may be formed by sputtering a conductive oxide sintered body such as InGaZnO as a target using inductively coupled plasma. In addition, the semiconductor layer 5 made of an oxide semiconductor may be formed by another method without being limited to this.

（４）ソース・ドレイン電極形成工程
次に、図２の（ｄ）に示すように、半導体層５上にソース電極６及びドレイン電極７を形成する。ソース電極６およびドレイン電極７の形成は、例えば、ＲＦマグネトロンスパッタリング等を用いた既知の方法により形成することができる。ソース電極６及びドレイン電極７は、半導体層５の表面上で互いに離間し、半導体層５の表面の一部を露出させるように形成される。 (4) Source/Drain Electrode Forming Step Next, as shown in FIG. 2D, the source electrode 6 and the drain electrode 7 are formed on the semiconductor layer 5 . The source electrode 6 and the drain electrode 7 can be formed by a known method using, for example, RF magnetron sputtering. The source electrode 6 and the drain electrode 7 are formed on the surface of the semiconductor layer 5 so as to be spaced apart from each other and partially expose the surface of the semiconductor layer 5 .

（５）プラズマ処理工程
ここで、半導体層５の表面に保護層８を形成する前に、半導体層５の表面に対してプラズマ処理（成膜前処理）を行ってもよい。具体的にこのプラズマ処理は、図３に例示するような誘導結合型のプラズマ処理装置１００を用いて行ってよい。具体的にプラズマ処理装置１００は、真空排気され且つプロセスガスＧが導入される処理室１０が内側に形成された真空容器２０と、処理室１０の外部に設けられたアンテナ３０と、アンテナ３０に高周波（１３．５６ＭＨｚ）を印加する高周波電源４０とを備えている。高周波電源４０からアンテナ３０に高周波を印加すると、アンテナ３０から発生した高周波磁場が処理室１０内に形成されることで誘導電界が発生し、これにより誘導結合型のプラズマＰが生成される。 (5) Plasma Treatment Step Here, before forming the protective layer 8 on the surface of the semiconductor layer 5, the surface of the semiconductor layer 5 may be subjected to plasma treatment (pre-film formation treatment). Specifically, this plasma processing may be performed using an inductively coupled plasma processing apparatus 100 as illustrated in FIG. Specifically, the plasma processing apparatus 100 includes a vacuum vessel 20 inside which is formed a processing chamber 10 which is evacuated and into which a process gas G is introduced; an antenna 30 provided outside the processing chamber 10; and a high frequency power supply 40 that applies a high frequency (13.56 MHz). When a high frequency is applied from the high frequency power supply 40 to the antenna 30, a high frequency magnetic field generated from the antenna 30 is formed in the processing chamber 10 to generate an induced electric field, thereby generating an inductively coupled plasma P.

具体的にこの工程では、少なくとも窒素ガスと酸素ガスとをプロセスガスとして処理室１０内に供給し、この状態でアンテナ３０に高周波を印加して誘導結合型のプラズマを生じさせる。ここで供給するプロセスガスは、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合（Ｎ２／Ｎ２＋Ｏ２）が、７０％以上であることが好ましく、８０％以上であることがより好ましく、９０％以上であることがさらに好ましい。窒素ガスの流量割合が大きいほど、後で形成する保護層８中の固定電荷密度を小さくできるので好ましい。またこの工程は、基板温度を１５０℃以上３００℃以下の低温で行うことが好ましい。プラズマ処理を行う処理時間は特に限定されないが、保護層８中の固定電荷密度をより小さくする観点から１５秒以上４５秒以下が好ましい。その他、ＲＦパワー、成膜時圧力、プロセスガスの絶対量等は適宜設定されてよい。なお、処理室１０内に供給される各ガスの流量は、ガス流路に設けたマスフローコントローラにより制御される。すなわち、ここでいう「流量」とは、マスフローコント―ラ等の流量制御機器における設定値を意味する（他の工程でも同じである。）。 Specifically, in this step, at least nitrogen gas and oxygen gas are supplied as process gases into the processing chamber 10, and in this state, a high frequency is applied to the antenna 30 to generate inductively coupled plasma. In the process gas to be supplied here, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas (N 2 /N 2 +O 2 ) is preferably 70% or more, more preferably 80% or more. More preferably, it is 90% or more. The higher the nitrogen gas flow rate, the lower the fixed charge density in the protective layer 8 to be formed later, which is preferable. Moreover, this step is preferably performed at a substrate temperature as low as 150° C. or higher and 300° C. or lower. The treatment time for the plasma treatment is not particularly limited, but from the viewpoint of further reducing the fixed charge density in the protective layer 8, it is preferably 15 seconds or more and 45 seconds or less. In addition, the RF power, the film-forming pressure, the absolute amount of the process gas, and the like may be appropriately set. The flow rate of each gas supplied into the processing chamber 10 is controlled by a mass flow controller provided in the gas flow path. That is, the "flow rate" referred to here means a set value in a flow control device such as a mass flow controller (the same applies to other processes).

（６）保護層形成工程
プラズマ処理工程の後、図２の（ｅ）に示すように、ソース電極６及びドレイン電極７の間から露出する半導体層５の表面を覆うように保護層８を形成する。この保護層８の形成は、例えば前記したプラズマ処理装置（以下、プラズマＣＶＤ装置ともいう）１００を用いてプラズマＣＶＤ法（化学気相成長法）を用いて行われる。ここでは、プラズマ処理工程においてプラズマＣＶＤ装置１００の処理室１０内に生成したプラズマを維持した状態で保護層形成工程に移行するようにしている。 (6) Protective Layer Forming Step After the plasma treatment step, a protective layer 8 is formed to cover the surface of the semiconductor layer 5 exposed between the source electrode 6 and the drain electrode 7, as shown in FIG. do. The protective layer 8 is formed by plasma CVD (chemical vapor deposition) using the above-described plasma processing apparatus (hereinafter also referred to as plasma CVD apparatus) 100, for example. Here, the protective layer forming step is performed while maintaining the plasma generated in the processing chamber 10 of the plasma CVD apparatus 100 in the plasma processing step.

具体的にこの保護層形成工程では、プロセスガスとして、ＳｉＦ４（四フッ化シリコン）ガス、窒素ガス、酸素ガス及び水素ガスを処理室１０内に供給し、この状態でアンテナ３０に高周波を印加して誘導結合型のプラズマを生じさせる。ここで本実施形態では、供給するプロセスガスにおいて、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合（Ｎ２／Ｎ２＋Ｏ２）が９３％以上であり、９６％以上であることが好ましい。また当該割合の上限は特に限らないが１００％であることが好ましい。なお、流量割合が１００％である場合、処理室１０内に意図的に供給する酸素ガスの流量は０ｃｃｍとなるが、この場合でも、プロセスガス中には酸素ガスが不可避的に含まれており、そのためフッ素含有シリコン酸窒化膜を成膜することができる。またこの工程は、基板温度を１５０℃以上３００℃以下の低温で行うことが好ましい。その他、ＲＦパワー、成膜時圧力、プロセスガスの絶対量等は適宜設定されてよい。 Specifically, in this protective layer forming step, SiF 4 (silicon tetrafluoride) gas, nitrogen gas, oxygen gas, and hydrogen gas are supplied as process gases into the processing chamber 10, and a high frequency is applied to the antenna 30 in this state. to generate an inductively coupled plasma. Here, in the present embodiment, in the process gas to be supplied, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas (N 2 /N 2 +O 2 ) is 93% or more, and 96% or more. is preferred. Although the upper limit of the ratio is not particularly limited, it is preferably 100%. When the flow rate ratio is 100%, the flow rate of the oxygen gas intentionally supplied into the processing chamber 10 is 0 ccm, but even in this case, the process gas inevitably contains oxygen gas. Therefore, a fluorine-containing silicon oxynitride film can be formed. Moreover, this step is preferably performed at a substrate temperature as low as 150° C. or higher and 300° C. or lower. In addition, the RF power, the film-forming pressure, the absolute amount of the process gas, and the like may be appropriately set.

必要に応じて、保護層８の上に、例えばフッ素含有シリコン酸化膜（ＳｉＮ：Ｆ）、フッ素含有シリコン酸化膜（ＳｉＯ：Ｆ）、シリコン窒化膜（ＳｉＮｘ）、シリコン酸化膜（ＳｉＯｘ）等からなる第２の保護層を成膜してもよい。この保護層の成膜は、保護層８と同様に、プラズマＣＶＤ装置１００を用いて行うことができる。 If necessary, on the protective layer 8, for example, a fluorine-containing silicon oxide film (SiN:F), a fluorine-containing silicon oxide film (SiO:F), a silicon nitride film (SiNx), a silicon oxide film (SiOx), etc. A second protective layer may be deposited. Film formation of this protective layer can be performed using the plasma CVD apparatus 100 similarly to the protective layer 8 .

（７）熱処理工程
必要に応じて酸素を含む大気圧下の雰囲気中で熱処理を行ってもよい。熱処理における炉内温度は特に限定されず、例えば１５０℃以上３００℃以下である。また熱処理時間は特に限定されず、例えば１時間以上３時間以下である。 (7) Heat Treatment Step If necessary, heat treatment may be performed in an atmosphere containing oxygen under atmospheric pressure. The furnace temperature in the heat treatment is not particularly limited, and is, for example, 150° C. or higher and 300° C. or lower. The heat treatment time is not particularly limited, and is, for example, 1 hour or more and 3 hours or less.

以上により、本実施形態の薄膜トランジスタ１を得ることができる。 As described above, the thin film transistor 1 of the present embodiment can be obtained.

＜３．本実施形態の効果＞
このように構成した本実施形態の薄膜トランジスタ１の製造方法であれば、保護層形成工程において、プロセスガスとして、高価なＳｉＣｌ４を用いることなく比較的な安価なガスを用いてプラズマＣＶＤ法により保護層８を形成するので、材料コストを低減できる。そしてさらに、プロセスガスとして供給する窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合を９３％以上とし、その割合を非常に高くしているので、絶縁性の良好な酸窒化シリコン膜から成る保護層８を酸化物半導体から成る半導体層５上に安定して成膜することができる。これにより歩留まりが向上し、製造コストをより一層低減させることができる。 <3. Effect of the present embodiment>
According to the manufacturing method of the thin film transistor 1 of the present embodiment configured as described above, in the protective layer forming step, the plasma CVD method is used to protect the thin film transistor 1 by using a relatively inexpensive gas as a process gas without using expensive SiCl 4 . Forming the layer 8 reduces material costs. Further, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas supplied as process gases is set to 93% or more. The protective layer 8 composed of an oxide semiconductor can be stably formed on the semiconductor layer 5 composed of an oxide semiconductor. As a result, the yield can be improved and the manufacturing cost can be further reduced.

＜４．その他の変形実施形態＞
なお、本発明は前記実施形態に限られるものではない。 <4. Other modified embodiments>
It should be noted that the present invention is not limited to the above embodiments.

前記実施形態の薄膜トランジスタ１は、ゲート電極３、ゲート絶縁層４及び半導体層５が基板２側から順に積層されたボトムゲート型のものであったがこれに限らない。他の実施形態では、図４に示すように、薄膜トランジスタ１は、半導体層５、ゲート絶縁層４、及びゲート電極３が基板２側から順に積層されたトップゲート型のものであってもよい。この場合には、半導体層５上に積層されるゲート絶縁層４が特許請求の範囲でいう“絶縁層”に相当する。この場合、ゲート絶縁層４はフッ素含有酸窒化シリコン膜（ＳｉＯＮ：Ｆ）により構成されており、リーク電流密度が１×１０－５Ａ／ｃｍ２以下であり、絶縁破壊電界強度が３ＭＶ／ｃｍ以上のものであることが好ましく、リーク電流密度が１×１０－７Ａ／ｃｍ２以下であり、絶縁破壊電界強度が８ＭＶ／ｃｍ以上のものであることがより好ましい。 The thin film transistor 1 of the above-described embodiment is a bottom gate type in which the gate electrode 3, the gate insulating layer 4 and the semiconductor layer 5 are stacked in order from the substrate 2 side, but the present invention is not limited to this. In another embodiment, as shown in FIG. 4, the thin film transistor 1 may be of a top gate type in which a semiconductor layer 5, a gate insulating layer 4, and a gate electrode 3 are stacked in order from the substrate 2 side. In this case, the gate insulating layer 4 laminated on the semiconductor layer 5 corresponds to the "insulating layer" in the claims. In this case, the gate insulating layer 4 is composed of a fluorine-containing silicon oxynitride film (SiON:F), has a leakage current density of 1×10 −5 A/cm 2 or less, and has a dielectric breakdown electric field strength of 3 MV/cm 2 . More preferably, it has a leakage current density of 1×10 −7 A/cm 2 or less and a dielectric breakdown field strength of 8 MV/cm or more.

また薄膜トランジスタ１がトップゲート型である場合、その製造方法は、前記した半導体層形成工程、ソース・ドレイン電極形成工程、プラズマ処理工程、ゲート絶縁層形成工程及びゲート電極形成工程をこの順に行うことで行われる。この場合には、ゲート絶縁層形成工程が特許請求の範囲でいう“絶縁層形成工程”に相当する。
そのためこの実施形態では、ゲート絶縁層形成工程は、ＳｉＦ４（四フッ化ケイ素）ガス、窒素ガス、酸素ガス及び水素ガスをプロセスガスとして用いて、プラズマＣＶＤ法により行われる。具体的な方法は、前記した保護層形成工程と同様である。 When the thin-film transistor 1 is of the top-gate type, the manufacturing method is to perform the semiconductor layer forming step, the source/drain electrode forming step, the plasma processing step, the gate insulating layer forming step, and the gate electrode forming step in this order. done. In this case, the gate insulating layer forming step corresponds to the "insulating layer forming step" in the claims.
Therefore, in this embodiment, the gate insulating layer forming step is performed by plasma CVD using SiF 4 (silicon tetrafluoride) gas, nitrogen gas, oxygen gas and hydrogen gas as process gases. A specific method is the same as the protective layer forming step described above.

前記実施形態では、酸化物半導体層５を形成した後、この上に絶縁層（保護層８）を形成する前に、酸化物半導体層５の表面にプラズマ処理を施していたがこれに限らない。他の実施形態では、酸化物半導体層５の表面にプラズマ処理を行うことなく、その表面に絶縁層（保護層８）を形成してもよい。 In the above embodiment, the surface of the oxide semiconductor layer 5 is plasma-treated after forming the oxide semiconductor layer 5 and before forming the insulating layer (protective layer 8) thereon, but the present invention is not limited to this. . In another embodiment, an insulating layer (protective layer 8) may be formed on the surface of the oxide semiconductor layer 5 without performing plasma treatment on the surface.

前記実施形態では、半導体層５は酸化物半導体からなるものであったが、これに限らない。他の実施形態は、半導体層５は、例えばアモルファスＳｉや多結晶Ｓｉ等、任意の半導体材料により構成されてもよい。 Although the semiconductor layer 5 is made of an oxide semiconductor in the above embodiment, it is not limited to this. In other embodiments, the semiconductor layer 5 may consist of any semiconductor material, for example amorphous Si or polycrystalline Si.

その他、本発明は前記実施形態に限られず、その趣旨を逸脱しない範囲で種々の変形が可能であるのは言うまでもない。 In addition, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications are possible without departing from the spirit of the present invention.

以下、実施例を挙げて本発明をより具体的に説明する。本発明は以下の実施例によって制限を受けるものではなく、前記、後記の趣旨に適合し得る範囲で適当に変更を加えて実施することが勿論可能であり、それらはいずれも本発明の技術的範囲に包含される。 EXAMPLES Hereinafter, the present invention will be described more specifically with reference to Examples. The present invention is not limited by the following examples, and it is of course possible to carry out the present invention by making appropriate changes within the scope that can be adapted to the spirit of the above and the following. Included in scope.

＜実験例１＞プロセスガスにおける窒素ガス流量の割合と成膜の安定性との関係性
プラズマＣＶＤ法におけるプロセスガス中の窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合（Ｎ２／（Ｎ２＋Ｏ２）とも記載する）と、酸化物半導体上への成膜の安定性との関係を評価した。 <Experimental Example 1 > Relationship between nitrogen gas flow rate ratio in process gas and film formation stability The relationship between (also referred to as (N 2 +O 2 )) and the stability of film formation over an oxide semiconductor was evaluated.

具体的にこの実施例では、前記したプラズマＣＶＤ装置を用いて、供給するプロセスガスにおけるＮ２／（Ｎ２＋Ｏ２）を変化させて（０％から１００％まで）、シリコン基板とＩＧＺＯ膜のそれぞれの表面にフッ素含有酸窒化シリコン膜を成膜した。そして、Ｓｉ基板上の膜厚に対するＩＧＺＯ膜上の膜厚の比率（以下、膜厚比ともいう）を測定した。 Specifically, in this embodiment, using the plasma CVD apparatus described above, the ratio of N 2 /(N 2 +O 2 ) in the process gas to be supplied is changed (from 0% to 100%), and the silicon substrate and the IGZO film are separated. A fluorine-containing silicon oxynitride film was formed on each surface. Then, the ratio of the film thickness on the IGZO film to the film thickness on the Si substrate (hereinafter also referred to as film thickness ratio) was measured.

具体的に各フッ素含有酸窒化シリコン膜の成膜は、プラズマＣＶＤ装置の処理室内に、ＳｉＦ４、Ｎ２、Ｏ２及びＨ２をプロセスガスとして供給し、ＲＦパワー：２０ｋＷ（０．４８Ｗ／ｃｍ２）、成膜時の圧力：１０Ｐａ、設定温度：２００℃の条件で行った。ここで、供給する各ガス流量は、ＳｉＦ４：５００ｓｃｃｍ、Ｈ２：９００ｓｃｃｍ、Ｎ２＋Ｏ２：３０００ｓｃｃｍ、となるようにした。そして成膜後のフッ素含有酸窒化シリコン膜の膜厚は、分光エリプソメーター（大塚電子製、ＦＥ－５０００Ｓ）により測定した。測定結果を図５に示す。 Specifically, each fluorine-containing silicon oxynitride film was formed by supplying SiF 4 , N 2 , O 2 and H 2 as process gases into the processing chamber of a plasma CVD apparatus, RF power: 20 kW (0.48 W/ cm 2 ), pressure during film formation: 10 Pa, and set temperature: 200°C. Here, the flow rates of the supplied gases were set to SiF 4 : 500 sccm, H 2 : 900 sccm, and N 2 +O 2 : 3000 sccm. The film thickness of the fluorine-containing silicon oxynitride film after film formation was measured with a spectroscopic ellipsometer (FE-5000S, manufactured by Otsuka Electronics Co., Ltd.). The measurement results are shown in FIG.

図５から分かるように、プロセスガス中のＮ２／（Ｎ２＋Ｏ２）を０％～５０％の範囲で行ったものは、膜厚比が０．９未満、あるいは１．１超となり、成膜が不安定であった。
一方で、プロセスガス中のＮ２／（Ｎ２＋Ｏ２）を９３％以上の範囲で行ったもの（９３．３％、９６．７％、１００％）は、膜厚比が０．９以上１．１以下（すなわち、膜厚の差が１０％以内）であり、ＩＧＺＯ膜上に安定してフッ素含有酸窒化シリコン膜を成膜できた。 As can be seen from FIG. 5, when the N 2 /(N 2 +O 2 ) in the process gas is in the range of 0% to 50%, the film thickness ratio is less than 0.9 or more than 1.1. Film formation was unstable.
On the other hand, when N 2 /(N 2 +O 2 ) in the process gas is in the range of 93% or more (93.3%, 96.7%, 100%), the film thickness ratio is 0.9 or more. It was 1.1 or less (that is, the film thickness difference was within 10%), and a fluorine-containing silicon oxynitride film could be stably formed on the IGZO film.

＜実験例２＞プロセスガスにおける窒素ガス流量の割合と成膜レート及び屈折率との関係性
次に、プラズマＣＶＤ法におけるプロセスガス中の窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合と、酸化物半導体上へのフッ素含有酸窒化シリコン膜の成膜レート及び屈折率との関係を評価した。 <Experimental Example 2> Relationship between nitrogen gas flow rate ratio in process gas, film formation rate, and refractive index Next, the ratio of the nitrogen gas flow rate to the total flow rate of nitrogen gas and oxygen gas in the process gas in the plasma CVD method. , the deposition rate and the refractive index of the fluorine-containing silicon oxynitride film over the oxide semiconductor.

具体的には、実験例１においてプロセスガス中のＮ２／（Ｎ２＋Ｏ２）を９３％以上（具体的には、９３．３％、９６．７％、１００％）にしてＩＧＺＯ膜上に成膜を行った３つのサンプルについて、その成膜レートと屈折率とを測定した。具体的に、各サンプルの成膜レートは、分光エリプソメーターにより測定した膜厚を成膜時間で除することで算出した。各サンプルの屈折率も、上記分光エリプソメーターにより測定した。その結果を図６に示す。 Specifically, in Experimental Example 1, the N 2 /(N 2 +O 2 ) in the process gas was set to 93% or more (specifically, 93.3%, 96.7%, 100%) and on the IGZO film The film formation rate and the refractive index were measured for the three samples on which the film was formed. Specifically, the film formation rate of each sample was calculated by dividing the film thickness measured by the spectroscopic ellipsometer by the film formation time. The refractive index of each sample was also measured by the above spectroscopic ellipsometer. The results are shown in FIG.

図６に示すように、プロセスガス中のＮ２／（Ｎ２＋Ｏ２）を９３％以上としても、成膜レートが２５ｎｍ／ｍｉｎ以上であり良好であることが分かった。また、プロセスガス中のＮ２／（Ｎ２＋Ｏ２）を９３％以上の範囲で、窒素ガス流量の増加に伴い屈折率が顕著に増加しており、窒化が急激に進むことが分かった。 As shown in FIG. 6, it was found that even when the N 2 /(N 2 +O 2 ) in the process gas was 93% or more, the film formation rate was 25 nm/min or more, which was favorable. In addition, it was found that the refractive index remarkably increased with an increase in the nitrogen gas flow rate when the N 2 /(N 2 +O 2 ) in the process gas was in the range of 93% or more, and the nitriding progressed rapidly.

＜実験例３＞プロセスガスにおける窒素ガス流量の割合と絶縁性との関係性
次に、プラズマＣＶＤ法におけるプロセスガス中の窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合と、酸化物半導体膜上に成膜したフッ素含有酸窒化シリコン膜の絶縁性との関係を評価した。 <Experimental Example 3> Relationship between nitrogen gas flow rate ratio in process gas and insulation properties The relationship with the insulating property of the fluorine-containing silicon oxynitride film formed on the semiconductor film was evaluated.

具体的にこの実施例では、前記したプラズマＣＶＤ装置を用いてＳｉ基板上にフッ素含有酸窒化シリコン膜を成膜し、このフッ素含有酸窒化シリコン膜上にアルミニウム電極を形成してサンプルを作成した。ここで、フッ素含有酸窒化シリコン膜を成膜する際に、供給するプロセスガスにおけるＮ２／（Ｎ２＋Ｏ２）を変化させた３種類（９３．３％、９６．７％、１００％）のサンプルを作成した。また各種類のサンプルは、図７に示すように、ＲＦパワー、成膜時の圧力及び温度、プロセスガス流量等の条件を変えて、合計６つのサンプルを作成した。そして、抵抗加熱真空蒸着法により、成膜面上に約1ｍｍφのＡｌ含有電極を形成し、デジタル超高抵抗／微小電流計（アドバンテスト製、Ｒ８３４０Ａ）によって、膜厚方向における電流電圧測定を行い、Ｉ－Ｖ曲線を得た。そのＩ－Ｖ曲線から、各サンプルのリーク電流密度（印加電界３ＭＶ／ｃｍにおける電流密度）と絶縁破壊電界（リーク電流密度が１×１０－５Ａ／ｃｍ２となる電界強度）を求めた。その結果を図７に示す。 Specifically, in this example, a fluorine-containing silicon oxynitride film was formed on a Si substrate using the plasma CVD apparatus described above, and an aluminum electrode was formed on this fluorine-containing silicon oxynitride film to prepare a sample. . Here, three types (93.3%, 96.7%, 100%) in which N 2 /(N 2 +O 2 ) in the process gas supplied when forming the fluorine-containing silicon oxynitride film are changed. created a sample of As for each type of sample, as shown in FIG. 7, a total of six samples were prepared by changing conditions such as RF power, pressure and temperature during film formation, and process gas flow rate. Then, an Al-containing electrode with a diameter of about 1 mm was formed on the film formation surface by a resistance heating vacuum deposition method, and current and voltage were measured in the film thickness direction with a digital ultra-high resistance/micro-ammeter (manufactured by Advantest, R8340A). An IV curve was obtained. From the IV curve, the leakage current density (current density at an applied electric field of 3 MV/cm) and dielectric breakdown electric field (electric field strength at which the leakage current density is 1×10 −5 A/cm 2 ) of each sample were obtained. The results are shown in FIG.

図７に示すように、プロセスガス中のＮ２／（Ｎ２＋Ｏ２）が９３％以上であるフッ素含有酸窒化シリコン膜を有するサンプルはいずれも、絶縁破壊電界が３ＭＶ／ｃｍ以上、かつリーク電流密度が１×１０－５Ａ／ｃｍ２以下であり、優れた絶縁性が得られることを確認した。特にプロセスガス中のＮ２／（Ｎ２＋Ｏ２）が９６％以上であるフッ素含有酸窒化シリコン膜を有するサンプルは、絶縁破壊電界が８ＭＶ／ｃｍ以上、かつリーク電流密度が１×１０－７Ａ／ｃｍ２以下であり、より優れた絶縁性が得られることを確認した。 As shown in FIG. 7, all samples having a fluorine-containing silicon oxynitride film in which the N 2 /(N 2 +O 2 ) in the process gas is 93% or more have a breakdown electric field of 3 MV/cm or more and a leakage current of 3 MV/cm or more. It was confirmed that the current density was 1×10 −5 A/cm 2 or less and excellent insulation was obtained. In particular, a sample having a fluorine-containing silicon oxynitride film in which N 2 /(N 2 +O 2 ) in the process gas is 96% or more has a breakdown electric field of 8 MV/cm or more and a leakage current density of 1×10 −7 . A/cm 2 or less, and it was confirmed that superior insulation can be obtained.

１ ・・・薄膜トランジスタ
２ ・・・基板
３ ・・・ゲート電極
４ ・・・ゲート絶縁層
５ ・・・半導体層
６ ・・・ソース電極
７ ・・・ドレイン電極
８ ・・・保護層 REFERENCE SIGNS LIST 1 thin film transistor 2 substrate 3 gate electrode 4 gate insulating layer 5 semiconductor layer 6 source electrode 7 drain electrode 8 protective layer

Claims (6)

酸化物半導体の上に酸窒化シリコン膜を成膜する成膜方法であって、
前記酸窒化シリコン膜を、ＳｉＦ４ガス、窒素ガス、酸素ガス及び水素ガスをプロセスガスとして供給して行うプラズマＣＶＤ法により成膜し、
前記供給するプロセスガスにおいて、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合が９３％以上であることを特徴とする成膜方法。 A film formation method for forming a silicon oxynitride film on an oxide semiconductor,
The silicon oxynitride film is formed by a plasma CVD method performed by supplying SiF 4 gas, nitrogen gas, oxygen gas and hydrogen gas as process gases,
A film forming method, wherein, in the process gas to be supplied, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas is 93% or more. 前記供給するプロセスガスにおいて、窒素ガスと酸素ガスの合計流量に対する窒素ガスの流量の割合が９６％以上である請求項１に記載の成膜方法。 2. The film forming method according to claim 1, wherein in said process gas to be supplied, the ratio of the flow rate of nitrogen gas to the total flow rate of nitrogen gas and oxygen gas is 96% or more. 前記酸窒化シリコン膜が、リーク電流密度が１×１０－５Ａ／ｃｍ２以下であり、絶縁破壊電界強度が３ＭＶ／ｃｍ以上のものである請求項１又は２に記載の成膜方法。 3. The film forming method according to claim 1, wherein the silicon oxynitride film has a leakage current density of 1×10 −5 A/cm 2 or less and a breakdown electric field strength of 3 MV/cm or more. 酸化物半導体がＩｎ－Ｇａ－Ｚｎ－Ｏにより構成されている請求項１～３のいずれか一項に記載の成膜方法。 4. The film forming method according to claim 1, wherein the oxide semiconductor is composed of In--Ga--Zn--O. 前記プラズマＣＶＤ法による前記酸窒化シリコン膜の成膜を３００℃以下で行う請求項１～４のいずれか一項に記載の成膜方法。 The film forming method according to any one of claims 1 to 4, wherein the silicon oxynitride film is formed by the plasma CVD method at 300°C or lower. Ｉｎ－Ｇａ－Ｚｎ－Ｏからなる酸化物半導体をチャネル層とする薄膜トランジスタの製造方法であって、
スパッタリングにより前記酸化物半導体を形成する半導体層形成工程と、
請求項１～５のいずれか一項に記載の成膜方法により、前記酸化物半導体の上に酸窒化シリコン膜から成る絶縁層を成膜する絶縁層形成工程と、を有することを特徴とする薄膜トランジスタの製造方法。 A method for manufacturing a thin film transistor having an oxide semiconductor made of In--Ga--Zn--O as a channel layer,
a semiconductor layer forming step of forming the oxide semiconductor by sputtering;
and an insulating layer forming step of forming an insulating layer made of a silicon oxynitride film on the oxide semiconductor by the film forming method according to any one of claims 1 to 5. A method for manufacturing a thin film transistor.
JP2021048568A 2021-03-23 2021-03-23 Film formation method for silicon oxynitride film and manufacturing method for thin film transistor Pending JP2022147359A (en)

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