JP2022019262A - Constant-voltage circuit - Google Patents

Abstract

To obtain a stable overcurrent protection characteristic without being affected by manufacturing variations of circuit elements in an overcurrent protection circuit.SOLUTION: A constant-voltage circuit includes: a third PchMOS type transistor whose gate is connected to a dividing circuit of an output voltage; a fourth PchMOS type transistor whose source and drain are connected to the third PchMOS type transistor in common; a first NchMOS type transistor whose source is connected to the sources of the third and fourth PchMOS type transistors via a fourth resistor element; a fifth PchMOS type transistor that eliminates a potential difference between the gate and source of the fourth PchMOS type transistor; and a second NchMOS type transistor and a fifth resistor element that eliminate a potential difference between the gate and source of the first NchMOS type transistor.SELECTED DRAWING: Figure 1

Description

The present invention relates to a constant voltage circuit capable of supplying a stabilized output voltage.

In a constant voltage circuit such as a regulator circuit that supplies a stabilized output voltage in a power supply circuit or the like, an overcurrent protection circuit is provided to protect the circuit and the device against a load short circuit or the like. In recent years, a stabilized power supply circuit (LDO (Low Drop-Out) regulator circuit) capable of low saturation operation has been used in response to a demand for low power consumption in in-vehicle applications and the like. In a constant voltage circuit of a linear regulator such as an LDO regulator circuit, it is required to protect overcurrent and suppress power consumption.

As a conventional example of a constant voltage circuit, for example, there is a constant voltage power supply circuit disclosed in Patent Document 1. In this conventional constant voltage power supply circuit, the overcurrent limiting function for overload and the short-circuit current limiting function for output short circuit can be set independently and arbitrarily, and the output voltage can be set up to the constant voltage range regardless of the startup conditions. It can be started, and even if external conditions such as input voltage conditions change, the F-shaped or foldback type overcurrent limit value can be optimally adjusted, and the hanging type overcurrent limit circuit can be operated properly to obtain the desired output current. It is possible to set the short-circuit current value to the optimum value.

Japanese Unexamined Patent Publication No. 2002-169618

In the conventional constant voltage circuit, the overcurrent limit value may fluctuate due to variations in the threshold voltage of the transistor used in the overcurrent protection circuit. Therefore, it is necessary to take a large margin between the operating current of the overcurrent protection circuit and the range of the output current normally used.

An object of the present invention is to provide a constant voltage circuit capable of obtaining stable overcurrent protection characteristics without being affected by manufacturing variations of circuit elements in the overcurrent protection circuit.

The present invention comprises a differential amplification circuit that outputs a voltage proportional to the difference between the voltage of the first voltage division terminal of the voltage division circuit that divides the output voltage and the reference voltage, and a gate at the output unit of the differential amplification circuit. Is a constant voltage circuit that includes a PchMOS type output transistor in which a source and a drain are connected between a power supply terminal and an output terminal, and obtains a predetermined voltage from the output terminal. A second PchMOS type transistor having a second voltage dividing terminal having a different voltage dividing ratio from the first voltage dividing terminal and having a common connection between the output transistor, a gate and a source, and the second voltage dividing terminal. A third PchMOS type transistor to which a gate is connected, a fourth PchMOS type transistor to which the reference voltage is supplied to the gate and the source and drain are commonly connected to the third PchMOS type transistor, and the above. A fifth PchMOS type transistor in which a source is connected to the drain of the second PchMOS type transistor via a third resistance element and the gate and drain are grounded, and the third and fourth PchMOS type transistors. A first NchMOS type transistor in which the source is connected to the source of the second PchMOS type transistor via a fourth resistance element and a gate is connected to the drain of the second PchMOS type transistor, and the third and fourth PchMOS type transistors. The drain of the second NchMOS type transistor whose drain is connected to the drain of the transistor, the gate is grounded, and the source is grounded via the fifth resistance element, and the drain of the third and fourth PchMOS type transistors. Provided is a constant voltage circuit comprising a first current mirror circuit having an input end connected to and an output end connected to an output portion of the differential amplification circuit, and an overcurrent protection circuit having.

Further, the present invention comprises a differential amplification circuit that outputs a voltage proportional to the difference between the voltage of the first voltage division terminal of the voltage division circuit that divides the output voltage and the reference voltage, and an output unit of the differential amplification circuit. A constant voltage circuit that includes a PchMOS type output transistor in which a gate is connected to the power supply terminal and a source and drain are connected between the power supply terminal and the output terminal, and obtains a predetermined voltage from the output terminal. The circuit is provided with a second voltage dividing terminal having a voltage dividing ratio different from that of the first voltage dividing terminal, and the output transistor is provided with a second PchMOS type transistor in which a gate and a source are commonly connected, and the second voltage dividing terminal. A third PchMOS type transistor having a gate connected to the terminal, and a fourth PchMOS type transistor to which the reference voltage is supplied to the gate and the source and drain are commonly connected to the third PchMOS type transistor. , The fifth PchMOS type transistor in which the source is connected to the drain of the second PchMOS type transistor via the third resistance element and the gate and drain are grounded, and the third and fourth PchMOS type transistors. A first NchMOS type transistor in which a source is connected to the source of the transistor of the above via a fourth resistance element and a gate is connected to the drain of the second PchMOS type transistor, and the first NchMOS type transistor. A third NchMOS type transistor in which a gate is connected to the drain of the transistor and a source is connected via a sixth resistance element and the drain is connected to the power supply terminal, and the first NchMOS type transistor. Provided is a constant voltage circuit comprising an overcurrent protection circuit comprising a second current mirror circuit having an input end connected to the drain and an output end connected to the output portion of the differential amplification circuit.

Further, the present invention is the above-mentioned constant voltage circuit, in which the fifth PchMOS type transistor has the same threshold voltage as the fourth PchMOS type transistor within a predetermined error range, and the second PchMOS type transistor has the same threshold voltage. The NchMOS type transistor has the same threshold voltage, gate width, and gate length as the first NchMOS type transistor within a predetermined error range, and the resistance values of the fourth resistance element and the fifth resistance element. Provides a constant voltage circuit in which is the same within a predetermined error range.

Further, the present invention is the constant voltage circuit described above, wherein the fifth PchMOS type transistor has the same threshold voltage as the fourth PchMOS type transistor within a predetermined error range, and the third PchMOS type transistor has the same threshold voltage. The NchMOS type transistor has the same threshold voltage, gate width, and gate length as the first NchMOS type transistor within a predetermined error range, and the resistance values of the fourth resistance element and the sixth resistance element. Provides a constant voltage circuit in which is the same within a predetermined error range.

According to the present invention, it is possible to provide a constant voltage circuit capable of obtaining stable overcurrent protection characteristics without being affected by manufacturing variations of circuit elements in the overcurrent protection circuit.

It is a circuit diagram which shows the structure of the constant voltage circuit of 1st Embodiment. It is a circuit diagram which shows the structure of the constant voltage circuit of 2nd Embodiment. It is a circuit diagram which shows the structure of the constant voltage circuit of the comparative example. It is a characteristic diagram which shows an example of the characteristic of an output voltage and an output current in a constant voltage circuit provided with an overcurrent protection circuit.

Hereinafter, an embodiment in which the constant voltage circuit according to the present invention is specifically disclosed (hereinafter, referred to as “the present embodiment”) will be described in detail with reference to the drawings.

(Background to this embodiment)
As an overcurrent protection circuit in a constant voltage circuit such as an LDO regulator circuit, there is a case where an overcurrent protection circuit having a so-called F-shaped characteristic is provided so that the overcurrent limit value of the output current decreases as the output voltage decreases during the overcurrent protection operation. be. Foldback protections, as an overcurrent protection operation, perform current limiting at the maximum limit value to reduce the output voltage, and then perform current foldback to reduce the output voltage. Therefore, the overcurrent limit value of the output current is lowered to prevent excessive power loss from occurring in the output element of the constant voltage circuit.

The following is an example of the configuration and operation of a constant voltage circuit provided with an overcurrent protection circuit having an F-shaped characteristic as a comparative example.

FIG. 3 is a circuit diagram showing the configuration of a constant voltage circuit of a comparative example. FIG. 4 is a characteristic diagram showing an example of the characteristics of the output voltage and the output current in the constant voltage circuit including the overcurrent protection circuit.

The constant voltage circuit 50 includes a differential amplifier circuit AMP1 as an error amplifier, an overcurrent protection circuit 60, and an output transistor MP1. The overcurrent protection circuit 60 includes an overcurrent limiting circuit 61 that limits the overcurrent and a F-shaped characteristic circuit 62 that realizes the F-shaped characteristic.

The overcurrent protection operation in the constant voltage circuit 50 will be described. Here, from the state where the output voltage V _OUT corresponding to the reference voltage Vref is output from the output terminal OUT, the resistance value of the load resistance RL connected between the output of the constant voltage circuit 50 and the ground gradually decreases. It is assumed that the drain current of the output transistor MP1, that is, the source current of the output terminal OUT gradually increases.

When the source current of the output terminal OUT increases, the drain currents of the transistor MP2 and the transistor MP10 connected in parallel to the output transistor MP1 increase accordingly. Along with this, the voltage generated in the resistors R3 and R7 through which the drain currents of the transistors MP2 and MP10 flow, respectively, also increases. When the voltage across the resistor R7 reaches the threshold voltage Vth _MN7 of the transistor MN7, the transistor MN7 turns on and sinks a current from the drain terminal of the transistor MN5.

The drain current of the transistor MN5 is folded back by the current mirror circuit composed of the transistors MP8 and MP9, and raises the gate terminal voltage of the output transistor MP1 that controls the output current. As a result, the drain current of the output transistor MP1 decreases, the output current of the constant voltage circuit 50 is controlled to a predetermined value or less, and the output voltage V _OUT begins to decrease. In FIG. 4, the source current of the output terminal OUT indicated by the line A is the point at which the above operation starts. The overcurrent limit value (maximum limit value) of the output current at this time is defined as _IOLIMA .

Next, the output voltage V _OUT of the output terminal OUT gradually decreases, and the gate voltage V _MP3 of the transistor MP3 connected to the connection points of the voltage dividing resistors R1 and R2 of the output voltage V _OUT has the following equation (1). When it falls below this, the drain current of the transistor MP3 begins to flow.

V _MP3 = (ID _MP1 / M) · R3- | VGS _MP3 | -VGS _MN1 ... (1)

Here, V _MP3 : the gate voltage of the transistor MP3, ID _MP1 : the drain current of the transistor MP1, M: the gate width ratio of the transistors MP1 and MP2 and the transistors MP1 and MP10, R3: the resistance value of the resistor R3, | VGS _MP3 |: Transistor MP3 gate-source potential difference, VGS _MN1 : Transistor MN1 (depression type) gate-source potential difference. Since the gate-source potential difference VGS _MP3 of the transistor MP3 is VGS _MP3 <0V, it is expressed as an absolute value in the equation (1). In the present specification, "・" represents a multiplier and "/" represents a divider.

The drain current of the transistor MP3 is folded back by the current mirror circuit composed of the transistors MN3 and MN4, and the current is synced from the drain terminal of the transistor MN5. As a result, the gate terminal voltage of the output transistor MP1 is raised, and the drain current of the output transistor MP1 is further reduced.

At this time, the gate aspect ratio of the transistors MP3 and MN1 whose sources are connected to each other via the resistor R4 is sufficiently large, and the gate-source potential difference of the transistors MP3 and MN1 is the drain current at which the overcurrent protection circuit operates. It is assumed that the value is close to the threshold voltage Vth of the element. In this case, the gate voltage V _MP3 of the transistor MP3 is represented by the following equation (2).

V _MP3 = (ID _MP1 / M) ・ R3 + Vth _MP3 －Vth _MN1 … (2)

Here, Vth _MN1 : the threshold voltage of the depletion type transistor MN1 (Vth _MN1 <0V), and Vth _MP3 : the threshold voltage of the transistor MP3 (Vth _MP3 <0V).

As the output voltage V _OUT of the output terminal OUT decreases, the transistor MN7 gradually turns off, but the gate voltage of the transistor MP3 further decreases, so that the transistor MP3 becomes conductive even if the voltage generated by the resistor R3 is lower. .. As a result, the source current of the output terminal OUT is reduced, and in a state where the output voltage V _OUT is short-circuited to the ground (V _OUT = 0V), the source current is reduced to the point of line B in FIG. Finally, the source current of the output terminal OUT drops to a value of about 1/3 to 1/4 from the peak time of the line A to the line B. By the above-mentioned operation, the overcurrent protection circuit 60 realizes the F-shaped characteristic.

In FIG. 4, the overcurrent limit value _IOLIMA of the output current of the constant voltage circuit 50, which corresponds to the shoulder portion of the F-shaped characteristic, is represented by the following equation (3).

_IOLIMA = (M / R7) ・ Vth _MN7 … (3)

Here, R7: the resistance value of the resistor R7, Vth _MN7 : the threshold voltage of the transistor MN7 (Vth _MN7 > 0V).

Further, the output voltage limit value _VOLIM of the constant voltage circuit 50, which corresponds to the arm portion of the F-shaped characteristic, is expressed by the following equation (4).

_VOLIM = (R1 + R2) / R2 ・ {( _IOLIMA / M) ・ R3
+ Vth _MP3 -Vth _MN1 } ... (4)

Here, R1: the resistance value of the resistor R1 and R2: the resistance value of the resistor R2.

In the constant voltage circuit 50 of the comparative example, when the output current of the constant voltage circuit 50 is close to 0A, the voltage generated in the resistor R3 also drops to the vicinity of the ground potential. Therefore, a voltage in the direction opposite to the conduction state is applied to the potential difference VGSMP3 between the gate and the source of the transistor MP3, the transistor MP3 is turned off, and no current is consumed in this portion. Therefore, there is an advantage that it is easy to configure a circuit with low power consumption in a no-load state. In addition, there are few elements constituting the circuit, and there is an advantage that the circuit can be simplified and miniaturized.

On the other hand, in the above-mentioned conventional example of Patent Document 1, a differential amplifier circuit is used for the overcurrent protection circuit as shown in FIG. 3 of Patent Document 1. Therefore, even if the load resistance is not connected to the output end of the constant voltage circuit, the current of the current source connected between the comparator A3 of the differential amplifier circuit and the power supply terminal VDD will continue to flow. There is a problem that it is difficult to reduce power consumption. Further, in the conventional constant voltage circuit, the overcurrent limit value may fluctuate due to the variation of the threshold voltage of the transistor used in the overcurrent protection circuit, the variation of the resistance value of the resistance element, the temperature change, and the like. Therefore, it is necessary to take a large margin between the operating current of the overcurrent protection circuit and the range of the output current normally used.

On the other hand, in the configuration of the comparative example, as shown in the above equations (2) to (4), the overcurrent limit value and the output voltage limit value fluctuate due to the variation of the threshold voltage Vth of the transistors MN1, MP3, and MN7. There are challenges. Therefore, even in the comparative example, it is necessary to take a large margin between the operating current of the overcurrent protection circuit and the range of the output current normally used.

In this embodiment, in view of the above circumstances, it is possible to reduce the influence of manufacturing variations of circuit elements such as the threshold voltage of the transistor in the overcurrent protection circuit of the constant voltage circuit, and suppress fluctuations in the overcurrent limit value and the output voltage limit value. , A configuration example of a constant voltage circuit capable of obtaining stable overcurrent protection characteristics is shown.

(First Embodiment)
FIG. 1 is a circuit diagram showing a configuration of a constant voltage circuit according to the first embodiment. The constant voltage circuit 10A of the present embodiment includes a differential amplifier circuit AMP1 as an error amplifier, an overcurrent protection circuit 20A, and an output transistor MP1 which is a PchMOS type transistor. The output transistor MP1 has a source connected to the power supply terminal VDD and outputs a predetermined output voltage V _OUT from the drain. The drain of the output transistor MP1 is provided with an output terminal OUT, and voltage dividing resistors R1 and R2 as voltage dividing circuits for dividing the output voltage V _OUT are connected in series. A resistor R6 is inserted between the voltage dividing resistors R1 and R2. That is, the voltage divider circuit has a first voltage divider terminal and a second voltage divider terminal having different voltage divider ratios, and the connection point between the voltage divider resistor R2 and the resistor R6 is the first voltage divider terminal and the voltage divider. The connection point between the resistor R1 and the resistor R6 is the second voltage dividing terminal. A load resistance RL and a capacitor CL are connected to the output terminal OUT.

The differential amplifier circuit AMP1 compares a voltage proportional to the output voltage V _OUT with the reference voltage Vref of the voltage source V1 and outputs an error component of the output voltage V _OUT . The differential amplifier circuit AMP1 has two NchMOS type transistors MN5 and MN6 to which a source is commonly connected, a current source I1, and PchMOS type transistors MP8 and MP9 constituting a current mirror circuit. In the transistors MN5 and MN6, the current source I1 is connected to the source, and the current mirror circuit by the transistors MP8 and MP9 is connected to the drain. A voltage source V1 is connected to the gate of the transistor MN6, which is one input end of the differential amplifier circuit AMP1, and a reference voltage Vref is supplied. The gate of the transistor MN5, which is the other input end of the differential amplifier circuit AMP1, is connected to the connection point between the voltage dividing resistor R2 and the resistor R6 as the first voltage dividing terminal, and is connected to the output voltage V _OUT of the output transistor MP1. A proportional voltage is input. In the differential amplifier circuit AMP1, in the output section, the drain current of the transistor MN5 is folded back by the current mirror circuit by the transistors MP8 and MP9, and the drain of the transistor MP9 is connected to the gate of the output transistor MP1. Here, in the input / output of the current mirror circuit of the differential amplifier circuit AMP1, the drain of the transistor MN5 and the drain of the transistor MP9 are both included in the output unit of the differential amplifier circuit AMP1. The output unit of the differential amplifier circuit AMP1 is connected to the gate of the output transistor MP1.

The overcurrent protection circuit 20A has PchMOS type transistors MP2, MP3, MP4, MP5, NchMOS type transistors MN1, MN2, MN3, MN4, and resistors R3, R4, R5. The gate and source of the transistor MP2 (second PchMOS type transistor) are connected in parallel with the output transistor MP1. The source of the transistor MP5 (fifth PchMOS type transistor) is connected to the drain of the transistor MP2 via the resistor R3 (third resistance element), and the gate and drain of the transistor MP5 are grounded.

Further, in the transistor MN1 (first NchMOS type transistor) which is a depletion type Nch MOSFET, the drain is connected to the source of the transistors MP1 and MP2, and the gate is connected to the drain of the transistor MP2. The source of the transistor MN1 is connected to the source of the transistor MP3 (third PchMOS type transistor) and the source of the transistor MP4 (fourth PchMOS type transistor) together via the resistor R4 (fourth resistance element).

A first current mirror circuit by the transistors MN3 and MN4 is connected to the drains of the transistors MP3 and MP4. In the first current mirror circuit, the gates of the transistors MN3 and MN4 are connected to each other, the drain and the gate of the transistor MN3 are the input ends, the source of the transistors MN3 and MN4 is grounded, and the drain of the transistor MN4 is the output end. It is connected to the drain of the transistor MN5. The drain of the transistor MN5 is connected to the gate of the output transistor MP1 via a current mirror circuit by the transistors MP8 and MP9.

The gate of the transistor MP3 is connected to the connection point between the voltage dividing resistor R1 and the resistor R6 as the second voltage dividing terminal, and a voltage proportional to the output voltage V _OUT of the output transistor MP1 is input. The gate of the transistor MP4 is connected to a reference voltage source that supplies the reference voltage Vref. Further, the drain of the transistor MN2 (second NchMOS type transistor), which is a depletion type Nch MOSFET, is connected to the drains of the transistors MP3 and MP4. One end of the resistor R5 (fifth resistance element) is connected to the source of the transistor MN2, and the gate of the transistor MN2 and the other end of the resistor R5 are grounded.

The present embodiment differs from the configuration of the comparative example shown in FIG. 3 in the following points. In addition to eliminating the transistor MP10, resistor R7, and transistor MN7 in the comparative example, a transistor MP4 in which the drain and source are commonly connected to the drain and source of the transistor MP3 is added to the circuit part that obtains the F-shaped characteristic. There is. Further, a transistor MP5 having the same threshold voltage as the transistors MP3 and MP4 is inserted between the resistor R3 and the ground so that the drain and the gate are connected to the ground and the source is connected to the resistor R3. Further, the gate of the transistor MP3 is not connected in common with the gate of the transistor MN5 which is the input end of the differential amplifier circuit AMP1, and the resistor R6 is inserted between the voltage dividing resistors R1 and R2 so that the gate voltage of the transistor MP3 is increased. The potential difference is made so that the voltage becomes a little high. Further, a depletion type transistor MN2 having the same threshold voltage as the transistor MN1 is connected between the drain and the ground of the transistors MP3 and MP4.

In the transistor MP5, in order to cancel the influence of the potential difference between the gate and the source of the transistor MP4, it is preferable that the threshold voltage is the same as the threshold voltage of the transistor MP4 within a predetermined error range. In the transistor MN2, the threshold voltage is preferably the same as the threshold voltage of the transistor MN1 within a predetermined error range in order to cancel the influence of the potential difference between the gate and the source of the transistor MN1. It is preferable that the resistance R5 has the same resistance value as the resistance value of the resistor R4 within a predetermined error range in order to cancel the influence of the potential difference between the gate and the source of the transistor MN1.

Next, the operation of the overcurrent protection circuit 20A in the constant voltage circuit 10A of the present embodiment will be described.

When the resistance value of the load resistance RL gradually decreases and the source current from the output terminal OUT increases, the current flowing through the resistor R3 and the transistor MP5 increases, and the gate voltage of the transistor MN1 rises. As a result, the drain current of the transistor MP4 starts to flow from the vicinity where the source voltage of the transistors MP3 and MP4 exceeds (reference voltage Vref) + (threshold voltage of the transistor MP4). Since the gate voltage of the transistor MP3 is higher than the reference voltage Vref applied to the gate of the transistor MP4, the transistor MP3 is turned off. The drain current of the output transistor MP1 at the beginning of the flow of the drain current of the transistor MP4 is obtained by the following equation (5).

ID _MP1 = (M / R3) · (Vref-Vth _MP4 + Vth _MP5
＋ R4 ・ ID _MP3 ＋ Vth _MN1 )… (5)

Here, ID _MP1 : the drain current of the transistor MP1, M: the gate width ratio of the transistors MP1 and MP2, R3: the resistance value of the resistor R3, Vref: the reference voltage of the output of the voltage source V1, and Vth _MP4 : the threshold voltage of the transistor MP4. (Vth _MP4 <0V), Vth _MP5 : Transistor MP5 threshold voltage (Vth _MP5 <0V), R4: Transistor R4 resistance value, ID _MP3 : Transistor MP3 drain current, Vth _MN1 : Transistor MN1 threshold voltage (Vth _MN1 ) <0V).

At this time, the gate voltage of the transistor MP4 is constant at the reference voltage Vref, and the threshold voltage Vth _MP4 of the transistor MP4 is canceled by the threshold voltage Vth _MP5 of the transistor MP5 having the same threshold.

Further, the transistor MN2, which is a depletion type Nch MOSFET, has a resistor R5 at the source. In order for the transistor MP4 to start flowing the drain current and to start suppressing the source current of the output terminal OUT, the drain current of the transistor MP4 needs to exceed the drain current of the transistor MN2.

The drain current of the transistor MN2 is expressed by the following equation (6), assuming that the gate aspect ratio of the transistor MN2 is sufficiently large and the potential difference between the gate and the source of the MN2 is operating near the threshold voltage Vth _MN2 of the MN2. ..

ID _MN2 = | Vth _MN2 | / R5 ... (6)

Here, ID _MN2 : the drain current of the transistor MN2, | Vth _MN2 |: the absolute value of the threshold voltage (Vth _MN2 <0V) of the transistor MN2.

When the resistance R4 and the resistance R5 are resistance elements having the same resistance value, the transistors MN1 and MN2 have the same threshold voltage Vth, and the gate width and the gate length are the same, the resistance R4 has the threshold voltage of the depletion type transistor MN2. Equal voltages are generated, and the source voltage of the transistor MP4 and the gate voltage of the transistor MN1 can be made substantially equal. Therefore, it is possible to cancel the influence of the threshold voltage Vth _MN1 of the transistor MN1.

In the configuration of the present embodiment, the overcurrent limit value _IOLIMA of the output current of the constant voltage circuit 10A, which corresponds to the shoulder portion of the F-shaped characteristic shown in FIG. 4, is represented by the following equation (7). ..

_IOLIMA ≒ (M / R3) ・ Vref… (7)

When the value of the load resistance RL is further reduced, the drain current of the output transistor MP1 is limited, so that the output voltage V _OUT of the output terminal OUT begins to decrease. As a result, when the gate voltage of the transistor MP3 decreases and becomes a voltage near the reference voltage Vref, the drain current of the transistor MP3 increases, the drain current of the transistor MP4 decreases, and the drain current of the output transistor MP1 is the gate voltage of the transistor MP3. Is controlled by. Therefore, as the gate voltage of the transistor MP3 decreases, the source current of the output terminal OUT decreases.

The output voltage limit value _VOLIM of the constant voltage circuit 10A, which corresponds to the arm portion of the F-shaped characteristic shown in FIG. 4, is represented by the following equation (8).

_VOLIM ≒ (R1 + R2 + R6) / (R2 + R6) ・ Vref ... (8)

Here, R1: the resistance value of the resistor R1, R2: the resistance value of the resistor R2, and R6: the resistance value of the resistor R6. In this embodiment, by providing a resistor R6 in the voltage dividing resistance of the output voltage, the reference voltage Vref is used for both the overcurrent limit value and the output voltage limit value, and the arm portion of the F-shaped characteristic is realized. There is.

Through the above process, the constant voltage circuit 10A of the present embodiment of FIG. 1 also has the same overcurrent protection characteristics as the constant voltage circuit 50 of the comparative example of FIG. That is, as the output voltage V _OUT of the output terminal OUT decreases, the gate voltage of the transistor MP3 further decreases and the source current of the output terminal OUT decreases.

In the overcurrent protection circuit 20A of the present embodiment, the threshold voltage of the transistor MP4 is canceled by the threshold voltage of the transistor MP5, and the threshold voltage of the transistor MN1 is canceled by the voltage generated in the resistor R4. Can be reduced.

When there is no load resistance RL of the output terminal OUT, the drain current of the transistor MN1 is also stopped by turning off the transistors MP3 and MP4, as in the constant voltage circuit of the comparative example. Therefore, it is possible to configure a low power consumption circuit in a no-load state without consuming current in the overcurrent protection circuit 20A.

As described above, in the first embodiment, a transistor MP4 in which the transistor MP3 and the drain and the source are commonly connected is provided, and the gate of the transistor MP4 is connected to the voltage source V1 to supply the reference voltage Vref. It has become. Further, a resistor R6 is provided between the voltage dividing resistors R1 and R2 to provide a predetermined potential difference between the gate voltage of the transistor MP3 and the gate voltage of the transistor MN5 which is the input end of the differential amplifier circuit AMP1. It is composed. Further, the transistor MP5 for canceling the influence of the gate-source potential difference of the transistor MP4 is provided, and the transistor MN2 and the resistors R4 and R5 for canceling the influence of the gate-source potential difference of the transistor MN1 are provided. ..

According to the first embodiment, in the overcurrent protection operation, the influence of the variation of each element such as the threshold voltage of the transistor MN1 and the like can be reduced, and the fluctuation of the overcurrent limit value and the output voltage limit value can be suppressed. , It is possible to reduce the margin of the operating current of the overcurrent protection circuit. The circuit configuration of FIG. 1 can obtain stable overcurrent protection characteristics even in a circuit designed with a low power supply voltage in order to further reduce power consumption.

(Second embodiment)
FIG. 2 is a circuit diagram showing the configuration of the constant voltage circuit of the second embodiment. The second embodiment is a modification of the first embodiment, and shows another configuration example in which the position of the current mirror circuit in the overcurrent protection circuit is changed. Here, the description of the configuration portion similar to that of the first embodiment shown in FIG. 1 will be omitted, and the description will be centered on the portion having a different configuration.

The overcurrent protection circuit 20B of the constant voltage circuit 10B has PchMOS type transistors MP2, MP3, MP4, MP5, NchMOS type transistors MN1 and resistors R3, R4, as in FIG. It also has an NchMOS type transistor MN8, a PchMOS type transistor MP6, MP7, and a resistor R8.

In the second embodiment, the input of the second current mirror circuit by the transistors MP6 and MP7 is provided between the drain of the transistor MN1 and the power supply terminal VDD of the constant voltage circuit 10B. As a result, the drain current of the transistor MN1 is folded back by the current mirror circuit, the gate voltage of the output transistor MP1 is raised, and the source current of the output terminal OUT is controlled. On the other hand, the drains of the transistors MP3 and MP4 are directly connected to the ground and grounded. Further, the gate of the transistor MN8 (third NchMOS type transistor), which is a depletion type Nch MOSFET, is connected to the drain of the transistor MN1, and the source of the transistor MN8 is further connected via the resistor R8 (sixth resistance element). Will be done. The drain of the transistor MN8 is connected to the power supply terminal VDD.

In the second current mirror circuit, the gates of the transistors MP6 and MP7 are connected to each other, the drain and the gate of the transistors MP6 are input ends, the source of the transistors MP6 and MP7 is connected to the power supply terminal VDD, and the drain of the transistor MP7 is output. At the end, it is connected to the output unit of the differential amplifier circuit AMP1 and the gate of the output transistor MP1. The configuration of other parts is the same as that of the first embodiment shown in FIG.

In the transistor MN8, the threshold voltage is preferably the same as the threshold voltage of the transistor MN1 within a predetermined error range in order to cancel the influence of the potential difference between the gate and the source of the transistor MN1. It is preferable that the resistance R8 has the same resistance value as the resistance value of the resistor R4 within a predetermined error range in order to cancel the influence of the potential difference between the gate and the source of the transistor MN1.

In the constant voltage circuit 10A of FIG. 1, when the output terminal OUT is short-circuited to ground, the gate voltage of the transistor MP3 is lowered to the ground potential. On the other hand, in the transistor MN3 which is an input element of the current mirror circuit, the gate-drain voltage of the transistor MN3 needs to be equal to or higher than the threshold voltage of the transistor MN3 in order to allow the operating current to flow. As a result, the potential difference between the drain and the source of the transistor MP3 is reduced, and the operation of the transistor MP3 changes from the operation in the saturated region to the operation in the unsaturated region. Therefore, the potential difference between the drain and the source of the transistors MP3 and MP4 cannot be sufficiently secured, and in order to pass the same drain current through the transistor MP5, a more potential difference between the gate and the source is required, and the potential difference between the gate and the source of the transistor MP5 is required. The voltage difference increases. As a result, when the output voltage drops near the ground potential when the load is short-circuited, the output current (source current of the output terminal OUT) tends to change with respect to the fluctuation of the threshold voltage Vth of the transistors MP3 and MP5.

In the second embodiment of FIG. 2, the above problem is avoided by forming a circuit configuration in which the drain current of the transistor MN1 is folded back by the current mirror circuit by the transistors MP6 and MP7 connected to the power supply terminal VDD side. In order to cancel the variation in the threshold voltage of the transistor MN1, the depletion type transistor MN8 and the resistance R8 connected to the source thereof are connected between the power supply terminal VDD and the drain terminal of the transistor MN1. As a result, when the current mirror circuit using the transistors MP6 and MP7 operates, a voltage that cancels the threshold voltage Vth _MN1 of the transistor MN1 can be generated in the resistor R4 as in the first embodiment.

As described above, in the second embodiment, the second current mirror circuit by the transistors MP6 and MP7 is provided between the drain of the transistor MN1 and the power supply terminal VDD for the configuration of the first embodiment, and the transistor is provided. The output voltage of the differential amplifier circuit AMP1 is controlled by the drain current of the MN1. Further, the transistor MN8 and the resistor R8 are provided to cancel the influence of the potential difference between the gate and the source of the transistor MN1.

Also in the second embodiment, the influence of the variation of each element such as the threshold voltage of the transistor MN1 and the like in the overcurrent protection operation can be reduced, and the fluctuation of the overcurrent limit value and the output voltage limit value can be suppressed. In the circuit configuration of FIG. 2, since the fluctuation of the overcurrent limit value can be suppressed in the region where the output voltage is close to the ground potential such as when the load is short-circuited, the accuracy of the overcurrent protection characteristic can be improved and a stable overcurrent protection characteristic can be obtained. It is possible.

Although various embodiments have been described above with reference to the drawings, it goes without saying that the present invention is not limited to such examples. It is clear that a person skilled in the art can come up with various modifications or modifications within the scope of the claims, which naturally belong to the technical scope of the present invention. Understood. Further, each component in the above embodiment may be arbitrarily combined as long as the gist of the present invention is not deviated.

INDUSTRIAL APPLICABILITY The present invention has the effect of obtaining stable overcurrent protection characteristics without being affected by manufacturing variations of circuit elements in the overcurrent protection circuit, and is useful for constant voltage circuits such as LDOs.

10A, 10B: Constant voltage circuit 20A, 20B: Overcurrent protection circuit AMP1: Differential amplifier circuit MP1: Output transistor MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9: Transistor (PchMOS)
MN1, MN2, MN3, MN4, MN5, MN6: Transistor (NchMOS)
R1, R2, R3, R4, R5, R6, R8: Resistance RL: Load resistance CL: Capacitor I1: Current source V1: Voltage source (reference voltage Vref)

Claims (4)

A gate is connected to a differential amplifier circuit that outputs a voltage proportional to the difference between the voltage of the first voltage dividing terminal of the voltage dividing circuit that divides the output voltage and the reference voltage, and an output unit of the differential amplifier circuit. A constant voltage circuit that includes a PchMOS type output transistor in which a source and a drain are connected between a power supply terminal and an output terminal, and obtains a predetermined voltage from the output terminal.
The voltage dividing circuit is provided with a second voltage dividing terminal having a different voltage dividing ratio from the first voltage dividing terminal.
A second PchMOS type transistor in which the output transistor and the gate and source are commonly connected, and
A third PchMOS type transistor in which a gate is connected to the second voltage dividing terminal, and
A fourth PchMOS type transistor to which the reference voltage is supplied to the gate and the source and drain are commonly connected to the third PchMOS type transistor.
A fifth PchMOS type transistor in which a source is connected to the drain of the second PchMOS type transistor via a third resistance element and the gate and drain are grounded.
A first NchMOS type transistor in which the source is connected to the source of the third and fourth PchMOS type transistors via a fourth resistance element, and the gate is connected to the drain of the second PchMOS type transistor. When,
A second NchMOS type transistor in which the drain is connected to the drain of the third and fourth PchMOS type transistors, the gate is grounded, and the source is grounded via the fifth resistance element.
A first current mirror circuit in which an input end is connected to the drain of the third and fourth PchMOS type transistors and an output end is connected to the output portion of the differential amplifier circuit.
A constant voltage circuit with an overcurrent protection circuit. A gate is connected to a differential amplifier circuit that outputs a voltage proportional to the difference between the voltage of the first voltage dividing terminal of the voltage dividing circuit that divides the output voltage and the reference voltage, and an output unit of the differential amplifier circuit. A constant voltage circuit that includes a PchMOS type output transistor in which a source and a drain are connected between a power supply terminal and an output terminal, and obtains a predetermined voltage from the output terminal.
The voltage dividing circuit is provided with a second voltage dividing terminal having a different voltage dividing ratio from the first voltage dividing terminal.
A second PchMOS type transistor in which the output transistor and the gate and source are commonly connected, and
A third PchMOS type transistor in which a gate is connected to the second voltage dividing terminal, and
A fourth PchMOS type transistor to which the reference voltage is supplied to the gate and the source and drain are commonly connected to the third PchMOS type transistor.
A fifth PchMOS type transistor in which a source is connected to the drain of the second PchMOS type transistor via a third resistance element and the gate and drain are grounded.
A first NchMOS type transistor in which the source is connected to the source of the third and fourth PchMOS type transistors via a fourth resistance element, and the gate is connected to the drain of the second PchMOS type transistor. When,
A third NchMOS type transistor in which a gate is connected to the drain of the first NchMOS type transistor, a source is connected via a sixth resistance element, and the drain is connected to the power supply terminal.
A second current mirror circuit in which an input end is connected to the drain of the first NchMOS type transistor and an output end is connected to the output portion of the differential amplifier circuit.
A constant voltage circuit with an overcurrent protection circuit. The constant voltage circuit according to claim 1.
The fifth PchMOS type transistor has the same threshold voltage as the fourth PchMOS type transistor within a predetermined error range.
The second NchMOS type transistor has the same threshold voltage, gate width, and gate length as the first NchMOS type transistor within a predetermined error range.
A constant voltage circuit in which the resistance values of the fourth resistance element and the fifth resistance element are the same within a predetermined error range. The constant voltage circuit according to claim 2.
The fifth PchMOS type transistor has the same threshold voltage as the fourth PchMOS type transistor within a predetermined error range.
The third NchMOS type transistor has the same threshold voltage, gate width, and gate length as the first NchMOS type transistor within a predetermined error range.
A constant voltage circuit in which the resistance values of the fourth resistance element and the sixth resistance element are the same within a predetermined error range.

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