JP2022006824A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device including a memory cell in which sizes of a control gate and a floating gate can be independently designed with each other.SOLUTION: A semiconductor device 1 includes: an epitaxial layer 9; a first p-type well 17 formed in the epitaxial layer 9; an n-type source region 18 and an n-type drain region formed in the first p-type well and separated from each other; a floating gate 38 facing a channel region via a gate insulation film 35; an n-type well 32 facing the floating gate 38 via the gate insulation film 35 as a control gate; and a p-type impurity diffusion region 21 formed adjacent to the n-type source region 18 in the first p-type well 17, having higher impurity concentration than the first p-type well 17, and forming a pn junction part (diode 22) between itself and the n-type source region 18.SELECTED DRAWING: Figure 6

Description

The present invention relates to a semiconductor device having a memory cell.

Patent Document 1 is an example of a document that discloses a semiconductor device including a non-volatile memory. The semiconductor device of Patent Document 1 includes a gate electrode provided on a p-type semiconductor substrate via a gate oxide film, and a pair of n-type impurities at positions in the surface layer region of the semiconductor substrate and sandwiching the gate electrode. It includes a transistor having a source region and a drain region, which are diffusion regions of the above. In the region sandwiched between the source region, the drain region and the channel forming region, a first resistance changing portion and a second resistance changing portion, which are regions having a lower n-type impurity concentration than the source region and the drain region, are provided, respectively. There is.

Japanese Unexamined Patent Publication No. 2005-06425

The semiconductor device according to the embodiment of the present invention is of a semiconductor layer, a first conductive type region formed in the semiconductor layer, and a second conductive type region formed in the first region and separated from each other. The first impurity diffusion region and the second impurity diffusion region, and the channel region between the first impurity diffusion region and the second impurity diffusion region in the first region are opposed to each other via the first insulating film. A floating gate, a control gate facing the floating gate via a second insulating film, and a first region formed adjacent to the first impurity diffusion region in the first region and higher than the first region. It has a conductive type impurity concentration and includes a third impurity diffusion region that forms a pn junction with the first impurity diffusion region.

FIG. 1 is a schematic perspective view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a block diagram showing an overall configuration of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a schematic plan view of the memory cell of FIG. 2 in cell units. FIG. 4 is a cross-sectional view taken along the IV-IV cross section of FIG. FIG. 5 is a cross-sectional view taken along the line VV of FIG. FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG. 7A and 7B are diagrams showing a modified example of the bonding state between the n-type source region and the p-type impurity diffusion region. FIG. 8 is a diagram for explaining an operation mechanism at the time of writing the memory. FIG. 9 is a diagram for explaining an operation mechanism at the time of writing the memory. FIG. 10 is a diagram showing a modified example of the plane layout of the memory cell.

<Embodiment of the present invention>
First, embodiments of the present invention will be listed and described.
The semiconductor device according to the embodiment of the present invention is of a semiconductor layer, a first conductive type region formed in the semiconductor layer, and a second conductive type region formed in the first region and separated from each other. The first impurity diffusion region and the second impurity diffusion region, and the channel region between the first impurity diffusion region and the second impurity diffusion region in the first region are opposed to each other via the first insulating film. A floating gate, a control gate facing the floating gate via a second insulating film, and a first region formed adjacent to the first impurity diffusion region in the first region and higher than the first region. It has a conductive type impurity concentration and includes a third impurity diffusion region that forms a pn junction with the first impurity diffusion region.

According to this configuration, a third impurity diffusion region is formed in the first region, and a pn is formed between the third impurity diffusion region (first conductive type) and the first impurity diffusion region (second conductive type). A diode consisting of a junction is formed. As a result, in addition to the hot carriers generated when a channel is formed between the first impurity diffusion region and the second impurity diffusion region and a current is passed, the hot carriers generated by avalanche breakdown of the diode are floated. Can be injected into. As a result, the number of hot carriers can be increased, so that the hot carrier injection efficiency can be improved. Therefore, the write efficiency of the memory can be improved.

Further, since the first region and the third impurity diffusion region are independent of each other, the respective impurity concentrations can be designed separately. For example, the impurity concentration in the third impurity diffusion region is designed to be relatively high in order to match the target breakdown voltage of the diode, while the impurity concentration in the first region is designed to be relatively lower than the third impurity diffusion region. May be. That is, the impurity concentration in the first region can be independently designed regardless of the target value (design value) of the breakdown voltage of the diode.

Thereby, for example, by relatively lowering the impurity concentration in the first region, the threshold voltage at the time of the read operation in the initial state of the memory can be lowered. Further, for example, when an element other than the memory (for example, an element constituting a logic circuit) is mixedly mounted on the semiconductor layer, the impurity concentration in the first region is adjusted according to the design of the impurity region of the other element. It can also be adjusted.

In the semiconductor device according to the embodiment of the present invention, the control gate includes a second conductive type second region formed on the semiconductor layer, and the floating gate is formed in the first region and the second region. It may be formed so as to straddle and face the second region via the second insulating film.
According to this configuration, the sizes of the control gate and the floating gate can be designed independently of each other.

When the semiconductor device according to the embodiment of the present invention includes an element separation structure for separating the semiconductor layer into a first active region and a second active region, the first region is formed in the first active region. The first well may be included, and the second region may include a second well formed in the second active region.
In the semiconductor device according to the embodiment of the present invention, the floating gate is formed on the first portion formed on the first active region and the second active region, and has a width larger than that of the first portion. May include a second portion having.

In the semiconductor device according to the embodiment of the present invention, the second portion is formed by a solid pattern covering the second active region, and the first portion is formed by a line pattern extending from the second portion of the solid pattern. It may have been done.
In the semiconductor device according to the embodiment of the present invention, the second insulating film may be formed continuously with the first insulating film.

In the semiconductor device according to the embodiment of the present invention, a plurality of independent floating gates may face the second region.
In the semiconductor device according to the embodiment of the present invention, the pn junction may form a Zener diode.
In the semiconductor device according to the embodiment of the present invention, the first impurity diffusion region includes a first high concentration portion having an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 , and the first high concentration portion is included. The 3 impurity diffusion region may include a second high concentration portion having an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 , which is a higher impurity concentration than the first region.

In the semiconductor device according to the embodiment of the present invention, the Zener diode may include a pn junction formed by a junction between the first high concentration portion and the second high concentration portion.
In the semiconductor device according to the embodiment of the present invention, the first impurity diffusion region further includes a first low concentration portion having an impurity concentration lower than that of the first high concentration portion, and the third impurity diffusion region is The second high-concentration portion and the second low-concentration portion having an impurity concentration lower than that of the first region are further included, and the Zener diode is formed by joining the first low-concentration portion and the second low-concentration portion. It may include a pn junction that has been formed.

In the semiconductor device according to the embodiment of the present invention, the first low-concentration section has an impurity concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 , and the second low-concentration section has an impurity concentration of 1 × 10 15 cm -3 to 1 × 10 18 cm -3. It may have an impurity concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 .
In the semiconductor device according to the embodiment of the present invention, the first region may have an impurity concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 .
<Detailed Description of Embodiments of the Present Invention>
Next, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
[Planar structure of memory cell]
FIG. 1 is a schematic perspective view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 2 is a block diagram showing an overall configuration of a semiconductor device 1 according to an embodiment of the present invention. In FIG. 2, some rows and columns of the matrix-shaped memory cell 4 are omitted due to the space limitation of the drawing, and the omitted parts are indicated by “...”.

With reference to FIG. 1, the semiconductor device 1 may be, for example, a chip-shaped LSI (Large Scale Integration). In this embodiment, the semiconductor device 1 is an analog LSI, and includes a memory area 2 and a logic area 3 in which a circuit for controlling the memory of the memory area 2 is formed as one of the components of the circuit of the LSI. You may be.
With reference to FIG. 2, the memory area 2 includes the memory cell 4. The memory cell 4 is electrically connected to, for example, the logic circuit 5 formed in the logic region 3 via the wiring 6. Although only one wiring 6 is shown in FIG. 2, for example, a gate wire, a bit wire, or the like may be included.

The memory cell 4 is formed by arranging the cell units 7 hatched in FIG. 2 in a matrix (= m × n). In this embodiment, in the memory cell 4, for example, m rows along the first direction X may be 32 to 1024 rows, and n columns along the second direction Y may be 32 to 512 columns. The memory cell 4 may have a capacity on the order of kilobits. Here, the kilobit order may be 1 K (kilo) bits or more and less than 1 M (mega) bits. That is, the memory cell 4 may include 1000 to n (n <1,000,000) cell units 7 in total.
[Structure of cell unit 7]
FIG. 3 is a schematic plan view of the cell unit 7 of the memory cell 4 of FIG. FIG. 4 is a cross-sectional view taken along the IV-IV cross section of FIG. FIG. 5 is a cross-sectional view taken along the line VV of FIG. FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG. 7A and 7B are diagrams showing a modified example of the bonding state between the n-type source region 18 and the p-type impurity diffusion region 21.

First, referring to FIG. 3, the portion surrounded by the alternate long and short dash line is one of the cell units 7 of the memory cell 4 of FIG. 2, and forms a cell of 1 bit of memory.
With reference to FIGS. 4-6, the semiconductor device 1 includes a substrate 8 and an epitaxial layer 9. Although the substrate 8 is made of a p ^- type silicon substrate in this embodiment, it may be a substrate 8 made of another material (for example, silicon carbide (SiC) or the like). The impurity concentration of the substrate 8 may be, for example, 1 × 10 ¹⁴ cm ^-3 to 5 × 10 ¹⁸ cm ^-3 . The thickness of the substrate 8 is, for example, 500 μm to 800 μm before grinding.

The epitaxial layer 9 is formed on the substrate 8. Although the epitaxial layer 9 is composed of a p ^- type silicon layer in this embodiment, it may be composed of another material (for example, silicon carbide (SiC) or the like). The impurity concentration of the epitaxial layer 9 may be, for example, 5 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 . The thickness of the epitaxial layer 9 is, for example, 3 μm to 20 μm.

The element separation structure 10 is formed on the epitaxial layer 9. In this embodiment, the element separation structure 10 partitions a first active region 11 for transistors, a second active region 12 for capacitors, and a third active region 13 for contacts. In FIG. 3, for clarification, the region of the element separation structure 10 is hatched.
Each element separation structure 10 may include an STI (Shallow Trench Isolation) structure. In this case, each element separation structure 10 includes a trench 14 and an insulator 15 embedded in the trench 14. Of course, the element separation structure 10 may be another element separation structure such as a LOCOS oxide film or a DTI (Deep Trench Isolation) structure. Further, although not shown, the element separation structure 10 may include a structure that separates the memory area 2 and the logic area 3.

The structure of the MOSFET 16 is formed in the first active region 11 for the transistor. More specifically, in the first active region 11, a first p-type well 17 as an example of the first region of the present invention is formed. The first p-type well 17 has a higher impurity concentration than the epitaxial layer 9, for example, 1.0 × 10 ¹⁷ cm ^-3 to 1.0 × 10 ¹⁹ cm ^-3 . May be good.

On the surface of the first p-type well 17, an n-type source region 18 as an example of the first impurity diffusion region of the present invention and an n-type drain region 19 as an example of the second impurity diffusion region of the present invention are first. They are formed at a distance from each other in the direction X. On the surface of the first p-type well 17, the region between the n-type source region 18 and the n-type drain region 19 is the channel region 20 in which the channel of the MOSFET 16 is formed.

Further, a p-type impurity diffusion region 21 as an example of the third impurity diffusion region of the present invention is formed on the surface of the first p-type well 17. As shown in FIG. 3, the p-type impurity diffusion region 21 is separated from the n-type drain region 19 in the first direction X and adjacent to the n-type source region 18 in the second direction Y. As a result, a pn junction is formed between the p-type impurity diffusion region 21 and the n-type source region 18, and a diode 22 is formed by the pn junction.

The diode 22 includes a p-type impurity diffusion region 21 and an n-type source region 18 including a portion having a relatively high impurity concentration (in this embodiment, a p ⁺ type high concentration portion 30 and an n ⁺ type high concentration portion 26 described later). It is formed by the pn junction of the above, and may be referred to as a Zener diode. For example, the breakdown voltage of the diode 22 may be 3V to 7V.
Further, the p-type impurity diffusion region 21 may face the n-type drain region 19 in the first direction X. That is, as shown in FIG. 3, the n-type drain region 19 includes a first portion 23 facing the n-type source region 18 in the first direction X and a second portion 24 not facing the n-type source region 18. The p-type impurity diffusion region 21 may face the second portion 24. The second portion 24 of the n-type drain region 19 is a portion protruding from the end portion of the n-type source region 18 (the boundary portion 25 between the n-type source region 18 and the p-type impurity diffusion region 21) in the second direction Y. May be.

The n-type source region 18 includes an n ⁺ type high concentration portion 26 having a relatively high impurity concentration and an n ⁻ type low concentration portion 27 having a lower impurity concentration than the n ⁺ type high concentration section 26. May be good. Similarly, the n-type drain region 19 includes an n ⁺ type high concentration portion 28 having a relatively high impurity concentration and an n ⁻ type low concentration portion 29 having a lower impurity concentration than the n ⁺ type high concentration section 28. It may be included. Further, the p-type impurity diffusion region 21 includes a p ⁺ type high concentration section 30 having a relatively high impurity concentration and a p ^- type low concentration section 31 having a lower impurity concentration than the p ⁺ type high concentration section 30. It may be included. In this specification, the notations of "n ⁺ type", "n type", "n ^- type", "p ⁺ type", "p-type" and "p ^- type" indicate the high and low impurities concentrations of each other. It is attached only to distinguish the relationship, and each notation does not indicate the impurity concentration in a specific range.

For example, the impurity concentration of the n ⁺ type high concentration portions 26 and 28 may be 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 , and the impurity concentration of the n ⁻ type low concentration portions 27 and 29 may be. It may be 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 . Further, for example, the impurity concentration of the p ⁺ type high concentration portion 30 may be 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 , and the impurity concentration of the p ⁻ type low concentration portion 31 may be 1. It may be × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 . The n ^- type low concentration portions 27 and 29 and the p ^- type low concentration portion 31 may be referred to as an n ^- type LDD (Lightly Doped Drain) region and a p ^- type LDD region, respectively.

The n ^- type low concentration portion 27 of the n-type source region 18 is formed on the side closer to the n-type drain region 19 than the n ⁺ type high concentration portion 26 in the first direction X. The n ^- type low concentration portion 29 of the n-type drain region 19 is formed on the side closer to the n-type source region 18 than the n ⁺ type high concentration portion 28 in the first direction X.
The p ^- type low concentration portion 31 of the p-type impurity diffusion region 21 is formed on the side closer to the n-type drain region 19 than the p ⁺ type high concentration portion 30 in the first direction X. Further, as shown in FIG. 3, the p ^- type low concentration portion 31 may be formed continuously with the n ^- type low concentration portion 27 in the second direction Y. For example, the p ^- type low concentration portion 31 and the n ^- type low concentration portion 27 may have a line shape extending along the second direction Y as a whole.

Here, variations of the junction between the n-type source region 18 and the p-type impurity diffusion region 21 will be described. As described above, the n-type source region 18 and the p-type impurity diffusion region 21 are adjacent to each other and form a diode 22. The diode 22 may be formed, for example, by joining the p ⁺ type high concentration portion 30 and the n ⁺ type high concentration portion 26 as shown in FIG. In this case, the p ^- type low concentration portion 31 and the n ^- type low concentration portion 27 may not be formed at least at the boundary portion 25 between the n-type source region 18 and the p-type impurity diffusion region 21.

On the other hand, the diode 22 may be formed by joining the p ^- type low concentration portion 31 and the n ^- type low concentration portion 27, for example, as shown in FIGS. 7A and 7B. That is, unlike the case of FIG. 6, the p ^- type low concentration portion 31 and the n ^- type low concentration portion 27 are formed at least at the boundary portion 25 between the n-type source region 18 and the p-type impurity diffusion region 21. May be good. The bonding between the p ^- type low-concentration portion 31 and the n ^- type low-concentration portion 27 is, for example, as shown in FIG. 7A, the contact between the tips of the p ^- type low-concentration portion 31 and the n ^- type low-concentration portion 27. It may be formed by overlapping the p ^- type low concentration portion 31 and the n ^- type low concentration portion 27 as shown in FIG. 7B.

As shown in FIG. 6, in the second active region 12 for a capacitor, an n-type well 32 as a control gate is formed with a capacitor structure facing the floating gate 38 via a gate insulating film 35 described later. There is.
As shown in FIG. 6, the n-type well 32 as an example of the second region of the present invention may be in contact with the first p-type well 17 of the first active region 11 below the element separation structure 10. The n-type well 32 has a higher impurity concentration than the epitaxial layer 9, for example, even if it has an impurity concentration of 1.0 × 10 ¹⁷ cm ^-3 to 1.0 × 10 ¹⁹ cm ^-3 . good. The n-type well 32 functions as a control gate in this embodiment.

A second p-type well 33 is formed in the third active region 13 for contacts. As shown in FIG. 6, the second p-type well 33 may be integrally connected to the first p-type well 17 of the first active region 11 below the element separation structure 10. The second p-type well 33 has a higher impurity concentration than the epitaxial layer 9, for example, 1.0 × 10 ¹⁷ cm ^-3 to 1.0 × 10 ¹⁹ cm ^-3 . May be good.

A p ⁺ type contact region 34 is formed on the surface of the second p-type well 33. The impurity concentration of the p ⁺ type contact region 34 may be the same as the impurity concentration of the p ⁺ type high concentration portion 26, for example. Specifically, the impurity concentration of the p ⁺ type contact region 34 may be 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 .
A gate insulating film 35 is formed on the epitaxial layer 9. The gate insulating film 35 covers the channel region 20 of the first active region 11 and covers the n-type well 32 of the second active region 12. In this embodiment, the gate insulating film 35 straddles the first active region 11 and the second active region 12 across the element separation structure 10 as shown in FIG. That is, the gate insulating film 35 is an example of the first portion 36 of the present invention covering the first active region 11 and the second insulating film of the present invention covering the second active region 12. A second portion 37 is included, and these are formed in succession. On the other hand, as another form, the first portion 36 and the second portion 37 of the gate insulating film 35 may be separated with the element separation structure 10 as a boundary.

In this embodiment, the gate insulating film 35 is made of silicon oxide (SiO ₂ ), but may be made of another insulating material (for example, silicon nitride oxide film (SiON) or the like). Further, the thickness of the gate insulating film 35 may be, for example, 7 nm to 15 nm.
A floating gate 38 is formed on the gate insulating film 35. The floating gate 38 may be, for example, polysilicon to which impurities have been added. In this embodiment, the floating gate 38 may integrally include a first portion 39 formed on the first active region 11 and a second portion 40 formed on the second active region 12. .. The first portion 39 of the floating gate 38 faces the channel region 20 via the first portion 36 of the gate insulating film 35. The second portion 40 of the floating gate 38 faces the n-type well 32 (control gate) via the second portion 37 of the gate insulating film 35.

With reference to FIG. 3, the second portion 40 of the floating gate 38 is formed in a solid pattern covering the n-shaped well 32, and in this embodiment, it has a rectangular shape in a plan view. Here, "formed by a solid pattern" may mean that the n-type well 32 covers the entire region other than the region that should be avoided in order to exert the function of the n-type well 32. .. For example, in this embodiment, the n-type well 32 functions as a control gate when a voltage is applied, so that the contact region 53 (described later) to which the third contact 51 for applying the voltage is connected is. It may be the area to be avoided. Further, the second portion 40 of the floating gate 38 may have a portion 41 drawn outward from both ends of the second active region 12 in the second direction Y.

On the other hand, the first portion 39 of the floating gate 38 is formed by a line pattern extending from the second portion 40 of the floating gate 38. Therefore, the second portion 40 of the floating gate 38 has a width W ₂ larger than the width W ₁ of the first portion 39 in the first direction X. In this embodiment, the first portion 39 of the floating gate 38 crosses the boundary 42 between the first p-type well 17 and the n-type well 32. Further, as shown in FIG. 6, the first portion 39 of the floating gate 38 overlaps with the pn junction (diode 22) which is the boundary portion 25 between the n-type source region 18 and the p-type impurity diffusion region 21. There is. Further, as shown in FIG. 6, the end portion of the first portion 39 of the floating gate 38 overlaps with the element separation structure 10.

A sidewall 45 is formed on the side surface of the floating gate 38 via the first insulating film 43 and the second insulating film 44. The first insulating film 43 covers the side surface of the floating gate 38, and the second insulating film 44 having an L-shaped cross section covers the gate insulating film 35 and the first insulating film 43 so as to cover the first insulating film 43. Is formed in. The sidewall 45 is formed on the second insulating film 44.

In this embodiment, the first insulating film 43 and the sidewall 45 are made of silicon oxide (SiO ₂ ), but are made of another insulating material (for example, silicon nitride oxide film (SiON)). May be good. On the other hand, the second insulating film 44 is made of silicon nitride (SiN) in this embodiment, but is made of another insulating material (for example, silicon oxide (SiO ₂ ), silicon nitride oxide film (SiON), etc.). It may be configured.

A third insulating film 46 is formed on the epitaxial layer 9. In this embodiment, the third insulating film 46 is made of silicon oxide (SiO ₂ ), but may be made of another insulating material (for example, silicon nitride oxide film (SiON) or the like). The third insulating film 46 covers the floating gate 38 and selectively covers the first active region 11, the second active region 12, and the third active region 13. As shown in FIG. 6, the end portion of the third insulating film 46 is in contact with the insulator 15 of the element separation structure 10.

With reference to FIGS. 4 and 5, the n-type source region 18 and the n-type drain region 19 are each partially exposed from the third insulating film 46, respectively. Also, referring to FIG. 6, the p ⁺ type contact region 34 is partially exposed from the third insulating film 46. Each portion of the n-type source region 18, the n-type drain region 19 and the p ⁺ type contact region 34 exposed from the third insulating film 46 is a silicide 47.

On the other hand, at least the boundary portion 25 between the n-type source region 18 and the p-type impurity diffusion region 21 and the entire p-type impurity diffusion region 21 are covered with the third insulating film 46. The third insulating film 46 may be referred to as a silicide block film. That is, the third insulating film 46 prevents conduction between the n-type source region 18 and the p-type impurity diffusion region 21 via the silicide 47 formed by silicidization of the surface portion of the epitaxial layer 9. ..

An interlayer insulating film 48 is formed on the epitaxial layer 9 so as to cover the third insulating film 46. In this embodiment, the interlayer insulating film 48 is made of silicon oxide (SiO ₂ ), but may be made of another insulating material (for example, silicon nitride oxide film (SiON) or the like).
The interlayer insulating film 48 is formed with a first contact 49, a second contact 50, a third contact 51, and a fourth contact 52. The first to fourth contacts 49 to 52 may be embedded in the contact holes formed in the interlayer insulating film 48, respectively. Only one of the first to fourth contacts 49 to 52 may be formed, or a plurality of the first to fourth contacts may be formed. The first to fourth contacts 49 to 52 are made of tungsten (W) in this embodiment, but may be made of another conductive material (for example, aluminum (Al) or the like).

The first contact 49 is connected to the n-type source region 18 (silicide 47), and the second contact 50 is connected to the n-type drain region 19 (silicide 47). The third contact 51 is connected to the n-type well 32. With reference to FIG. 3, the third contact 51 may be connected to the contact region 53 of the n-type well 32 drawn from the floating gate 38 in plan view. In this embodiment, the contact regions 53 are formed on both sides of the floating gate 38 in the first direction X, and the third contact 51 is connected to each contact region 53. By making contact on both sides of the floating gate 38, a voltage can be uniformly applied to the n-type well 32 that functions as a control gate.

The fourth contact 52 is connected to the p ⁺ type contact region 34. Although no contact is connected to the p-type impurity diffusion region 21, the potential of the p-type impurity diffusion region 21 is supplied via the fourth contact 52, the second p-type well 33, and the first p-type well 17.
Further, the first to fourth contacts 49 to 52 may be electrically connected to the wiring 6 at positions (not shown).
[Operation of memory cell 4 and operation and effect of semiconductor device 1]
Next, the operation of the memory cell 4 will be described in detail with reference to FIGS. 8 and 9.

In writing the memory in each cell unit 7, for example, the potential of the n-type drain region 19 is open (Vd = Open) as shown in FIG. 8, or the ground potential is set as shown in FIG. 9 (Vd). = 0V), a voltage Vg is applied to the n-type well 32 which is a control gate, and a voltage Vs is applied to the n-type source region 18. In this embodiment, for example, Vg = 5V and Vs = 5V may be used. As a result, electrons are induced in the vicinity of the floating gate 38 (channel region 20) to form a channel, and the MOSFET 16 in the first active region 11 is turned on. Then, the hot carriers (electrons) generated at this time are injected into the floating gate 38.

On the other hand, in this semiconductor device 1, a p-type impurity diffusion region 21 is formed in the first active region 11, and a diode 22 (Zener diode) is formed between the p-type impurity diffusion region 21 and the n-type source region 18. It is formed. Therefore, for example, if the potential of the p-type impurity diffusion region 21 (potential of the first p-type well 17) is set as the ground potential, a reverse voltage is applied to the diode 22 when a potential difference is applied between the source and the drain. Will be done. This reverse voltage allows the diode 22 to yield avalanche (band to band) and generate hot carriers.

Therefore, in addition to the hot carriers generated when a channel is formed in the channel region 20 and a current is passed, the hot carriers generated by avalanche breakdown of the diode 22 can be injected into the floating gate 38. As a result, the number of hot carriers can be increased, so that the hot carrier injection efficiency can be improved. Therefore, the write efficiency of the memory can be improved.

As shown in FIG. 8, it is preferable to yield the diode 22 avalanche in a state where the potential of the n-type drain region 19 is open (Vd = Open). When the potential of the n-type drain region 19 is open, it is possible to prevent hot carriers generated by interband tunneling from escaping to the drain side, unlike the case of FIG. 9.
Further, in this embodiment, since the first p-type well 17 and the p-type impurity diffusion region 21 are independent of each other, the respective impurity concentrations can be designed separately. For example, the impurity concentration of the p-type impurity diffusion region 21 is designed to be relatively high in order to match the target breakdown voltage of the diode 22, while the impurity concentration of the first p-type well 17 is relative to the p-type impurity diffusion region 21. It may be designed to be low. That is, the impurity concentration of the first p-type well 17 can be independently designed regardless of the target value (design value) of the breakdown voltage of the diode 22.

Thereby, for example, by making the impurity concentration of the first p-type well 17 relatively low, it is possible to increase the number of minority carriers (electrons in this embodiment) in the first p-type well 17. As a result, even if the voltage applied to the floating gate 38 is low, electrons can be easily induced in the channel region 20 to form a channel. Therefore, the threshold voltage at the time of the read operation in the initial state of the memory can be lowered.

Further, for example, when an element other than the memory (for example, an element constituting the logic circuit 5) is mixedly mounted on the epitaxial layer 9, the first p-type well 17 is matched with the design of the impurity region of the other element. It is also possible to adjust the impurity concentration of.
Although the embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.

For example, a configuration in which the conductive type of each semiconductor portion of the semiconductor device 1 is inverted may be adopted. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.
Further, in the above-described embodiment, one floating gate 38 faces one n-type well 32 (control gate) on a one-to-one basis, but as shown in FIG. 10, one n-type well 32 A plurality of independent floating gates 38 may face each other (hatched area). That is, the n-type well 32 (control gate) is formed across the plurality of cell units 7, and may be shared by the plurality of cell units 7. In FIG. 10, for the sake of clarity, among the reference numerals shown in FIG. 3, reference numerals that are not particularly necessary for the explanation of FIG. 10 are omitted.

Further, the p-type impurity diffusion region 21 may be selectively formed in one of the n-type source region 18 and the n-type drain region 19, and for example, unlike the above-described embodiment, the n-type drain region 19 may be formed. It may be formed adjacent to each other. That is, the n-type drain region 19 may be an example of the first impurity diffusion region of the present invention, and the n-type source region 18 may be an example of the second impurity diffusion region of the present invention.

Further, in the above-described embodiment, the n-type well 32, which is a part of the epitaxial layer 9 (semiconductor layer), is used as a control gate. For example, the control gate is placed on the floating gate 38 via an insulating film. It may be a conductive layer laminated with each other. For example, it may be a conductive layer such as polysilicon laminated on the floating gate 38.

In addition, various design changes can be made within the scope of the matters described in the claims.

1: Semiconductor device 9: epitaxial layer 10: element separation structure 11: first active region 12: second active region 17: first p-type well 18: n-type source region 19: n-type drain region 20: channel region 21: p Type impurity diffusion region 22: Diode 26: n ⁺ type high concentration part 27: n ^- type low concentration part 30: p ⁺ type high concentration part 31: p ^- type low concentration part 32: n type well 35: Gate insulating film 36: (Gate insulating film) 1st part 37: (Gate insulating film) 2nd part 38: Floating gate 39: (Floating gate) 1st part 40: (Floating gate) 2nd part W ₁ : (Floating gate first 1 part) Width W ₂ : (2nd part of floating gate) Width

Claims (13)

With the semiconductor layer,
The first region of the first conductive type formed on the semiconductor layer and
A second conductive type first impurity diffusion region and a second impurity diffusion region formed in the first region and separated from each other,
A floating gate facing the channel region between the first impurity diffusion region and the second impurity diffusion region in the first region via the first insulating film.
A control gate facing the floating gate via a second insulating film,
A pn junction portion formed adjacent to the first impurity diffusion region in the first region, has a higher first conductive type impurity concentration than the first region, and is connected to the first impurity diffusion region. A semiconductor device including a third impurity diffusion region forming the above. The control gate includes a second region of the second conductive type formed on the semiconductor layer.
The semiconductor device according to claim 1, wherein the floating gate is formed so as to straddle the first region and the second region, and faces the second region via the second insulating film. A device separation structure for separating the semiconductor layer into a first active region and a second active region is included.
The first region includes a first well formed in the first active region.
The semiconductor device according to claim 2, wherein the second region includes a second well formed in the second active region. 3. The floating gate includes a first portion formed on the first active region and a second portion formed on the second active region and having a width larger than that of the first portion. The semiconductor device described in. The second portion is formed of a solid pattern covering the second active region.
The semiconductor device according to claim 4, wherein the first portion is formed of a line pattern extending from the second portion of the solid pattern. The semiconductor device according to any one of claims 2 to 5, wherein the second insulating film is formed in succession with the first insulating film. The semiconductor device according to any one of claims 2 to 6, wherein the plurality of independent floating gates face the second region. The semiconductor device according to any one of claims 1 to 7, wherein the pn junction forms a Zener diode. The first impurity diffusion region includes a first high concentration portion having an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 .
The third impurity diffusion region includes a second high-concentration portion having an impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 , which is a higher impurity concentration than the first region. The semiconductor device described in 1. The semiconductor device according to claim 9, wherein the Zener diode includes a pn junction formed by a junction between the first high-concentration portion and the second high-concentration portion. The first impurity diffusion region further includes a first low concentration portion having a lower impurity concentration than the first high concentration portion.
The third impurity diffusion region further includes the second high concentration portion and the second low concentration portion having an impurity concentration lower than that of the first region.
The semiconductor device according to claim 9, wherein the Zener diode includes a pn junction formed by a junction between the first low concentration portion and the second low concentration portion. The first low concentration portion has an impurity concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 .
The semiconductor device according to claim 11, wherein the second low-concentration portion has an impurity concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁸ cm ^-3 . The semiconductor device according to any one of claims 1 to 12, wherein the first region has an impurity concentration of 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 .

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