JP2022099547A - Frequency synchronization circuit - Google Patents

Abstract

To perform frequency synchronization without using an integrated circuit for PLL control.SOLUTION: A frequency synchronization circuit includes an orthogonal demodulation unit 103 that performs digital orthogonal demodulation processing, which is configured in an FPGA 100, and an NCO unit 102 that supplies an oscillation signal used in the digital orthogonal demodulation processing to the orthogonal demodulation unit 103, and a frequency error Δf between the frequency of the signal to be digitally orthogonal demodulated and the oscillation frequency of the NCO unit 102 is detected, and the operating clock of the FPGA 100 is controlled on the basis of the frequency error Δf.SELECTED DRAWING: Figure 1

Description

The present invention relates to a frequency synchronization circuit, for example, a technique suitable for application as a frequency synchronization mechanism in a wireless communication device.

In a receiver that orthogonally demolishes a received signal in the carrier frequency band to generate a baseband received signal in the base band, the carrier frequency of the received signal and the carrier frequency used for orthogonal demodulation (in other words, the local oscillation frequency) If there is a frequency error between them, the transmitted data may be erroneously reproduced. Therefore, such a receiver usually has a carrier frequency synchronization function as a function of detecting a frequency error and correcting the error. In carrier frequency synchronization, in order to match the communication frequencies between the transmitting side and the receiving side, the receiving side detects a frequency error and controls the local oscillation frequency so as to reduce this error. As such a technique, for example, on the transmitting side, one or more types of unmodulated carrier signals having different frequencies are repeatedly repeated at a predetermined position in a synchronization signal section of an OFDM (Orthogonal Frequency Division Multiplexing) signal. There is a known method of inserting in a pattern and transmitting intermittently, locking to the frequency of the highest level unmodulated carrier signal among the unmodulated carrier signals on the receiving side, and reproducing the reference carrier frequency signal for OFDM signal demodulation. (Patent Document 1).

Japanese Unexamined Patent Publication No. 10-605644

By the way, if an integrated circuit (IC: an abbreviation for Integrated Circuit) for controlling a PLL (Phase Locked Loop) control is used to configure a circuit for carrier frequency synchronization, the number of parts increases. There is.

Therefore, an object of the present invention is to provide a frequency synchronization circuit capable of performing frequency synchronization without using an integrated circuit for PLL control.

In order to solve the above problems, the invention according to claim 1 has a quadrature demodulator that is configured in the FPGA and performs digital quadrature demodulation processing, and an oscillating signal used in the digital quadrature demographic processing. It has an NCO unit to supply to, detects a frequency error between the frequency of the signal subject to the digital orthogonal demodulation process and the oscillation frequency of the NCO unit, and detects the frequency error of the FPGA based on the frequency error. It is a frequency synchronization circuit characterized in that the operating clock is controlled.

The invention according to claim 2 is the integral of 0 to T for each of the real part and the imaginary part after the digital orthogonal demographic processing, which are configured in the FPGA in the frequency synchronization circuit according to claim 1. The division unit that performs complex division processing by dividing the integration result of time T by the integration result of integration time T of T to 2T for each of the real part and the imaginary part after the digital orthogonal demodulation processing, and the complex division processing. It is characterized by having a frequency error calculation unit that calculates the phase rotation angle by performing an inverse tangential function calculation using the latter real part and the imaginary part and also calculates the frequency error using the phase rotation angle. And.

According to the third aspect of the present invention, in the frequency synchronization circuit according to the first aspect, the real part and the imaginary part after the digital quadrature demodulation process at the time t ₁ configured in the FPGA are the same as the real part and the imaginary part at the time t ₂ . A division unit that performs complex division processing by dividing by the real part and imaginary part after digital orthogonal demodulation processing (however, if the sampling period of the signal targeted for digital orthogonal demodulation processing is Δt, t ₂ = t ₁ + Δt). , A frequency error calculation unit that calculates the phase rotation angle by performing an inverse tangential function operation using the real part and the imaginary part after the complex division process, and calculates the frequency error using the phase rotation angle. It is characterized by having.

The invention according to claim 4 performs an inverse tangential function operation using the real part and the imaginary part after the digital orthogonal demodulation process configured in the FPGA in the frequency synchronization circuit according to claim 1. Inverse tangential calculation unit and the integration result of integration time T of -T to 0 for the result of the inverse tangential function operation are subtracted from the integration result of integration time T of 0 to T for the result of the inverse tangential function operation. It is characterized by having an integral calculation unit for calculating an integral difference and a frequency error calculation unit for calculating the frequency error using the integral difference.

The invention according to claim 5 performs an inverse tangential function operation using the real part and the imaginary part after the digital orthogonal demodulation process configured in the FPGA in the frequency synchronization circuit according to claim 1. An inverse tangential unit and a differential calculation unit that calculates the time difference by subtracting the result of the inverse tangential function operation at time t ₁ from the result of the inverse tangential function operation at time t ₂ (provided that the digital orthogonal demodulation process is performed). Letting Δt be the sampling period of the signal of interest, t ₂ = t ₁ + Δt), and a frequency error calculation unit for calculating the frequency error using the time difference.

The invention according to claim 6 is characterized in that, in the frequency synchronization circuit according to claims 1 to 5, the frequency of the signal to be digitally orthogonal demodulated is in the voice frequency band.

According to the inventions of claims 1 to 5, based on the frequency error between the frequency of the signal to be digitally orthogonal demodulated in the orthogonal demodulation unit configured in the FPGA and the oscillation frequency of the NCO unit. Since the operating clock of the FPGA is controlled, frequency synchronization can be performed without using an integrated circuit for PLL control.

According to the inventions of claim 2 and claim 4, since the integration is used for detecting the frequency error, the influence of the instantaneous fluctuation can be averaged as compared with the method using the differentiation. , It becomes possible to appropriately detect the frequency error, and by extension, it becomes possible to perform frequency synchronization with higher accuracy.

According to the sixth aspect of the present invention, it is possible to exert the above-mentioned effects in the communication of signals in the voice frequency band.

It is a functional block diagram which shows the schematic structure of the frequency synchronization circuit which concerns on Embodiment 1 of this invention. It is a functional block diagram which shows the schematic structure of the frequency synchronization circuit which concerns on Embodiment 2 of this invention. It is a functional block diagram which shows the schematic structure of the frequency synchronization circuit which concerns on Embodiment 3 of this invention. It is a functional block diagram which shows the schematic structure of the frequency synchronization circuit which concerns on Embodiment 4 of this invention.

Hereinafter, the present invention will be described based on the illustrated embodiment. In the following, the characteristic configuration of the present invention related to frequency synchronization will be described, and the description of the same mechanism as the conventional one when performing wireless communication will be omitted.

In addition, the meaning of each symbol / variable in each of the following formulas is as follows.
A: Amplitude of input signal (in other words, received signal) f: Reference frequency [kHz]
Δf: Frequency error [kHz]
θ: Phase difference [rad]
t: time (sampling time)
j: Imaginary unit

The reference frequency f (that is, the frequency of the input signal (received signal); in other words, the carrier frequency used for transmitting the radio signal in the radio communication device on the transmitting side) is not limited to a specific frequency band. However, for example, an appropriate frequency band is appropriately set and selected after considering the frequency band corresponding to each of various communication standards. The reference frequency f may be set, for example, in the voice frequency band, specifically, in a frequency band of, for example, about 3 kHz (in this case, the reference frequency f = 3 [kHz]). The reference frequency f is preferably set and selected with an upper limit of about one-fourth of the maximum sampling frequency that the FPGA 100 can handle.

The frequency synchronization circuit 1 according to the embodiment is configured in the FPGA 100, the orthogonal demodulation unit 103 that performs digital orthogonal demodulation processing, and the NCO unit that supplies the oscillation signal used in the digital orthogonal demodulation processing to the orthogonal demographic unit 103. 102, the frequency error Δf between the frequency of the signal to be digitally orthogonally demodulated and the oscillation frequency of the NCO unit 102 is detected, and the operating clock of the FPGA 100 is controlled based on the frequency error Δf. , And so on.

Then, the frequency synchronization circuit 1 according to the present invention can be realized by the configuration as in the following embodiments 1 to 4.

(Embodiment 1)
FIG. 1 is a functional block diagram showing a schematic configuration of a frequency synchronization circuit 1 according to the first embodiment of the present invention. This frequency synchronization circuit 1 synchronizes the frequency of the receiving side with the frequency of the input signal, in other words, the communication frequency of the receiving side (in other words, the demodulated carrier frequency) is the communication frequency of the transmitting side (in other words, in other words). It is a signal processing circuit that controls the frequency in synchronization with the modulated carrier frequency). The frequency synchronization circuit 1 is mounted on, for example, a wireless communication device on a receiving side that performs wireless communication with a wireless communication device on the transmitting side and receives a wireless signal. A wireless signal generated by performing quadrature modulation processing is transmitted from the wireless communication device on the transmitting side.

The frequency synchronization circuit 1 uses an FPGA (abbreviation of Field Programmable Gate Array) 100, that is, is configured in the FPGA 100 and mounted on a wireless communication device on the receiving side.

An oscillation circuit 200 including an oscillator 201 that generates a reference clock (in other words, an original clock) is connected to the FPGA 100 as a clock circuit that supplies a clock for operating the FPGA 100 to the FPGA 100. The frequency of the reference clock (original clock) generated by the oscillator 201 is configured to be variable by adjusting the control voltage Vc.

The oscillator 201 is composed of a voltage controlled oscillator (VCO: Voltage Controlled Oscillator) whose frequency is controlled by an analog voltage (that is, an analog controlled voltage Vc), although not limited to a specific type, for example, a voltage controlled temperature. It is preferably configured by a voltage controlled temperature compensated crystal oscillator (VCTCXO).

The frequency synchronization circuit 1 according to the first embodiment digitally quadrature demodulates the integration result of the integration time T of 0 to T for each of the real part and the imaginary part after the digital quadrature demodulation process, which is configured in the FPGA 100. Using the division unit 108 that performs the complex division process by dividing by the integration result of the integration time T of T to 2T for each of the subsequent real part and the imaginary part, and the real part and the imaginary part after the complex division process. It has a frequency error calculation unit 110 that calculates the phase rotation angle Z by performing an inverse tangential function calculation and also calculates the frequency error Δf using the phase rotation angle Z.

The receiving-side wireless communication device on which the frequency synchronization circuit 1 is mounted receives a wireless signal transmitted from the transmitting-side wireless communication device via an antenna (not shown). Predetermined processing (for example, band limiting processing, amplification processing, frequency conversion processing) is performed from the radio signal as necessary to generate an analog received signal. The frequency of this analog received signal is the reference frequency f.

The A / D converter 101 (ADC: an abbreviation for Analog to Digital Converter) is arranged outside the FPGA 100, converts the above analog received signal into a digital received signal, and outputs the signal. The signal output from the A / D converter 101 is input to the orthogonal demodulation unit 103 of the frequency synchronization circuit 1 configured in the FPGA 100. The signal d (t) output from the A / D converter 101 is expressed by the following mathematical formula 1.

The signal d (t) output from the A / D converter 101 is adjusted in gain by automatic gain control (AGC: abbreviation for Automatic Gain Control) as necessary so that the amplitude A is normalized. May be good. It is assumed that the signal d _A (t) in which the amplitude A is normalized is expressed by the following equation 2 and the signal d _A (t) expressed by the following equation 2 is used in the following description.

The NCO unit 102 functions as a numerically controlled oscillator (NCO: an abbreviation for Numerically Controlled Oscillator), and generates and outputs an oscillation signal having an oscillation frequency matched to the reference frequency f.

Here, if there is a frequency error between the reference frequency f, which is the frequency of the analog received signal input to the frequency synchronization circuit 1, and the oscillation frequency of the NCO unit 102, the transmission data may be erroneously reproduced. Therefore, it is desirable that the reference frequency f and the oscillation frequency match in order to reproduce the transmitted data without error. However, the reference frequency f and the oscillation frequency of the NCO unit 102 do not always match, and there may be a frequency error between the reference frequency f and the oscillation frequency.

Therefore, in the present invention, the oscillation frequency of the NCO unit 102 is made to follow the reference frequency f so that the frequency error between the reference frequency f and the oscillation frequency is reduced to the minimum (preferably zero). , The frequency of the reference clock generated by the oscillator 201 of the oscillation circuit 200 connected to the FPGA 100 to which the frequency synchronization circuit 1 is configured is variably controlled. That is, the frequency of the reference clock generated by the oscillator 201 is variably controlled by adjusting the control voltage Vc of the oscillator 201 that generates the reference clock, whereby the frequency of the operating clock of the FPGA 100 is controlled by the NCO unit 102. The oscillation frequency is controlled to reduce the frequency error between the reference frequency f and the oscillation frequency to the minimum and preferably zero.

Assuming that the frequency error between the reference frequency f and the oscillation frequency of the NCO unit 102 is Δf, the oscillation frequency of the NCO unit 102 becomes “f + Δf” and the frequency of the oscillation signal generated by the NCO unit 102 becomes “f + Δf”. , The oscillation signal s (t) output from the NCO unit 102 is expressed by the following equation 3.

The oscillation signal s (t) output from the NCO unit 102 is frequency-converted (specifically, down-converted) so as to match the sampling rate of the A / D converter 101, if necessary. You may.

The orthogonal demodulation unit 103 receives an input of a digital reception signal output from the A / D converter 101 (here, a signal d _A (t) in which the amplitude A is normalized; see the above equation 2), and also receives an NCO. The oscillation signal s (t) output from the unit 102 is supplied (see the above equation 3), and the digital received signal d _A (t) is subjected to digital orthogonal demodulation processing using the oscillation signal s (t). Is applied, and the received signal after the orthogonal demodulation processing is output.

The received signal after the orthogonal demodulation process is a complex signal composed of an I signal of an in-phase component in orthogonal demodulation and a Q signal of a quadrature component in orthogonal demodulation. When a complex number represented by a complex signal is expressed as "I + jQ" (where j is an imaginary unit), the in-phase component is a signal representing the real part I of the complex number, and the orthogonal component is a signal representing the imaginary part Q of the complex number. Is

The signal y (t) after the digital orthogonal demodulation process output from the orthogonal demodulation unit 103 is expressed by the following mathematical formula 4.

The first real part extraction unit 104 _R extracts the real part from the signal y (t) after the digital orthogonal demodulation process by the orthogonal demodulation unit 103 and outputs the real part. Further, the first imaginary part extraction unit 104 _I extracts an imaginary part from the signal y (t) after the digital orthogonal demodulation process by the orthogonal demodulation unit 103 and outputs the imaginary part. The digital orthogonal demodulation process is performed by numerical calculation, and is executed by extracting the real part and the imaginary part, respectively.

The real part LPF part 105 _R and the imaginary part LPF part 105 _I each function as a low-pass filter (LPF: an abbreviation for Low Pass Filter), and the real part LPF part 105 _R is output from the first real part extraction unit 104 _R. Regarding the real part of the signal y (t) after the orthogonal demodulation process, and the imaginary part LPF part 105 _I is the signal y (t) after the orthogonal demodulation process output from the first imaginary part extraction unit 104 _I. For each of the imaginary parts, the double wave generated by the orthogonal demodulation process is removed, and the DC component is extracted and output.

Specifically, the component of the second term of the molecule on the right side of the above formula 4 is removed by the real part LPF part 105 _R and the imaginary part LPF part 105 _I , and the real part LPF part 105 _R and the imaginary part LPF part 105 _I The signal LPF (y (t)) output from is expressed by the following mathematical formula 5.

The real part integrating unit 106 _R is for the signal output from the real part LPF part 105 _R , and the imaginary part integrating unit 106 _I is for the signal output from the imaginary part LPF part 105 _I , respectively, with the integration time T [seconds]. Is integrated (in other words, integrated over the integration time T [seconds]), and the result of the integration process is output every T seconds. The integration time T is not limited to a specific time length, and may be set to any time length in the range of, for example, about 0.50 to 0.85 [seconds].

The real part delay part 107 _R receives the signal output from the real part integrating part 106 _R , and the imaginary part delay part 107 _I receives the signal output from the imaginary part integrating part 106 _I , respectively, with an integration time T [seconds]. Output with a delay.

The division unit 108 receives inputs of signals output from each of the real part integration unit 106 _R and the imaginary part integration unit 106 _I , and the real part delay unit 107 _R and the imaginary part delay unit 107 _I. At this time, the real part delay unit 107 _R and the imaginary part delay unit 107 _I delay the signals output from the real part integration unit 106 _R and the imaginary part integration unit 106 _I by the integration time T [seconds] and output them. As a result, the division unit 108 receives the input of the integration result of the integration time T from T to 2T from the real part integration unit 106 _R and the imaginary part integration unit 106 _I , and also receives the real part delay unit 107 _R and the imaginary part delay unit 107. Receives the input of the integration result of the integration time T from 0 to T from _I.

The division unit 108 outputs the integration result of the integration time T from 0 to T output from the real part delay unit 107 _R and the imaginary part delay unit 107 _I from the real part integration unit 106 _R and the imaginary part integration unit 106 _I. Integral time T to 2T Divide by the integration result of T, perform complex division processing, and output the signal Y _d after complex division processing.

The second real part extraction unit 109 _R extracts the real part Re (Y _d ) from the signal Y _d after the complex division process by the division unit 108 and outputs it. Further, the second imaginary part extraction unit 109 _I extracts and outputs the imaginary part Im (Y _d ) from the signal Y _d after the complex division process by the division unit 108.

The frequency error calculation unit 110 is derived from the real part Re (Y _d ) of the signal Y _d after the complex division process output from the second real part extraction unit 109 _R and the second imaginary part extraction unit 109 _I. Phase by performing an inverse tangent function (that is, tan ^-1 ) operation as shown in Equation 6 below using the imaginary part Im (Y _d ) of the output signal Y _d after complex division processing. Calculate the value of the rotation angle Z.

Here, the indefinite integral of the signal LPF (y (t)) (see the above equation 5) output from the real part LPF unit 105 _R and the imaginary part LPF unit 105 _I is as shown in the following equation 7.

Based on the above formula 7, the definite integral of the integration time T of LPF (y (t)) from 0 to T is as shown in the following formula 8. That is, the signals output from the real part delay part 107 _R and the imaginary part delay part 107 _I are expressed by the following mathematical formula 8.

Further, the definite integral of the integration time T of LPF (y (t)) from T to 2T is as shown in Equation 9 below. That is, the signals output from the real part integrating unit 106 _R and the imaginary part integrating unit 106 _I are expressed by the following mathematical formula 9.

Based on the above equations 8 and 9, the signal Y _d after the complex division process output from the division unit 108 is expressed as the following equation 10.

Based on the above formula 10, the above formula 6 becomes the following formula 11A, so that the frequency error Δf becomes the following formula 11B.

The frequency error calculation unit 110 calculates and outputs the frequency error Δf according to the above equation 11B using the calculated value of the phase rotation angle Z (see the above equation 6).

The control voltage update unit 111 controls the frequency of the operating clock of the FPGA 100 including the NCO unit 102 so as to reduce the frequency error Δf output from the frequency error calculation unit 110 to the minimum and preferably to zero. A control voltage Vc for variably controlling the frequency of the reference clock generated by the oscillator 201 of the oscillation circuit 200 connected to the FPGA 100 for controlling the oscillation frequency of the unit 102 is calculated.

Specifically, the control voltage update unit 111 receives the input of the frequency error Δf output from the frequency error calculation unit 110, and oscillates the frequency error Δf and the NCO unit 102 at the present time point (in other words, in the previous processing). Based on the frequency and the control voltage Vc of the oscillator 201, the control voltage Vc of the oscillator 201 of the oscillation circuit 200 for minimizing the frequency error Δf is calculated and output.

It should be noted that, for example, the fluctuation of the oscillation frequency of the NCO unit 102 with respect to the increase / decrease of the control voltage Vc of the oscillator 201, such as the relationship between the degree of increase / decrease of the control voltage Vc of the oscillator 201 and the degree of fluctuation of the frequency error Δf. The sensitivity of the variation of the frequency error Δf (eg, a function) may be used to calculate or specify the control voltage Vc.

The D / A converter 112 (DAC: Digital to Analog Converter) is arranged outside the FPGA 100 and has a control voltage Vc output from the control voltage updater 111 of the frequency synchronization circuit 1 configured in the FPGA 100. Upon receiving the input, the control voltage Vc, which is a digital signal, is converted into an analog signal and output.

The oscillator 201 of the oscillation circuit 200 receives the input of the control voltage Vc (which is an analog signal) output from the D / A converter 112, generates a reference clock of the frequency based on the control voltage Vc, and sends it to the FPGA 100. And supply.

The frequency of the operating clock of the FPGA 100 is controlled by the reference clock supplied from the oscillator 201, whereby the oscillation frequency of the NCO unit 102 configured in the FPGA 100 is controlled, and the reference frequency f and the oscillation frequency of the NCO unit 102 are used. The frequency error between is reduced and minimized, preferably zero.

According to the frequency synchronization circuit 1 according to the first embodiment, the frequency (that is, the reference frequency f) of the signal to be digitally orthogonally demodulated in the orthogonal demodizing unit 103 configured in the FPGA 100 and the oscillation frequency of the NCO unit 102. Since the operating clock of the FPGA 100 is controlled based on the frequency error Δf between the frequencies, frequency synchronization can be performed without using an integrated circuit for PLL control.

According to the frequency synchronization circuit 1 according to the first embodiment, the frequency error Δf is calculated at any time by the frequency error calculation unit 110, so that the frequency error Δf is generated every moment by the device alone. It will be possible to investigate.

According to the frequency synchronization circuit 1 according to the first embodiment, since the integral is used for the detection of the frequency error Δf, the influence of the instantaneous fluctuation is averaged as compared with the method using the derivative. Therefore, the frequency error Δf can be appropriately detected, and the frequency synchronization can be performed with higher accuracy.

(Embodiment 2)
FIG. 2 is a functional block diagram showing a schematic configuration of the frequency synchronization circuit 1 according to the second embodiment of the present invention. In the second embodiment, the A / D converter 101, the NCO unit 102, the orthogonal demodulation unit 103, the first real part extraction unit 104 _R and the first imaginary part extraction unit 104 _I , and the real part LPF unit 105 _R and Since the imaginary portion LPF portion 105 _I has the same configuration and processing as that of the first embodiment described above, the description thereof will be omitted by assigning the same reference numerals.

In the frequency synchronization circuit 1 according to the second embodiment, the real part and the imaginary part after the digital quadrature demodulation process at time t ₁ and the real part and the imaginary part after the digital quadrature demodulation process at time t ₂ are configured in the FPGA 100. The division unit 121 that performs the complex division process by dividing by (however, if the sampling period of the signal to be digitally orthogonally demodulated is Δt, t ₂ = t ₁ + Δt), the real part and the imaginary part after the complex division process. It has a frequency error calculation unit 123 that calculates the phase rotation angle Z by performing an inverse tangential function calculation using the above and also calculates the frequency error Δf using the phase rotation angle Z.

The division unit 121 receives the input of the signal LPF (y (t)) (see the above equation 5) output from each of the real part LPF unit 105 _R and the imaginary part LPF unit 105 _I , and receives the signal LPF (y (y (y)). For t)), the LPF (y (t ₁ )) at time (sampling time) t = “t ₁ ” is divided by the LPF (y (t ₂ )) at time (sampling time) t = “t ₂ ”. The complex division process is performed, and the signal Y _d after the complex division process is output. If the sampling period in the A / D converter 101 is Δt [sec], it is “t ₂ = t ₁ + Δt”, and if the sampling frequency in the A / D converter 101 is fs [Hz], “Δt = 1 /”. fs ".

The second real part extraction unit 122 _R extracts the real part Re (Y _d ) from the signal Y _d after the complex division process by the division unit 121 and outputs it. Further, the second imaginary part extraction unit 122 _I extracts and outputs the imaginary part Im (Y _d ) from the signal Y _d after the complex division process by the division unit 121.

The frequency error calculation unit 123 is derived from the real part Re (Y _d ) of the signal Y _d after the complex division process output from the second real part extraction unit 122 _R and the second imaginary part extraction unit 122 _I. Phase by performing an inverse tangent function (that is, tan ^-1 ) operation as shown in Equation 12 below using the imaginary part Im (Y _d ) of the output signal Y _d after complex division processing. Calculate the value of the rotation angle Z.

Here, with respect to the signal LPF (y (t)) (see the above equation 5) output from the real part LPF part 105 _R and the imaginary part LPF part 105 _I , the LPF at the time (sampling time) t = “t ₁ ”. (y (t ₁ )) is expressed by the following formula 13A, and the LPF (y (t ₂ )) at the time (sampling time) t = "t ₂ " is expressed by the following formula 13B.

Based on the above formula 13, the signal Y _d after the complex division process output from the division unit 121 is expressed as the following formula 14.

Based on the above formula 14, the above formula 12 becomes the following formula 15A, so that the frequency error Δf becomes the following formula 15B.

In addition, "t ₂ -t ₁ " in the formula 15 is a difference in time (sampling time) t used when calculating the signal Y _d (see the above formula 14) after the complex division process, and specifically. Is the sampling period [seconds] in the A / D converter 101. That is, assuming that the sampling period in the A / D converter 101 is Δt [seconds], “t ₂ −t ₁ = Δt”.

The frequency error calculation unit 123 calculates and outputs the frequency error Δf according to the above equation 15B using the calculated value of the phase rotation angle Z (see the above equation 12).

Since the configuration / processing of the control voltage updating unit 111 and subsequent units is the same configuration / processing as that of the first embodiment described above, the description thereof will be omitted by assigning the same reference numerals.

According to the frequency synchronization circuit 1 according to the second embodiment, the frequency (that is, the reference frequency f) of the signal to be digitally orthogonally demodulated in the orthogonal demodating unit 103 configured in the FPGA 100 and the oscillation frequency of the NCO unit 102. Since the operating clock of the FPGA 100 is controlled based on the frequency error Δf between the frequencies, frequency synchronization can be performed without using an integrated circuit for PLL control.

According to the frequency synchronization circuit 1 according to the second embodiment, the frequency error Δf is calculated at any time by the frequency error calculation unit 110, so that the frequency error Δf is generated every moment by the device alone. It will be possible to investigate.

(Embodiment 3)
FIG. 3 is a functional block diagram showing a schematic configuration of the frequency synchronization circuit 1 according to the third embodiment of the present invention. The A / D converter 101, the NCO unit 102, the orthogonal demodulation unit 103, the first real part extraction unit 104 _R and the first imaginary part extraction unit 104 _I , and the real part LPF unit 105 _R in the third embodiment. Since the imaginary portion LPF portion 105 _I has the same configuration and processing as that of the first embodiment described above, the description thereof will be omitted by assigning the same reference numerals.

The frequency synchronization circuit 1 according to the third embodiment has an inverse tangential function unit 131 that performs an inverse tangential function calculation using a real part and an imaginary part after digital orthogonal demodulation processing, and an inverse tangential function. Integral difference Δ∫y _atan (t) is calculated by subtracting the integral result of the integral time T of 0 to T for the result of the inverse tangential function operation from the integral result of the integral time T of −T to 0 for the result of the operation. It has an integral calculation unit 132 to be performed, and a frequency error calculation unit 133 to calculate the frequency error Δf using the integral difference Δ∫y _atan (t).

The inverse tangent calculation unit 131 includes the real part Re (LPF (y (t))) of the signal LPF (y (t)) (see the above equation 5) output from the real part LPF unit 105 _R and the imaginary part. It is shown in the following formula 16 using the imaginary part Im (LPF (y (t))) of the signal LPF (y (t)) (see the above formula 5) output from the part LPF part 105 _I. By performing the inverse trigonometric function (that is, tan ^-1 ) operation as described above, the value of _yatan (t) is calculated and output.

The integration calculation unit 132 receives the input of the value of _yatan (t) of the inverse trigonometric function calculation result output from the inverse tangent calculation unit 131, and the integration time T [seconds] is applied to the value of _yatan (t). Integrate is performed (in other words, integrated over the integration time T [seconds]), and the result of the integration process is retained every T seconds. The integration time T is not limited to a specific time length, and may be set to any time length in the range of, for example, about 0.50 to 0.85 [seconds].

Then, the integral calculation unit 132 determines from the integration result (integration result) of the integration time T of −T to 0 of the value of _yatan (t) of the inverse tangential function calculation result to the _yatan (t) of the inverse tangential function calculation result. The integration result (integration result) of the integration time T of the value 0 to T is subtracted, and the subtraction result is output as the integration difference Δ∫y _atan (t). That is, the integration calculation unit 132 subtracts the integration result (integration result) of the value of _{yatan (t) over the integration time T [seconds] in two consecutive integration periods, and the integration difference Δ∫y atan (} t). ) Is output.

Here, based on the above formula 5, the real part Re (LPF (y (t))) in the above formula 16 is expressed as the following formula 17A, and the imaginary part Im (LPF (y (t))). Is expressed as the following formula 17B.

Based on the above formula 17, the above formula 16 becomes the following formula 18.

The indefinite integral of the above formula 18 becomes the following formula 19.

Based on the above equation 19, the result of subtracting the definite integral of the integration time T from 0 to T of y _atan (t) from the definite integral of the integration time T at −T to 0 of _yatan (t) is as follows. Equation 20 becomes.

Based on the above formula 20, the integral difference Δ∫y _atan (t) output from the integral calculation unit 132 is expressed as the above formula 20, so “Δ∫y _atan (t) = 2πΔfT ² ”. Is true. Therefore, the frequency error Δf is “Δf = Δ∫y _atan (t) / 2πT ² ”.

Based on the above, the frequency error calculation unit 133 receives the input of the value of the integral difference Δ∫y _atan (t) output from the integral calculation unit 132, and uses the value of the integral difference Δ∫ y _atan (t). The frequency error Δf is calculated and output according to “Δf = Δ∫y _atan (t) / 2πT ² ”.

Since the configuration / processing of the control voltage updating unit 111 and subsequent units is the same configuration / processing as that of the first embodiment described above, the description thereof will be omitted by assigning the same reference numerals.

According to the frequency synchronization circuit 1 according to the third embodiment, the frequency (that is, the reference frequency f) of the signal to be digitally orthogonally demodulated in the orthogonal demodating unit 103 configured in the FPGA 100 and the oscillation frequency of the NCO unit 102. Since the operating clock of the FPGA 100 is controlled based on the frequency error Δf between the frequencies, frequency synchronization can be performed without using an integrated circuit for PLL control.

According to the frequency synchronization circuit 1 according to the third embodiment, the frequency error Δf is calculated at any time by the frequency error calculation unit 110, so that the frequency error Δf is generated every moment by the device alone. It will be possible to investigate.

According to the frequency synchronization circuit 1 according to the third embodiment, since the integral is used for the detection of the frequency error Δf, the influence of the instantaneous fluctuation is averaged as compared with the method using the derivative. Therefore, the frequency error Δf can be appropriately detected, and the frequency synchronization can be performed with higher accuracy.

(Embodiment 4)
FIG. 4 is a functional block diagram showing a schematic configuration of the frequency synchronization circuit 1 according to the fourth embodiment of the present invention. In the fourth embodiment, the A / D converter 101, the NCO unit 102, the orthogonal demodulation unit 103, the first real part extraction unit 104 _R and the first imaginary part extraction unit 104 _I , and the real part LPF unit 105 _R and Since the imaginary portion LPF portion 105 _I has the same configuration and processing as that of the first embodiment described above, the description thereof will be omitted by assigning the same reference numerals.

The frequency synchronization circuit 1 according to the fourth embodiment includes an inverse tangential calculation unit 141 that performs an inverse tangential function calculation using a real part and an imaginary part after digital orthogonal demodulation processing, which are configured in the FPGA 100, and a time t ₂ . The differential calculation unit 142 that calculates the time difference Δy _atan (t) by subtracting the result of the inverse tangential function operation at time t ₁ from the result of the inverse tangential function operation in Assuming that the period is Δt, it has t ₂ = t ₁ + Δt) and a frequency error calculation unit 143 that calculates the frequency error Δf using the time difference Δy _atan (t).

The inverse tangent calculation unit 141 includes the real part Re (LPF (y (t))) of the signal LPF (y (t)) (see the above equation 5) output from the real part LPF unit 105 _R and the imaginary part. It is shown in the following formula 21 using the imaginary part Im (LPF (y (t))) of the signal LPF (y (t)) (see the above formula 5) output from the part LPF part 105 _I. By performing the inverse trigonometric function (that is, tan ^-1 ) operation as described above, the value of _yatan (t) is calculated and output.

The differential calculation unit 142 receives the input of the value of _yatan (t) of the inverse trigonometric function calculation result output from the inverse tangent calculation unit 141, and the time (sampling time) t = for the value of _yatan (t). The value of _yatan (t ₁ ) at "t ₁ " and the value of _yatan (t ₂ ) at time (sampling time) t = "t ₂ " are retained. If the sampling period in the A / D converter 101 is Δt [sec], it is “t ₂ = t ₁ + Δt”, and if the sampling frequency in the A / D converter 101 is fs [Hz], “Δt = 1 /”. fs ".

Then, the differential calculation unit 142 has an inverse trigonometric function at time (sampling time) t = "t ₁ " from the value of _yatan (t ₂ ) of the inverse trigonometric function calculation result at time (sampling time) t = "t ₂ ". The value of _yatan (t ₁ ) of the calculation result is subtracted, and the subtraction result is output as the time difference Δy _atan (t ₂ ). That is, the differential calculation unit 142 subtracts the value of _{yatan (t) of the inverse tangent function calculation result output from the inverse tangent calculation unit 141 at two consecutive sampling times, and the time difference Δy atan (} t). Is output as.

Here, based on the above formula 5, the real part Re (LPF (y (t))) in the above formula 21 is expressed as the following formula 22A, and the imaginary part Im (LPF (y (t))). Is expressed as the following formula 22B.

Based on the above formula 22, the above formula 21 becomes the following formula 23.

When the above formula 23 is differentiated with respect to time t, the following formula 24 is obtained.

Based on the above equation 24, the time difference Δy _atan (t) output from the differential calculation unit 142 is expressed as in the above equation 24, so that “Δy _atan (t) = -2πΔf” holds. Therefore, the frequency error Δf is “Δf = −Δy _atan (t) / 2π”.

Based on the above, the frequency error calculation unit 143 receives the input of the value of the time difference Δy _atan (t) output from the differential calculation unit 142, and uses the value of the time difference Δy _atan (t) to “Δf = −”. The frequency error Δf is calculated and output according to “Δy _atan (t) / 2π”.

Since the configuration / processing of the control voltage updating unit 111 and subsequent units is the same configuration / processing as that of the first embodiment described above, the description thereof will be omitted by assigning the same reference numerals.

According to the frequency synchronization circuit 1 according to the fourth embodiment, the frequency (that is, the reference frequency f) of the signal to be digitally orthogonally demodulated in the orthogonal demodizing unit 103 configured in the FPGA 100 and the oscillation frequency of the NCO unit 102. Since the operating clock of the FPGA 100 is controlled based on the frequency error Δf between the frequencies, frequency synchronization can be performed without using an integrated circuit for PLL control.

According to the frequency synchronization circuit 1 according to the fourth embodiment, the frequency error Δf is calculated at any time by the frequency error calculation unit 110, so that the frequency error Δf is generated every moment by the device alone. It will be possible to investigate.

Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above-described embodiment, and even if there is a design change or the like within a range that does not deviate from the gist of the present invention. Included in the invention.

Specifically, in the above-described embodiment, the present invention is realized by the specific circuit configurations shown in FIGS. 1 to 4, but the specific circuit configuration for realizing the present invention is shown in the figure. The invention is not limited to the embodiments shown in FIGS. 1 to 4, and the present invention may be realized by other specific circuit configurations.

1 Frequency synchronization circuit 100 FPGA
101 A / D converter 102 NCO part 103 Orthogonal demodulation part 104 _R First real part extraction part 104 _I First imaginary part extraction part 105 _R Real part LPF part 105 _I Imaginary part LPF part 106 _R Real part integration part 106 _I imaginary part integration part 107 _R real part delay part 107 _I imaginary part delay part 108 division part 109 _R second real part extraction part 109 _I second imaginary part extraction part 110 frequency error calculation part 111 control voltage update part 112 D / A converter 121 Divider (Embodiment 2)
122 _R Second real part extraction part (Embodiment 2)
122 _I Second imaginary part extraction part (Embodiment 2)
123 Frequency error calculation unit (Embodiment 2)
131 Inverse tangent calculation unit (Embodiment 3)
132 Integral calculation unit 133 Frequency error calculation unit (Embodiment 3)
141 Inverse tangent calculation unit (Embodiment 4)
142 Differentiation calculation unit 143 Frequency error calculation unit (Embodiment 4)
200 Oscillator 201 Oscillator 201

Claims (6)

Constructed in FPGA,
An orthogonal demodulation unit that performs digital orthogonal demodulation processing,
It has an NCO unit that supplies an oscillation signal used in the digital orthogonal demodulation process to the orthogonal demodulation unit.
The frequency error between the frequency of the signal to be digitally orthogonal demodulated and the oscillation frequency of the NCO unit is detected.
The operating clock of the FPGA is controlled based on the frequency error.
A frequency synchronization circuit characterized by that. It is configured in the FPGA.
The integration result of the integration time T of 0 to T for each of the real part and the imaginary part after the digital orthogonal demographic processing is integrated with T to 2T for each of the real part and the imaginary part after the digital orthogonal demographic processing. A division unit that performs complex division processing by dividing by the integration result of time T,
It has a frequency error calculation unit that calculates the phase rotation angle by performing an inverse trigonometric function operation using the real part and the imaginary part after the complex division process and calculates the frequency error using the phase rotation angle. ,
The frequency synchronization circuit according to claim 1. It is configured in the FPGA.
A division unit that performs complex division processing by dividing the real part and the imaginary part after the digital orthogonal demodulation process at time t ₁ by the real part and the imaginary part after the digital orthogonal demodulation process at time t ₂ (provided, the digital). Assuming that the sampling period of the signal to be orthogonal demodulated is Δt, t ₂ = t ₁ + Δt),
It has a frequency error calculation unit that calculates the phase rotation angle by performing an inverse trigonometric function operation using the real part and the imaginary part after the complex division process and calculates the frequency error using the phase rotation angle. ,
The frequency synchronization circuit according to claim 1. It is configured in the FPGA.
An inverse tangent calculation unit that performs an inverse tangent function operation using the real part and the imaginary part after the digital orthogonal demodulation process,
Integral for calculating the integral difference by subtracting the integral result of the integral time T of 0 to T for the result of the inverse tangential function operation from the integral result of the integral time T of −T to 0 for the result of the inverse tangential function operation. The arithmetic unit and
It has a frequency error calculation unit for calculating the frequency error using the integral difference.
The frequency synchronization circuit according to claim 1. It is configured in the FPGA.
An inverse tangent calculation unit that performs an inverse tangent function operation using the real part and the imaginary part after the digital orthogonal demodulation process,
A differential calculation unit that calculates the time difference by subtracting the result of the inverse tangential function operation at time t ₁ from the result of the inverse tangential function operation at time t ₂ (however, sampling of the signal to be processed by the digital orthogonal demodulation process). Assuming that the period is Δt, t ₂ = t ₁ + Δt),
It has a frequency error calculation unit for calculating the frequency error using the time difference.
The frequency synchronization circuit according to claim 1. The frequency of the signal to be subjected to the digital orthogonal demodulation process is the voice frequency band.
The frequency synchronization circuit according to any one of claims 1 to 5, wherein the frequency synchronization circuit is characterized in that.

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