JP2021128993A - Semiconductor device and switching system - Google Patents

Abstract

To provide a semiconductor device and a switching system including RC-IGBT in which the increase in switching time is suppressed.SOLUTION: A semiconductor device 1 includes: an insulated gate type bipolar transistor disposed in a transistor region 110 of a semiconductor base body 10, using a semiconductor layer 11 as a drift region, and including an insulated gate type control electrode; a diode disposed in a diode region 120 of the semiconductor base body 10, including a cathode region 21 of a first conductivity type disposed on a back surface side of the semiconductor layer 11 and an anode region 22 of a second conductivity type disposed on a front surface side of the semiconductor layer 11, and connected in reverse parallel to the insulated gate type bipolar transistor; and a surface semiconductor region 42 of the second conductivity type disposed over an inactive region 200. In a plan view, the surface semiconductor region 42 and the cathode region 21 are separated and quasi-synchronous rectifying operation is performed.SELECTED DRAWING: Figure 1

Description

The present invention relates to semiconductor devices and switching systems including RC-IGBTs.

An insulated gate bipolar transistor (IGBT) having a high input impedance and a low on-voltage is used as a switching element (power semiconductor element) that performs a large current switching operation. For example, RC (Reverse) that combines an IGBT and a freewheel diode as shown in Patent Document 1 and Patent Document 2 in a switching system such as driving an inductive load such as a motor or an inverter of a power conversion system between a motor and a battery. Conductive) -IGBT is used. In the RC-IGBT used in the switching system, a reflux current flows through the diode when the IGBT is in the off state. Patent Document 1 discloses a switching method in which the IGBT is temporarily turned on during the OFF period of the IGBT to reduce the recovery loss.

Japanese Unexamined Patent Publication No. 2011-146555 JP-A-2007-129195

In RC-IGBTs used in switching systems, a recovery current flows after turn-off. Since the recovery current flows until the carriers accumulated in the drift region disappear, the switching time increases when the recovery current is large. Further, in the RC-IGBT, when a carrier is supplied to the diode from the surroundings, the recovery current increases and the switching time increases.

In view of the above problems, an object of the present invention is to provide a semiconductor device including an RC-IGBT in which an increase in switching time is suppressed. Further, in an inductive load switching system in which a control circuit for transmitting a control signal for temporarily turning on the IGBT during the off period of the semiconductor device is combined with the semiconductor device, a drive system with further suppressed recovery time is provided. The purpose is.

According to one aspect of the present invention, it has an active region divided into a diode region and a transistor region outside the diode region in a plan view, and an inactive region outside the active region, and extends over the active region and the inactive region. A semiconductor substrate including a first conductive type semiconductor layer which is continuously arranged, and an insulated gate type bipolar transistor which is arranged in the transistor region of the semiconductor substrate, has the semiconductor layer as a drift region, and has an insulated gate type control electrode. , A first conductive type first semiconductor region arranged in the diode region of the semiconductor substrate and arranged on the back surface side of the semiconductor layer, and a second conductive type second semiconductor region arranged on the front surface side of the semiconductor layer. A diode connected in antiparallel to the insulated gate type bipolar transistor and a second conductive type surface semiconductor region arranged on the surface side of the semiconductor layer in the inactive region are provided, and the surface semiconductor region can be seen in a plan view. The first semiconductor regions are separated from each other, and a quasi-synchronous rectification operation is performed.

According to the present invention, it is possible to provide a semiconductor device and a switching system including an RC-IGBT in which an increase in switching time is suppressed.

It is a schematic cross-sectional view which shows the structure of the semiconductor device which concerns on embodiment. It is a schematic plan view which shows the structure of the semiconductor device which concerns on embodiment. It is a schematic plan view which shows the arrangement of the groove formed in the semiconductor device which concerns on embodiment. It is a schematic cross-sectional view along the VI-VI direction of FIG. It is an equivalent circuit diagram of the semiconductor device which concerns on embodiment. It is a schematic diagram which shows the structure of the switching system using the semiconductor device which concerns on embodiment. It is an operation simulation circuit of a switching system. It is a timing chart of an operation simulation circuit. It is a schematic diagram which shows the current path in a period T1. It is a schematic diagram which shows the current path in a period T2. It is a timing chart which shows the method of applying the gate voltage of the semiconductor device which concerns on embodiment. It is a timing chart for demonstrating the quasi-synchronous rectification operation of the semiconductor device which concerns on embodiment. It is a calculation result of the carrier concentration of the semiconductor device which concerns on embodiment at time ta. It is a calculation result of the carrier concentration of the semiconductor device which concerns on embodiment at time tb. It is another calculation result of the carrier concentration of the semiconductor device which concerns on embodiment at time tb. It is a calculation result of the carrier concentration in the cross section along the AA direction of FIGS. 13 to 14. It is a calculation result of the carrier concentration in the cross section along the BB direction of FIG. It is a schematic plan view which shows the back surface of the semiconductor device which concerns on the modification of embodiment. It is a schematic plan view which shows the back surface of the semiconductor device which concerns on other modification of embodiment.

Next, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the lengths of each part, etc. are different from the actual ones. Therefore, the specific dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other.

Further, the embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention describes the shape, structure, arrangement, etc. of components. It is not specific to the following. The embodiments of the present invention can be modified in various ways within the scope of the claims.

As shown in FIG. 1, the semiconductor device 1 according to the embodiment has a semiconductor substrate 10 having an active region 100 and an inactive region 200 of the remaining region of the active region 100, and above the inactive region 200 of the semiconductor substrate 10. The gate bus line 40 is provided. The semiconductor substrate 10 includes a first conductive semiconductor layer 11 that is continuously arranged over the active region 100 and the inactive region 200.

In a plan view, the active region 100 is divided into a diode region 120 and a transistor region 110 arranged outside the diode region 120. Although the diode region 120 is surrounded by the transistor region 110, a part of the periphery of the diode region 120 may not be surrounded by the transistor region 110. In the semiconductor device 1, the inert region 200 and the diode region 120 are separated from each other with the transistor region 110 in between in a plan view. Here, the "planar view" is the surface normal direction of the surface of the semiconductor layer 11, and is the case when viewed from the vertical direction (Z direction) of the paper surface in FIG. In FIG. 1, the plane perpendicular to the Z direction is the XY plane, the left-right direction of the paper surface is the Y direction, and the direction perpendicular to the paper surface is the X direction.

Although details will be described later, an insulated gate bipolar transistor (IGBT) having a semiconductor layer 11 as a drift region is arranged in the transistor region 110. Then, in the diode region 120, a diode connected in antiparallel to the IGBT arranged in the transistor region 110 is arranged. Further, the gate bus line 40 is arranged outside the transistor region 110 and above the inert region 200 of the semiconductor substrate 10 via an interlayer insulating film 30.

FIG. 2 shows a plan view of the semiconductor device 1. FIG. 1 is a cross-sectional view taken along the I-I direction of FIG. Although the case where the outer edge of the diode region 120 is elliptical is exemplified in FIG. 2, the shape of the outer edge of the diode region 120 can be arbitrarily set, for example, the outer edge of the diode region 120 is made rectangular. May be good.

In the semiconductor device 1 shown in FIG. 2, the outer edge portion (40b) of the gate bus line 40 is located in the outer peripheral region, which is the inactive region 200 outside the active region 100, along the outer edge of the semiconductor substrate 10 which is rectangular in a plan view. Is placed. Further, the gate bus line 40 has a connecting portion (40a) that connects the outer edge portion (40b) of the gate bus line 40 in the X direction. In the semiconductor device shown in FIG. 2, the stretched portion (40c) extending in the Y direction of the gate bus line 40 is orthogonal to the connecting portion (40a) of the gate bus line 40. The active region 100 is divided into two regions by the inert region 200 in which the extended portion (40c) of the gate bus line 40 is arranged. Further, as shown in FIG. 2, the gate pad 41 connected to the gate bus line 40 is arranged in the inert region 200.

In FIG. 2, the gate bus line 40 has one connecting portion (40a) extending in the X direction and two outer edge portions (40a) connecting to each end of the connecting portion (40a) and extending in the Y direction. An example is shown which is composed of one stretched portion (40c) extending in the Y direction between the 40b) and the outer edge portion (40b). However, the gate bus line 40 may be arranged so as to surround the active region 100 from four directions. Further, the gate bus line 40 may not have a stretched portion (40c), or the active region 100 may be divided into three or more by a plurality of stretched portions (40c).

The details of the configuration of the IGBT and the diode formed in the active region 100 will be described below with reference to FIG. First, an IGBT arranged in the transistor region 110 and having the semiconductor layer 11 as the drift region 11d will be described.

The IGBT has a second conductive type first semiconductor layer (collector region 12) arranged on the back surface side of the semiconductor layer 11. Further, the IGBT is a second conductive type second semiconductor layer (base region 13) arranged on the surface side of the semiconductor layer 11, and a first conductive type third semiconductor layer (emitter) arranged on the upper part of the base region 13. It has a region 14). Then, the gate electrode (insulated gate type control electrode 16x) faces the base region 13 via the insulating film (gate insulating film 15) arranged on the surface of the base region 13.

The first conductive type and the second conductive type are opposite conductive types to each other. That is, if the first conductive type is n type, the second conductive type is p type, and if the first conductive type is p type, the second conductive type is n type. Here, the case where the first conductive type is the n type and the second conductive type is the p type will be described exemplarily.

An interlayer insulating film 30 is arranged above the control electrode 16x. The base region 13 and the emitter electrode 32 arranged on the surface of the semiconductor substrate 10 connected to the emitter region 14 selectively arranged above the base region 13 are insulated and separated from the control electrode 16x by the interlayer insulating film 30. There is. A collector electrode 31 that is electrically connected to the collector region 12 is arranged on the back surface of the semiconductor substrate 10.

In the IGBT shown in FIG. 1, a first conductive type carrier accumulation region 17 having a higher impurity concentration than the drift region 11d is arranged between the base region 13 and the drift region 11d. By arranging the carrier storage region 17 between the base region 13 and the drift region 11d, the on-voltage of the IGBT can be further reduced, as will be described later.

Further, a first conductive type field stop region 18 having a higher impurity concentration than the drift region 11d is arranged between the drift region 11d and the collector region 12. The field stop region 18 prevents the depletion layer extending from the base region 13 from reaching the collector region 12 when the IGBT is off.

A second conductive type contact region having a higher impurity concentration than the base region 13 may be formed on the surface of the base region 13 between the emitter regions 14.

A trench gate type IGBT is formed in the transistor region 110 of the semiconductor device 1 shown in FIG. That is, a groove (hereinafter referred to as "groove 160X") is formed which extends from the surface of the emitter region 14 to penetrate the emitter region 14, the base region 13 and the carrier storage region 17 and reach the semiconductor layer 11 at the tip. .. The groove 160X extends along the surface of the semiconductor substrate 10, and the gate insulating film 15 is arranged on the inner wall of the groove 160X. The control electrode 16x is arranged on the gate insulating film 15 on the side surface of the groove 160X so as to face the side surface of the base region 13. The surface of the base region 13 facing the control electrode 16x via the gate insulating film 15 is the channel region in which the channel is formed.

The control electrode 16x of the IGBT arranged in the transistor region 110 is electrically connected to the gate pad 41 via the gate bus line 40. A control voltage applied to the gate pad 41 from the outside of the semiconductor device 1 (hereinafter, also referred to as “gate voltage”) is applied to the control electrode 16x of the IGBT via the gate bus line 40.

Next, the diode arranged in the diode region 120 will be described. As shown in FIG. 1, the diode is arranged on the back surface side of the semiconductor layer 11, the first conductive type first semiconductor region (cathode region 21), and the second conductive region arranged on the front surface side of the semiconductor layer 11. It has a second semiconductor region (anode region 22) of the mold. A pn junction is formed at the interface between the semiconductor layer 11 and the anode region 22. In the diode region 120, the semiconductor layer 11 functions as part of the cathode. The cathode region 21 is connected to the field stop region 18 of the transistor region 110.

The collector electrode 31 and the emitter electrode 32 are arranged on the entire surface of the transistor region 110 and the diode region 120. That is, the cathode region 21 is connected to the collector electrode 31, and the anode region 22 is connected to the emitter electrode 32. Therefore, the cathode region 21 is electrically connected to the collector region 12 via the collector electrode 31. Then, the anode region 22 is electrically connected to the emitter region 14 via the emitter electrode 32.

A groove (hereinafter referred to as "groove 160A") is also formed in the diode region 120. An insulating film is provided on the side surface of the groove 160A, and a conductive material 16a is further filled inside. The conductor material 16a inside the groove 160A is electrically connected to the emitter electrode 32. In the diode region 120, the opening of the groove 160A is not covered with the interlayer insulating film 30.

The arrangement of the grooves formed in the semiconductor substrate 10 for arranging the conductor material 16a and the control electrode 16x is shown in the plan view of FIG. As shown in FIG. 3, a plurality of grooves 160A in the diode region 120 and a plurality of grooves 160X in the transistor region 110 extend in parallel with the X direction. In order to connect the grooves 160A extending in the X direction to each other, the grooves 160B connected to the respective ends of the grooves 160A extending in the X direction are formed along the Y direction. An insulating film is provided on the side surface of the groove 160B, and the inside is further filled with a conductor material that connects the conductor materials 16a to each other. Further, in order to connect the grooves 160X extending in the X direction to each other, grooves 160Y connected to each end of the grooves 160X extending in the X direction are formed along the Y direction. An insulating film is provided on the side surface of the groove 160Y, and the inside is further filled with a conductor material 16y that connects the control electrodes 16x to each other. In FIG. 1, the emitter region 14 is not formed around the groove 160Y provided with the conductor material 16y. The groove 160A and 160B are not connected to the groove 160X and the groove 160Y.

Further, in FIG. 3, the cathode region 21 is shown by a dotted line. The outer edge of the cathode region 21 may be the same as the outer edge of the outermost groove in the groove 160A and 160B, or the outermost of the groove 160A and 160B in the range not reaching the groove 160X and the groove 160Y in the transistor region. It may be wider than the outer groove.

The semiconductor substrate 10 forms an n-type impurity region and a p-type impurity region on the semiconductor substrate 10 by an epitaxial growth method, ion implantation and diffusion, or the like. Further, for example, the gate insulating film 15 is formed on the inner wall surface of the groove formed by using the photolithography technique and the etching technique by a thermal oxidation method or the like. Then, the control electrode 16x is formed on the gate insulating film 15 by a polysilicon film, a metal film, or the like.

The field stop region 18, the cathode region 21, the base region 13 and the anode region 22 may be formed at the same time. As a result, the manufacturing process of the semiconductor device 1 can be shortened.

As shown in FIG. 1, the emitter region 14 is not formed around the groove 160X of the transistor region 110 closest to the groove 160Y connected to the gate bus line 40 in the inert region 200. When the IGBT is turned off, the carrier passes through this region where the emitter region 14 is not formed, and the carrier escapes to the emitter electrode 32.

Directly below the gate pad 41, directly below the gate bus line 40, and on the surface side of the semiconductor substrate 10 of the inert region 200 that surrounds the periphery of the active region 100 from the outside, a second conductor is provided in order to secure the withstand voltage of the semiconductor device 1. A type (p type) surface semiconductor region 42 is provided. For example, a well-known resurf structure or FLR structure provided with a second conductive type (p type) surface semiconductor region 42 is formed in the outer peripheral region in order to secure the withstand voltage of the semiconductor device 1.

FIG. 4 shows a cross-sectional view of the semiconductor device 1 along the X direction. In the semiconductor device 1, the inert region 200 and the diode region 120 are separated from each other with the transistor region 110 interposed therebetween.

An equivalent circuit diagram of the semiconductor device 1 is shown in FIG. The semiconductor device 1 is an RC-IGBT that combines an IGBT 51 arranged in the transistor region 110 and a diode 52 arranged in the diode region 120. That is, the emitter region 14 of the IGBT 51 is electrically connected to the anode region 22 of the diode 52. Further, the collector region 12 of the IGBT 51 is electrically connected to the cathode region 21 of the diode 52. Such a semiconductor device 1 is combined to form an inverter circuit as described in Patent Document 1, and a switching system including a control circuit for driving the IGBT 51 is configured.

FIG. 6 shows an example of a switching system using the semiconductor device 1 according to the embodiment. In the switching system shown in FIG. 6, the semiconductor device 1 is attached to the upper arm transistor and freewheeling diode Q2, Q4, Q6 and the lower arm transistor and freewheeling diode Q1, Q3, Q5 of the three-phase motor bridge circuit for driving the motor 500. It is used as a drive switch. The on / off operation of the transistor of the transistor and the freewheeling diode Q1 to the transistor and the freewheeling diode Q6 is controlled by the control circuit 60. In this three-phase motor bridge circuit, a current is passed through the coil (induction load) of the motor 500 at a predetermined timing to rotate the motor 500. The control circuit 60 turns on the insulated gate type bipolar transistor of the other semiconductor device 1 when a recirculation current is flowing in the diode region of one of the semiconductor devices 1 of the upper arm and the lower arm. In the switching system shown in FIG. 6, a low impedance impedance 510 is connected to the lower arm, and the current is monitored from the voltage drop.

FIG. 7 shows a partial operation simulation circuit of the three-phase motor bridge circuit shown in FIG. In FIG. 7, the motor 500 is shown by the coil 501. The current I is the current flowing through the coil 501. Further, the emitter current of the transistor of the transistor and the freewheeling diode Q1 is indicated by the current Q1-Ie, and the collector current of the transistor of the transistor and the freewheeling diode Q2 is indicated by the current Q2-Ic. The gate voltage V1 of the transistor of the transistor and the freewheeling diode Q1 and the gate voltage V2 of the transistor of the transistor and the freewheeling diode Q2 are actually supplied from the control circuit 60, but in order to simplify the operation simulation circuit, FIG. Then, it is shown as a voltage source. The resistors and diodes connected between the gate terminal and the voltage source shown in FIG. 7 indicate the output circuit from the control circuit 60.

FIG. 8 shows a timing chart of the motion simulation circuit shown in FIG. 7. In FIG. 8, the period in which the transistor of the transistor and the freewheeling diode Q1 is in the on state is shown in the period T1, and the period in which the transistor of the transistor and the freewheeling diode Q1 is in the off state is shown in the period T2. In the following, when the transistor of the lower arm and the transistor of the freewheeling diode Q1 are switched from on to off, a forward voltage is applied to the transistor of the upper arm and the diode of the freewheeling diode Q2 by the energy stored in the motor 500, and the diode is used. A freewheeling current flows through the diode. Next, when the transistor of the lower arm and the transistor of the freewheeling diode Q1 are turned on, the freewheeling current does not flow through the transistor of the upper arm and the diode of the freewheeling diode Q2. During the off period of the lower arm transistor and the freewheeling diode Q1 transistor, before turning on the lower arm transistor and the freewheeling diode Q1 transistor, the gate voltage is applied to the control electrode 16x of the upper arm transistor and the freewheeling diode Q2 transistor. It is applied for a certain period of time (hereinafter, this operation is referred to as "quasi-synchronous rectification operation"). In the semiconductor device 1 that operates in quasi-synchronous rectification, as shown in FIG. 8, before the transistor of the lower arm and the transistor of the freewheeling diode Q1 are turned on, after the transistor of the upper arm and the transistor of the freewheeling diode Q2 are turned on for a certain period of time. Turn off. The time for temporarily turning on the transistor of the upper arm and the freewheeling diode Q2 is, for example, 2 μsec. In the semiconductor device that does not operate in quasi-synchronous rectification, the gate voltage V2 is not applied at this timing.

In the quasi-synchronous rectification operation, a channel is generated in the transistor by temporarily turning on the transistor of the transistor and the freewheeling diode Q2. As a result, the barrier of the electron passage of the transistor is lowered, and the holes accumulated directly under the transistor are reduced. As a result, the recovery time is suppressed. Also, the surge voltage is reduced.

FIG. 9 shows the current path R1 in the period T1 in which the transistor and the freewheeling diode Q1 are in the ON state. In the period T1, the transistor of the transistor and the freewheeling diode Q1 and the transistor of the transistor and the freewheeling diode Q4 are turned on, and a current flows through the coil 501. Then, when the transistor and the freewheeling diode Q1 and the transistor of the transistor and the freewheeling diode Q4 are turned off at the same time, as shown by the current path R2 in FIG. A current flows through the diode of the diode Q3. As described above, the transistor is connected in series with the transistor and the freewheeling diode Q1 by the transistor and the freewheeling diode Q4, and the diode is connected in series with the transistor and the freewheeling diode Q2 by the transistor and the freewheeling diode Q3. However, it is possible to evaluate the element operation in operation confirmation and operation simulation even if it is not connected in series in terms of operation. Therefore, the evaluation was performed using the motion simulation circuit shown in FIG. 7.

The operation of the semiconductor device 1 of the transistor and the freewheeling diode Q1 will be described. When the transistor region 110 of the semiconductor device 1 of the transistor and the freewheeling diode Q1 is turned on, the potential of the collector electrode 31 is set higher than the potential of the emitter electrode 32, and a predetermined gate voltage is set between the emitter electrode 32 and the control electrode 16x. Is applied. When the transistor region 110 of the semiconductor device 1 is turned on, the channel region is inverted from the p-type to the n-type to form a channel. Electrons are injected into the drift region 11d from the emitter electrode 32 through the formed channel. Further, the area between the collector region 12 and the drift region 11d is forward-biased, and holes move from the collector electrode 31 via the collector region 12 in the order of the drift region 11d, the carrier accumulation region 17, and the base region 13. .. When the current is further increased, the holes from the collector region 12 increase, and the holes are accumulated in the drift region 11d. As a result, the on-voltage drops due to conductivity modulation.

When the transistor region 110 of the semiconductor device 1 of the transistor and the freewheeling diode Q1 is changed from the on state to the off state, the gate voltage is controlled to be lower than the threshold voltage. For example, the gate voltage is set to have the same potential or negative potential as the emitter voltage. As a result, the channel in the base region 13 disappears, and the injection of electrons from the emitter electrode 32 into the drift region 11d is stopped. When the transistor region 110 of the semiconductor device 1 is turned off, the coil 501 stores energy, the potential of the emitter electrode 32 of the semiconductor device 1 becomes higher than the potential of the collector electrode 31, and the anode in the diode region 120 of the transistor and the freewheeling diode Q1. A return current flows from the region 22 to the cathode region 21 via the semiconductor layer 11 (hereinafter, referred to as “diode operation”).

By arranging the carrier storage region 17 having a higher impurity concentration than the drift region 11d between the drift region 11d and the base region 13, the carrier storage region 17 is in the on state (hereinafter, referred to as “transistor operation”). An electric field is generated from the drift region 11d. As a result, holes are accumulated in the drift region 11d in the vicinity of the interface between the drift region 11d and the carrier accumulation region 17. Therefore, more holes are accumulated as compared with the case where the carrier accumulation region 17 is not arranged. As a result, the on-voltage of the IGBT 51 can be further reduced.

However, if the impurity concentration in the carrier accumulation region 17 is too high, the spread of the depletion layer caused by the pn junction at the interface between the base region 13 and the carrier accumulation region 17 is suppressed in the off state. As a result, the withstand voltage of the semiconductor device 1 decreases. Therefore, it is preferable that the impurity concentration in the carrier accumulation region 17 is higher than the impurity concentration in the drift region 11d and lower than the impurity concentration in the base region 13.

FIG. 11 shows a method of applying the gate voltage Q1-Vg of the semiconductor device 1 of the transistor and the freewheeling diode Q1 and a method of applying the gate voltage Q2-Vg of the semiconductor device 1 of the transistor and the freewheeling diode Q2. After the transistor and freewheeling diode Q1 switch from transistor operating Tt to diode operating Td at time t_OFF, before the time t_ON when the transistor and freewheeling diode Q1 switch from diode operating Td to transistor operating Tt, the positive gate voltage is passed through the transistor and freewheeling. It is applied to the control electrode 16x of the diode Q2. As a result, the recovery current of the transistor and the freewheeling diode Q2 can be suppressed.

FIG. 12 shows an example of the voltage waveform and the current waveform of the semiconductor device 1 in the quasi-synchronous rectification operation. In FIG. 12, the voltage Q1_Vge indicates the gate voltage when viewed as a voltage for controlling the operation of the IGBT 51. On the other hand, the voltage Q2_Vge indicates the gate voltage when viewed as a voltage for controlling the operation of the diode 52 in the diode operation. The collector-emitter voltage in diode operation is indicated by the voltage Q2_Vce. In FIG. 12, the current Q2_Id is the current flowing through the diode 52.

13 and 14 show the results of calculating the carrier (hole) concentration at time ta and time tb in FIG. 12 by a simulation modeling the active region 100 near the boundary between the transistor region 110 and the diode region 120. At time ta, the gate voltage is not applied in the diode operation. At time tb, the gate voltage is applied in the diode operation by the quasi-synchronous rectification operation. The carrier concentration at time tb shown in FIG. 14 is lower than the carrier concentration at time ta shown in FIG. FIG. 16 shows the carrier concentration of the semiconductor device 1 in the depth direction D in the cross section along the AA direction in FIGS. 13 and 14. It can be seen that the point h indicating the peak of the carrier concentration at time ta is reduced to the point i at time tb, and the total amount of carrier concentration at time tb is also smaller than the total amount of carrier concentration at time ta.

When the quasi-synchronous rectification operation is not performed, the recovery operation is started in the state of time ta. Therefore, the carrier concentration in the drift region 11d of the IGBT 51 is high, and it is necessary to pass a large recovery current. Therefore, the recovery time is increased and the switching characteristics are deteriorated. On the other hand, when the quasi-synchronous rectification operation is performed, the recovery current in the transistor region 110 can be reduced. By performing the quasi-synchronous rectification operation in this way, the recovery current of the entire semiconductor device 1 can be reduced.

It is not preferable to apply a gate voltage to the control electrode 16x over the entire period of diode operation. This is because the forward voltage Vf increases as the carriers decrease during the entire diode operation. Therefore, it is preferable to apply the gate voltage to the control electrode 16x only for a certain period of the diode operation before switching to the transistor operation.

By the way, a p-type surface semiconductor region 42 is formed on the surface side of the semiconductor substrate 10 of the inert region 200 of the semiconductor device 1. The p-type surface semiconductor region 42 on the surface side of the semiconductor substrate 10 in the inactive region 200 serves as a source of carriers (holes) during diode operation, and forms a semiconductor layer 11 between the surface semiconductor region 42 and the cathode region 21. There will be many carriers (holes). As a result, the recovery current of the semiconductor device 1 cannot be further reduced.

Therefore, in the semiconductor device 1, the p-type surface semiconductor region 42, which is arranged on the surface side of the semiconductor layer 11 directly under the gate bus line 40, the gate pad 41, etc. and serves as a supply source of a small number of carriers in diode operation, is viewed in a plan view. The structure does not overlap with the cathode region 21. Therefore, the recovery time can be shortened. Further, in the plan view of the semiconductor device 1, the transistor region 110 is provided between the inert region 200 such as the gate bus line 40 and the gate pad 41 and the cathode region 21. By turning on the transistor in the transistor region 110 in the quasi-synchronous rectification operation, the recovery time can be further shortened in the semiconductor device 1.

As shown in FIG. 14, the region having a high carrier concentration gradually increases from the boundary between the transistor region 110 and the diode region 120 toward the inside of the transistor region 110 with the vicinity of the center of the depth of the semiconductor substrate 10 as a convex portion. do. Therefore, it is preferable that the distance W from the gate bus line 40 or the gate pad 41 to the diode region 120 in a plan view is somewhat wider than the thickness L of the semiconductor substrate 10. For example, the distance W from the gate bus line 40 or the gate pad 41 to the diode region 120 (cathode region 21) in a plan view is set to be at least twice the thickness L of the semiconductor substrate 10, and the semiconductor substrate 10 in between is set to the transistor region. It is desirable to set it to 110.

By the way, in the diode region 120, the area of the cathode region 21 may be larger than the area of the anode region 22. In this case, in a plan view, the distance from the inert region 200 where the gate bus line 40 and the gate pad 41 are arranged to the cathode region 21 is preferably larger than twice the thickness L of the semiconductor substrate 10. ..

Further, FIG. 15 shows an example in which the carrier concentration at time tb in the active region 100 (transistor region 110 and diode region 120) and the inactive region 200 was calculated by simulation. Further, FIG. 17 shows the carrier concentration in the depth direction D of the semiconductor device 1 in the cross section along the BB direction of FIG. Note that FIG. 15 is different in that a part of the transistor region 110 of FIG. 14 becomes the inert region 200, and the p-type surface semiconductor region 42 is provided on the surface side of the semiconductor substrate 10 of the inert region 200.

Compared with the carrier concentration on the surface side of the semiconductor substrate 10 in the cross section along the AA direction of FIG. 14 (for example, the carrier concentration of the point i in FIG. 16), the semiconductor substrate in the cross section along the BB direction of FIG. The carrier concentration on the surface side of No. 10 (for example, the carrier concentration at point j in FIG. 17) is high, and serves as a carrier supply source. Therefore, the recovery time can be shortened by adopting a structure in which the inert region 200 does not overlap with the cathode region 21 in the plan view of the semiconductor device 1. Further, in the plan view of the semiconductor device 1, the transistor region 110 is provided between the inert region 200 such as the gate bus line 40 and the gate pad 41 and the cathode region 21. By turning on the transistor in the transistor region 110 in the quasi-synchronous rectification operation, the recovery time can be further shortened in the semiconductor device 1. Further, the recovery time can be further shortened by separating the inert region 200 and the cathode region 21 by 2 L or more with respect to the thickness L of the semiconductor substrate in the plan view of the semiconductor device 1.

As described above, in the semiconductor device 1 according to the embodiment, the p-type on the surface side of the arranged inert region 200 such as the gate bus line 40 and the gate pad 41, which is a supply source of a small number of carriers in the diode operation. The surface semiconductor region 42 of the above is arranged apart from the diode region 120 (cathode region 21) in a plan view. Therefore, according to the semiconductor device 1, an increase in the recovery current can be suppressed. As a result, the recovery time can be shortened and the switching characteristics of the semiconductor device 1 can be improved.

<Modification example>
For example, in the semiconductor device 1 that requires a high withstand voltage of 1000 V or more, carriers are generated in the outer peripheral region for ensuring the withstand voltage. Due to this carrier generation, the switching speed of the semiconductor device 1 decreases. In the case of RC-IGBT, the switching time in the off operation of the IGBT 51 and the recovery operation of the diode 52 is reduced due to the above-mentioned carrier generation.

In the IGBT, the carrier passes between the groove around the transistor region 110 and the groove on the outside thereof, and the carrier escapes to the emitter electrode 32. Therefore, it is preferable to consider the balance between the OFF operation of the IGBT 51 and the recovery operation of the diode 52. For example, as shown in FIG. 18, an n-type outer edge semiconductor region 211 is arranged along the outer edge of the semiconductor substrate 10 on the back surface of the semiconductor substrate 10 in the inactive region 200 outside the gate bus line 40 in a plan view ( That is, the collector region 12 is not provided along the outer edge of the semiconductor substrate 10). The n-type outer edge semiconductor region 211 is electrically connected to the collector electrode 31 and the drift region 11d. The impurity concentration of the outer edge semiconductor region 211 is set to be about the same as that of the cathode region 21, for example.

As shown in FIG. 18, the length of the outer edge semiconductor region 211 from the outer edge of the semiconductor substrate 10 toward the center of the semiconductor substrate 10 is defined as the corner portion in the vicinity of the corner portion of the semiconductor substrate 10 which is rectangular in a plan view. It may be longer than the outer side portion (other than the vicinity of the corner portion) connecting the above. This is because the carrier is less likely to come off in the vicinity of the corner portion than in other regions.

Further, in the semiconductor device of FIG. 18, the outer edge semiconductor region 211 is not provided on the back surface side of the semiconductor substrate 10 directly under the gate pad 41, and the collector region 12 is provided on the back surface of the semiconductor substrate 10 directly under the gate pad 41. desirable. Specifically, it is desirable that the outer edge semiconductor region 211 is not provided on the back surface side of the semiconductor substrate 10 on the paper surface of 13, but is used as a collector region. Since the p-type surface semiconductor region 42 is provided under the gate pad 41 as well as the p region under the gate bus line 40 shown in FIG. 1, the outer edge is on the back surface side of the semiconductor substrate 10 directly under the gate pad 41. When the semiconductor region 211 is provided, the outer edge semiconductor region 211 and the p-type surface semiconductor region 42 under the gate pad 41 are close to each other when the semiconductor device 1 is viewed in a plan view, and the p-type under the gate pad 41 is formed. This is because the surface semiconductor region 42 serves as a carrier (hole) supply source during diode operation.

By the way, when the area of the collector region 12 of the transistor region 110 is large, the hFE of the IGBT becomes very large. As a result, the number of carriers generated increases and the recovery current increases. Therefore, in order to control the amount of carriers generated in the IGBT, a part of the collector region 12 may be formed as a dot-shaped n-type semiconductor region on the back surface side of the semiconductor substrate 10 of the transistor region 110. The area of the newly provided dot-shaped n-type semiconductor region is smaller than the area of the diode region 120, and the newly provided dot-shaped n-type semiconductor region is electrically connected to the collector electrode 31 and the drift region 11d.

For example, as shown in FIG. 19, a plurality of island-shaped n-type dot-shaped regions 212 arranged around the diode region 120 surrounded by the collector region 12 are arranged on the back surface side of the semiconductor substrate 10. The size of the punctate region 212 is not particularly limited, but is made larger than the size that can be accurately formed by, for example, a semiconductor manufacturing process. Further, the upper limit of the size of the point-shaped region 212 is set so as not to limit the main current flowing through the IGBT too much in the transistor operation. By arranging the n-type region on the back surface side of the semiconductor substrate 10 of the transistor region 110, the solid area of the collector region 12 can be reduced and the amount of carriers generated in the IGBT can be controlled.

(Other embodiments)
As mentioned above, the invention has been described by embodiment, but the statements and drawings that form part of this disclosure should not be understood to limit the invention. Various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art from this disclosure.

For example, in the above, the case where the IGBT is a trench gate type has been described, but the IGBT may be a planar type.

As described above, it goes without saying that the present invention includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description.

10 ... Semiconductor substrate 11 ... Semiconductor layer 12 ... Collector region 13 ... Base region 14 ... Emitter region 15 ... Gate insulating film 16x ... Control electrode 21 ... Cathode region 22 ... Anode region 30 ... Interlayer insulating film 31 ... Collector electrode 32 ... Emitter electrode 40 ... Gate bus line 41 ... Gate pad 42 ... Surface semiconductor region 100 ... Active region 110 ... Transistor region 120 ... Diode region 200 ... Inactive region

Claims (8)

It has an active region divided into a diode region and a transistor region outside the diode region in a plan view, and an inactive region outside the active region, and is continuously arranged over the active region and the inactive region. A semiconductor substrate containing the first conductive semiconductor layer,
An insulated gate bipolar transistor arranged in the transistor region of the semiconductor substrate, having the semiconductor layer as a drift region, and having an insulated gate type control electrode.
A first conductive type first semiconductor region arranged in the diode region of the semiconductor substrate and arranged on the back surface side of the semiconductor layer, and a second conductive type second semiconductor arranged on the front surface side of the semiconductor layer. A diode having a region and connected in antiparallel to the insulated gate type bipolar transistor,
A second conductive type surface semiconductor region arranged on the surface side of the semiconductor layer of the inert region is provided, and the surface semiconductor region and the first semiconductor region are separated from each other in a plan view.
A semiconductor device characterized by quasi-synchronous rectification operation. Further provided with a gate bus line located above the surface semiconductor region and electrically connected to the control electrode.
The semiconductor device according to claim 1, wherein the distance from the surface semiconductor region to the first semiconductor region is twice or more the thickness of the semiconductor substrate in a plan view. It has an active region divided into a diode region and a transistor region outside the diode region in a plan view, and an inactive region outside the active region, and is continuously arranged over the active region and the inactive region. A semiconductor substrate containing the first conductive semiconductor layer,
An insulated gate bipolar transistor arranged in the transistor region of the semiconductor substrate and having the semiconductor layer as a drift region,
A first conductive type first semiconductor region arranged in the diode region of the semiconductor substrate and arranged on the back surface side of the semiconductor layer, and a second conductive type second semiconductor arranged on the front surface side of the semiconductor layer. A diode having a region and connected in antiparallel to the insulated gate type bipolar transistor,
A second conductive surface semiconductor region arranged on the surface side of the semiconductor layer in the inert region,
It is provided with a control electrode of the insulated gate bipolar transistor arranged above the surface semiconductor region and a gate bus line electrically connected to the control electrode.
A semiconductor device characterized in that the distance from the surface semiconductor region to the first semiconductor region is twice or more the thickness of the semiconductor substrate in a plan view. Any of claims 1 to 3, further comprising a plurality of island-shaped first conductive type point-shaped regions arranged in the transistor region around the diode region on the back surface side of the semiconductor substrate. The semiconductor device according to item 1. 2. The second aspect of the present invention is characterized in that, in the inert region outside the gate bus line, a first conductive type outer edge semiconductor region arranged on the back surface side of the semiconductor substrate along the outer edge of the semiconductor substrate is further provided. Or the semiconductor device according to 3. The length of the outer edge semiconductor region from the outer edge of the semiconductor substrate toward the center of the semiconductor substrate is longer at the corner portion of the semiconductor substrate, which is rectangular in a plan view, than at the outer edge portion connecting the corner portions. The semiconductor device according to claim 5, wherein the semiconductor device is characterized by the above. Further provided with a gate pad located in the inert region and connected to the gate bus line.
Any of claims 2, 3, 5, and 6, wherein in a plan view, the distance from the gate pad to the first semiconductor region is larger than twice the thickness of the semiconductor substrate. The semiconductor device according to item 1. A switching system with an inductive load connected
The semiconductor device according to any one of claims 1 to 7 is used as a drive switch for an upper arm and a lower arm connected to the inductive load.
A switching system comprising a control circuit for turning on the insulated gate bipolar transistor of the other semiconductor device when a recirculation current is flowing in the diode region of the semiconductor device.

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