JP2021101496A - Circuit device, radio transmitter, oscillator, and electronic apparatus - Google Patents

Abstract

To provide a circuit device that generates, with a simple configuration, a clock signal for radio transmission that is synchronized with a reference clock signal and has high frequency accuracy, a radio transmitter, an oscillator, and an electronic apparatus.SOLUTION: In a radio transmitter, a circuit device 10 has a processing circuit 20 and a synchronous circuit 50. The processing circuit 20 generates frequency control data DFC and performs modulation processing on the frequency control data DFC. The synchronous circuit 50 has a digital control oscillation circuit 80. The digital control oscillation circuit 80 generates a clock signal CLK with an oscillatory frequency corresponding to the frequency control data DFC. The synchronous circuit 50 outputs the clock signal CLK generated by the digital control oscillation circuit 80 based on the frequency control data DFC on which the modulation processing is performed, as a modulated clock signal for radio transmission.SELECTED DRAWING: Figure 2

Description

The present invention relates to circuit devices, wireless transmitters, oscillators, electronic devices, and the like.

When wireless communication is performed between devices, it is necessary to synchronize the frequencies between the transmitting device and the receiving device to some extent. However, it is difficult for a frequency output device such as an inexpensive oscillator to synchronize the frequencies because the oscillation frequency varies from individual to individual and the temperature characteristics of the oscillation frequency are different. In Patent Document 1, in order to correct such frequency variation, a preamble or a synchronization code is provided as a communication format, data for frequency correction is transmitted separately from wireless transmission data, and correction is performed by a device on the receiving side. Is going.

Japanese Unexamined Patent Publication No. 06-1253667

In the configuration as in Patent Document 1, a digital arithmetic unit for data correction or the like is also required for the device on the receiving side, which is a complicated configuration. In addition, if the communication format includes a preamble or the like, the data rate will drop and the current consumption will increase. Therefore, no method has been proposed that realizes wireless communication between devices whose frequencies are synchronized with a simple configuration without using a communication format such as a preamble.

One aspect of the present disclosure includes a processing circuit that generates frequency control data and a synchronization circuit having a digital control oscillation circuit that generates a clock signal of an oscillation frequency corresponding to the frequency control data. The synchronization circuit synchronizes the clock signal generated by the digitally controlled oscillation circuit with a reference clock signal input from the outside, and in the output mode, the processing circuit performs modulation processing on the frequency control data, and the synchronization. The circuit relates to a circuit device that outputs the clock signal generated by the digitally controlled oscillator circuit based on the frequency control data to which the modulation processing has been performed as the clock signal for modulated wireless transmission.

Configuration example of the circuit device and wireless transmitter of this embodiment. A detailed configuration example of the circuit device of this embodiment. A detailed configuration example of the circuit device of this embodiment. Configuration example of a comparison circuit including a time-digital conversion circuit. Configuration example of digital control oscillator circuit. The signal waveform diagram explaining the operation of the circuit apparatus of this embodiment. Another detailed configuration example of the circuit device of this embodiment. Configuration example of a comparison circuit including a frequency counter and a time digital conversion circuit. A signal waveform diagram illustrating the operation of a comparison circuit including a frequency counter and a time-to-digital conversion circuit. Another detailed configuration example of the circuit device of this embodiment. The signal waveform diagram explaining the operation of the circuit apparatus of this embodiment. Explanatory drawing of setting of disable or power saving state in synchronous mode. Explanatory drawing of setting of disable or power saving state in output mode. Explanatory drawing of setting of disable or power saving state in sleep mode. First configuration example of a time digital conversion circuit. The signal waveform diagram explaining the operation of the 1st configuration example of a time digital conversion circuit. A second configuration example of a time digital conversion circuit. The signal waveform diagram explaining the operation of the 2nd configuration example of a time digital conversion circuit. Configuration example of the oscillator of this embodiment. Configuration example of the electronic device of this embodiment.

Hereinafter, this embodiment will be described. The present embodiment described below does not unreasonably limit the description of the scope of claims. Moreover, not all of the configurations described in the present embodiment are essential configuration requirements.

1. 1. Circuit device and wireless transmitter FIG. 1 shows a configuration example of the circuit device 10 and the wireless transmitter 200 of the present embodiment. The wireless transmitter 200 of the present embodiment includes the circuit device 10 and the wireless transmitter 100 of the present embodiment. The wireless transmitter 200 is a device that performs wireless transmission at a frequency in a predetermined frequency band, and is a wireless transmission module. The radio transmission unit 100 includes at least an antenna and a matching circuit for radio transmission, and more preferably includes a radio transmission circuit such as a power amplifier. Then, the circuit device 10 outputs the clock signal CLK for wireless transmission to the wireless transmission unit 100. Using this clock signal CLK, the wireless transmission unit 100 outputs a wireless transmission signal at a carrier frequency of a predetermined frequency band to an antenna to perform wireless transmission. The radio frequency band includes various frequency bands such as UHF (Ultra High Frequency), HF (High Frequency), MF (Medium Frequency), and LF (Low Frequency).

As shown in FIG. 1, the circuit device 10 of the present embodiment includes a processing circuit 20 and a synchronization circuit 50. The processing circuit 20 is a circuit that performs various processes, for example, performs a process of generating frequency control data DFC. The frequency control data DFC is also called the frequency control word FCW. The processing circuit 20 also performs modulation processing for wireless communication and the like. Further, the processing circuit 20 may perform interface processing with the external device of the circuit device 10. This processing circuit 20 can be realized by, for example, an ASIC (Application Specific Integrated Circuit) or a processor such as a microcomputer.

The synchronization circuit 50 is a circuit that performs processing such as synchronization processing for wireless communication, and has a digital control oscillation circuit 80. The digital control oscillation circuit 80 generates a clock signal CLK of an oscillation frequency corresponding to the frequency control data DFC from the processing circuit 20. As shown in FIG. 5 described later, the digital control oscillation circuit 80 generates a clock signal CLK by oscillating the oscillator XTAL at an oscillation frequency corresponding to, for example, frequency control data DFC. As the digital control oscillation circuit 80, an LC oscillation circuit, a ring type oscillation circuit, or the like may be used.

In the present embodiment, the circuit device 10 has a synchronization mode and an output mode as operation modes. The processing circuit 20 sets the operation mode, for example. The operation mode may be set from the outside by command setting. The synchronization mode is a mode in which the clock signal CLK is synchronized with the reference clock signal RCLK input from the outside. The output mode is a mode for outputting a clock signal CLK for wireless transmission, and is an output mode for a specific frequency. For example, the output mode is a mode in which wireless transmission is performed, and a modulated clock signal CLK for wireless transmission is output.

Specifically, in the synchronization mode, the synchronization circuit 50 synchronizes the clock signal CLK generated by the digital control oscillation circuit 80 with the reference clock signal RCLK input from the outside. For example, the reference clock signal RCLK is input from the outside via the terminal TE, which is an external input terminal of the circuit device 10. In the synchronization mode, the synchronization circuit 50 performs an operation of synchronizing the clock signal CLK with the reference clock signal RCLK which is the external input signal. For example, by using a PLL (Phase Locked Loop) or FLL (Frequency Locked Loop) circuit as described later as the synchronization circuit 50, the clock signal CLK can be synchronized with the reference clock signal RCLK.

On the other hand, in the output mode, the processing circuit 20 performs modulation processing on the frequency control data DFC. For example, the modulation processing for the frequency control data DFC is realized by adding or subtracting the modulation data to the frequency control data DFC. Then, the synchronization circuit 50 outputs the clock signal CLK generated by the digital control oscillation circuit 80 based on the modulated frequency control data DFC as the modulated clock signal CLK for wireless transmission.

For example, the processing circuit 20 holds the frequency control data DFC when the clock signal CLK is synchronized with the reference clock signal RCLK in the synchronization mode. For example, the processing circuit 20 holds the frequency control data DFC before switching from the synchronous mode to the output mode. Then, the processing circuit 20 performs modulation processing on the held frequency control data DFC in the output mode. By doing so, the frequency control data DFC when synchronized with the reference clock signal RCLK, which guarantees high frequency accuracy, can be modulated. Then, in the present embodiment, for example, the modulated clock signal CLK for wireless transmission is output to the wireless transmission unit 100 via the terminal TCQ which is the clock output terminal of the circuit device 10. In the output mode, modulation is performed in which the frequency of the clock signal CLK changes alternately, for example, fs1 and fs2. This enables wireless transmission by a modulation method such as FSK (Frequency shift keying).

Here, as the reference clock signal RCLK, a time signal input from a GNSS (Global Navigation Satellite System) or a network receiver can be assumed. When the GNSS is a GPS (Global Positioning System), the reference clock signal RCLK, which is an external clock signal, is a 1 pps signal, for example, a signal having a frequency of 1 Hz. Then, the synchronization circuit 50 is a signal obtained by multiplying the frequency of the reference clock signal RCLK, and generates a clock signal CLK that is phase-synchronized or frequency-synchronized with the reference clock signal RCLK.

As described above, in the present embodiment, in the synchronization mode, the clock signal CLK generated by the digital control oscillation circuit 80 is synchronized with the reference clock signal RCLK from GNSS, the network, or the like. By synchronizing with the reference clock signal RCLK having high frequency accuracy in this way, the digital control oscillator circuit 80 can generate the clock signal CLK with high frequency accuracy. That is, if the clock signal CLK is generated simply by using only the vibrator, the frequency accuracy of the clock signal CLK is lowered due to individual variation of the vibrator, temperature characteristics, aging characteristics, and the like. On the other hand, in the present embodiment, the frequency accuracy of the clock signal CLK can be made equal to the frequency accuracy of the reference clock signal RCLK by synchronizing the clock signal CLK with the reference clock signal RCLK having high frequency accuracy. It will be possible. Then, in the present embodiment, in the output mode, the processing circuit 20 performs modulation processing on the frequency control data DFC output to the digital control oscillation circuit 80. In this way, the clock signal CLK maintained at high frequency accuracy by synchronizing with the reference clock signal RCLK is modulated by the modulation process of the frequency control data DFC, so that the modulated clock signal CLK for wireless transmission is used. Can be output to the wireless transmission unit 100. Therefore, the carrier frequency in wireless transmission can be made highly accurate, and the wireless transmitter 200 can perform wireless transmission with a carrier frequency having high frequency accuracy. As described above, in the present embodiment, the synchronization of the clock signal CLK with the external reference clock signal RCLK and the output of the modulated clock signal CLK can be time-divisioned. Therefore, it becomes possible to realize wireless transmission of a modulation method such as FSK by using the clock signal CLK with high frequency accuracy synchronized with the reference clock signal RCLK.

For example, if the frequency accuracy of a wireless carrier wave is low, a communication error will occur and the communication quality will deteriorate. In this regard, according to the circuit device 10 of the present embodiment, since wireless transmission can be performed using the clock signal CLK with high frequency accuracy, it is possible to suppress the occurrence of communication errors and improve the communication quality. Further, for example, even in the wireless receiver with which the wireless transmitter 200 of the present embodiment communicates, a clock signal for wireless reception can be generated based on a reference clock signal from, for example, a GNSS or a network. By doing so, it is possible to accurately match the frequency on the transmitting side and the frequency on the receiving side of the radio without using a communication format such as a preamble, and it is possible to effectively suppress the occurrence of communication errors and the like. Further, it is not necessary to provide a digital arithmetic unit or the like as in Patent Document 1 described above, and high-quality wireless communication can be realized by a circuit device 10 having a simple configuration. Further, in FDD (Frequency Division Duplex) and TDD (Time Division Duplex), it is necessary to synchronize the time between the transmitting side and the receiving side of the radio. In this regard, in the present embodiment, both the wireless transmitter 200 and the wireless receiver have a simple configuration such as time synchronization in FDD or TDD by synchronizing the clock signal with the reference clock signal from the GNSS or the network. There is an advantage that it can be realized by the circuit device 10 of.

FIG. 2 shows a detailed configuration example of the circuit device 10 of the present embodiment. In FIG. 2, the processing circuit 20 includes an adder 30, a modulation data output unit 32, and a digital loop filter 40. A modulator is composed of an adder 30 and a modulation data output unit 32. The digital loop filter 40 is a circuit that performs digital filter processing, and performs digital loop filter processing in a PLL or the like. The digital loop filter 40 has, for example, a holding circuit 42. The adder 30 performs a process of adding the modulation data DM from the modulation data output unit 32 to the frequency control data DFC 1 from the digital loop filter 40, and outputs the frequency control data DFC 2 after the modulation processing. This frequency control data DFC2 corresponds to the frequency control data DFC of FIG. The modulation process is not limited to such an addition process, and may be realized by a process of subtracting the modulation data DM from the frequency control data DFC1.

The synchronization circuit 50 includes a comparison circuit 60 and a digitally controlled oscillator circuit 80. Further, the synchronization circuit 50 can include a frequency dividing circuit 52, an output circuit 54, switches SW1 and SW2. An ADPLL (All Digital Phase-locked loop) circuit is configured by the comparison circuit 60, the processing circuit 20, the digital control oscillation circuit 80, and the frequency dividing circuit 52. This ADPLL circuit can be made into a fractional-N type PLL circuit by setting a decimal division ratio with respect to the frequency division circuit 52, for example, by using a delta-sigma modulation unit.

The frequency dividing circuit 52 divides the clock signal CLK generated by the digital control oscillation circuit 80, and outputs the divided clock signal as the feedback clock signal FBCLK to the comparison circuit 60. For example, when the reference clock signal RCLK is a 1 pps signal from a GPS receiver and the frequency of the clock signal CLK is 10 MHz, the frequency divider circuit 52 converts the 10 MHz clock signal CLK into a 1 Hz feedback clock signal FBCLK. Performs frequency division processing.

The output circuit 54 is a circuit for buffering the clock signal CLK generated by the digital control oscillation circuit 80 and outputting it to the outside via the terminal TCQ. For example, the output circuit 54 outputs the clock signal CLK in the form of a CMOS signal to the outside via the terminal TCQ.

The wireless transmission unit 100 includes a transmission circuit 102 and an antenna ANT. The transmission circuit 102 is, for example, a circuit in which a clock signal CLK is input and a radio transmission signal is output to the antenna ANT. The transmission circuit 102 is composed of, for example, a power amplifier or the like. The power amplifier amplifies the transmission signal and outputs it to the antenna ANT. As a result, the transmitted data is transmitted to the receiving device by wireless communication. This power amplifier can include, for example, a current source realized by a P-type transistor and a drive unit realized by an N-type transistor. Further, a matching circuit or the like can be provided between the transmission circuit 102 and the antenna ANT. Although the wireless transmission unit 100 is configured to include the transmission circuit 102 in FIG. 2, the circuit device 10 may be provided with all or a part of the transmission circuit 102.

Further, the synchronization circuit 50 includes a switch SW1 which is a first switch. Further, the synchronization circuit 50 includes a switch SW2 which is a second switch. These switches SW1 and SW2 are composed of, for example, transistors. Specifically, it is composed of MOS transistors. For example, the switches SW1 and SW2 may be realized by an N-type transistor or a P-type transistor, or may be realized by a transfer gate or the like. The switches SW1 and SW2 can be said to be switch circuits composed of transistors, for example.

The switch SW1 which is the first switch is provided between the digital control oscillation circuit 80 and the comparison circuit 60. For example, the switch SW1 is provided between the output node of the digital control oscillation circuit 80 and the input node of the comparison circuit 60. For example, in FIG. 2, the switch SW1 is provided between the output node of the digitally controlled oscillator circuit 80 and the input node of the frequency dividing circuit 52, and the frequency dividing circuit 52 is provided between the switch SW1 and the input node of the comparison circuit 60. It is provided in. Then, as shown in FIG. 2, the switch SW1 is turned on in the synchronous mode. On the other hand, as shown in FIG. 3, the switch SW1 is turned off in the output mode. By turning on the switch SW1 in the synchronous mode in this way, the clock signal CLK from the digitally controlled oscillation circuit 80 is input to the frequency dividing circuit 52 via, for example, the switch SW1, and the frequency dividing circuit 52 causes the frequency dividing circuit 52 to input the clock signal CLK. The feedback clock signal FBCLK, which is a signal obtained by dividing the clock signal CLK, is input to the comparison circuit 60. As a result, a feedback loop in the PLL and the FLL described later is formed, and a synchronous operation for synchronizing the clock signal CLK with the reference clock signal RCLK becomes possible.

The second switch, switch SW2, is turned off in the synchronous mode as shown in FIG. 2 and turned on in the output mode as shown in FIG. By turning off the switch SW2 in the synchronous mode, it is possible to prevent the clock signal CLK generated by the digital control oscillation circuit 80 from being unnecessarily transmitted to the wireless transmission unit 100 via the output circuit 54. It is possible to prevent problems such as wasteful consumption of electric power. On the other hand, when the switch SW2 is turned on in the output mode, the clock signal CLK generated by the digital control oscillation circuit 80 can be output to the wireless transmission unit 100. For example, the generated clock signal CLK can be buffered by the output circuit 54 and output to the wireless transmission unit 100.

Further, as shown in FIG. 2, the synchronization circuit 50 includes a comparison circuit 60. The comparison circuit 60 compares the reference clock signal RCLK with the feedback clock signal FBCLK based on the clock signal CLK, and outputs the comparison result data CQ obtained by the comparison to the processing circuit 20. For example, the comparison circuit 60 performs phase comparison or frequency comparison between the reference clock signal RCLK and the feedback clock signal FBCLK. Then, the comparison circuit 60 outputs data corresponding to the phase difference or frequency difference between the reference clock signal RCLK and the feedback clock signal FBCLK as the comparison result data CQ. The processing circuit 20 generates the frequency control data DFC1 based on the comparison result data CQ from the comparison circuit 60. For example, the frequency control data DFC1 is generated when the digital loop filter 40 of the processing circuit 20 performs the digital loop filter processing based on the comparison result data CQ. In FIG. 2, the feedback clock signal FBCLK is a clock signal obtained by dividing the clock signal CLK by the frequency dividing circuit 52. The feedback clock signal FBCLK based on the clock signal CLK may be the clock signal CLK itself as shown in FIG. 7 described later.

If such a comparison circuit 60 is provided, frequency control data DFC1 corresponding to the comparison result data CQ of the reference clock signal RCLK and the feedback clock signal FBCLK based on the clock signal CLK is generated, and corresponds to the frequency control data DFC1. The frequency clock signal CLK can be generated. That is, by generating the frequency control data DFC1 corresponding to the comparison result data CQ of the comparison circuit 60, it is possible to generate a clock signal CLK that is phase-locked or frequency-synchronized with the reference clock signal RCLK in the synchronization mode. become. Therefore, in the synchronous mode, the clock signal CLK having a frequency accuracy corresponding to the frequency accuracy of the reference clock signal RCLK can be generated, and the frequency accuracy of the clock signal CLK generated by the circuit device 10 can be remarkably improved.

Further, the processing circuit 20 includes a digital loop filter 40 that performs digital loop filter processing on the comparison result data CQ to generate frequency control data DFC1. The digital loop filter 40 can be realized by, for example, a digital filter such as FIR (Finite Impulse Response) or IIR (Infinite Impulse Response). By providing such a digital loop filter 40, it is possible to set the loop response characteristics in the feedback loop of the PLL and the FLL described later. For example, by setting the frequency characteristics such as the cutoff frequency of the digital loop filter 40, the loop response characteristics can be set, and the synchronization characteristics such as the time until the synchronization of the synchronization circuit 50 converges can be set.

Further, in the present embodiment, the processing circuit 20 holds the frequency control data DFC1 when the clock signal CLK is synchronized with the reference clock signal RCLK in the synchronization mode. Specifically, in FIG. 2, the holding circuit 42 of the digital loop filter 40 holds the frequency control data DFC1 in the synchronous mode. For example, the frequency control data DFC1 when switching from the synchronous mode to the output mode is held. For example, the holding circuit 42 holds the frequency control data DFC1 immediately before switching to the output mode. Then, the processing circuit 20 performs modulation processing on the frequency control data DFC 1 held in the holding circuit 42 in the output mode. For example, modulation processing such as adding modulation data DM to the held frequency control data DFC 1 is performed, and the frequency control data DFC 2 after the modulation processing is output to the digital control oscillation circuit 80. In this way, the frequency control data DFC1 when synchronized with the reference clock signal RCLK is retained, and the frequency control data DFC1 is modulated to obtain the modulated clock signal CLK for wireless transmission. It will be possible to output to 100. Since the frequency control data DFC1 to be modulated is data that synchronizes the clock signal CLK with the reference clock signal RCLK, for example, the clock signal CLK with frequency accuracy corresponding to the reference clock signal RCLK is used. Wireless transmission using a modulation method such as FSK will be possible.

Further, in FIG. 2, the comparison circuit 60 performs a phase comparison comparing the phase of the reference clock signal RCLK and the phase of the feedback clock signal FBCLK, and outputs the comparison result data CQ obtained by the phase comparison to the processing circuit 20. That is, the comparison circuit 60 outputs data corresponding to the phase difference between the reference clock signal RCLK and the feedback clock signal FBCLK to the processing circuit 20 as comparison result data CQ. Then, the frequency control data DFC1 is generated based on the comparison result data CQ according to the phase difference, and the digital control oscillation circuit 80 generates the clock signal CLK based on the frequency control data DFC1. In this way, in the feedback loop of the PLL circuit formed by the comparison circuit 60, the processing circuit 20, the digital control oscillation circuit 80, and the frequency dividing circuit 52, the clock signal CLK is phase-locked with respect to the reference clock signal RCLK. Therefore, it becomes possible to generate a clock signal CLK with a frequency accuracy corresponding to the frequency accuracy of the reference clock signal RCLK.

Further, in FIG. 2, the comparison circuit 60 converts the phase difference between the reference clock signal RCLK and the feedback clock signal FBCLK into a digital value, and outputs the digital value as the comparison result data CQ to the processing circuit 20. Including. For example, the time digital conversion circuit 62 outputs a digital value corresponding to the time difference between the transition timing of the reference clock signal RCLK and the transition timing of the feedback clock signal FBCLK to the processing circuit 20 as comparison result data CQ which is a digital value of the phase difference. .. For example, a signal based on the reference clock signal RCLK is input to the time digital conversion circuit 62 as a start signal STA, and a signal based on the feedback clock signal FBCLK is input as a stop signal STP. Then, the time digital conversion circuit 62 outputs a digital value corresponding to the time difference between the transition timing of the start signal STA and the transition timing of the stop signal STP as the comparison result data CQ.

Specifically, for example, as shown in FIG. 4, the comparison circuit 60 includes a time digital conversion circuit 62, a start signal generation circuit 70, and a stop signal generation circuit 72. The start signal generation circuit 70 generates a start signal STA based on the reference clock signal RCLK. For example, the start signal generation circuit 70 generates a signal whose signal level changes at a transition timing such as a rising edge of the reference clock signal RCLK as a start signal STA. The start signal STA is, for example, a signal in which a pulse is generated at the transition timing of the reference clock signal RCLK.

The stop signal generation circuit 72 generates a stop signal STP based on the feedback clock signal FBCLK. For example, the stop signal generation circuit 72 generates a signal whose signal level changes at a transition timing such as a rising edge of the feedback clock signal FBCLK as a stop signal STP. The stop signal STP is, for example, a signal in which a pulse is generated at the transition timing of the feedback clock signal FBCLK.

A signal based on the feedback clock signal FBCLK may be input to the time digital conversion circuit 62 as a start signal STA, and a signal based on the reference clock signal RCLK may be input as a stop signal STP. In this case, in FIG. 4, if the start signal generation circuit 70 generates the start signal STA based on the feedback clock signal FBCLK and the stop signal generation circuit 72 generates the stop signal STP based on the reference clock signal RCLK. Good. As described above, the time digital conversion circuit 62 of the comparison circuit 60 is a signal based on the transition timing of the start signal STA, which is a signal based on one of the reference clock signal RCLK and the feedback clock signal FBCLK, and a signal based on the other clock signal. The time difference of the transition timing of the stop signal STP is measured, and the digital value corresponding to this time difference is output as the comparison result data CQ.

If the time digital conversion circuit 62 as described above is provided in the comparison circuit 60, the phase difference between the reference clock signal RCLK and the feedback clock signal FBCLK is compared, and the comparison result data CQ is output, the phase difference between these clock signals can be obtained. Accurate measurement enables the phase-locked loop operation of the PLL circuit based on the phase difference to be realized. Therefore, the clock signal CLK can be synchronized with the reference clock signal RCLK having high frequency accuracy with high accuracy, and the frequency accuracy of the clock signal CLK can be significantly improved.

FIG. 5 shows a configuration example of the digital control oscillation circuit 80. The digital control oscillation circuit 80 of FIG. 5 includes a frequency adjustment circuit 82 and a drive circuit 86. The frequency adjustment circuit 82 includes a D / A conversion circuit 84 and a variable capacitance capacitor CV.

The drive circuit 86 drives the oscillator XTAL connected via the terminals TX1 and TX2 for external connection of the circuit device 10. The drive circuit 86 realizes an oscillation circuit that oscillates the oscillator XTAL. The drive circuit 86 can be realized by, for example, a transistor such as a bipolar transistor or an active element such as a capacitor or a resistor. As the oscillation circuit, various types of oscillation circuits such as Pierce type, Colpitts type, inverter type and Hartley type can be used.

The vibrator XTAL is an element that generates mechanical vibration by an electric signal. The oscillator XTAL can be realized by a vibrating piece such as a crystal vibrating piece. For example, the oscillator XTAL can be realized by a crystal vibrating piece having a cut angle of AT cut, SC cut, or the like that vibrates by sliding in thickness. The vibrator XTAL of the present embodiment can be realized by various vibration pieces such as a vibration piece other than the thickness sliding vibration type and a piezoelectric vibration piece made of a material other than quartz. For example, as the oscillator XTAL, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) oscillator as a silicon oscillator formed by using a silicon substrate, or the like may be adopted.

Further, in FIG. 5, the frequency adjustment circuit 82 is configured by the D / A conversion circuit 84 and the variable capacitance capacitor CV. The frequency adjusting circuit 82 is a variable capacitance circuit. The D / A conversion circuit 84 performs D / A conversion of the frequency control data DFC2, and outputs the voltage DAQ obtained by the D / A conversion to one end of the variable capacitance capacitor CV. The other end of the variable capacitance capacitor CV is connected to the node on one end side of the oscillator XTAL. The variable capacitance capacitor CV is a capacitor whose capacitance value changes according to the voltage at both ends, and is, for example, a MOS capacitor or a variable capacitance diode. With such a configuration, it becomes possible to realize a digital control oscillation circuit 80 that oscillates the oscillator XTAL at a frequency corresponding to the frequency control data DFC2 to generate a clock signal CLK.

The configuration of the digital control oscillation circuit 80 is not limited to the configuration shown in FIG. 5, and various modifications can be performed. For example, in FIG. 5, the frequency adjustment circuit 82 is realized by the D / A conversion circuit 84 and the variable capacitance capacitor CV, but the present embodiment is not limited to this. For example, as the frequency adjustment circuit 82, a variable capacitance circuit including a capacitor array having a plurality of capacitors and a switch array having a plurality of switch elements is provided. Each switch element of the plurality of switch elements in the switch array is electrically connected to each capacitor of the plurality of capacitors in the capacitor array. Then, based on the frequency control data DFC2, the on / off of each switch element of the plurality of switch elements is controlled. Then, by turning the plurality of switch elements on or off in this way, the number of capacitors to which one end of the plurality of capacitors is connected to one end of the oscillator XTAL changes. As a result, the capacitance value of the variable capacitance circuit is controlled, and the capacitance value at one end of the vibrator XTAL changes. Therefore, the frequency control data DFC2 directly controls the capacitance value of the variable capacitance circuit, so that the oscillation frequency of the clock signal CLK can be controlled.

FIG. 6 is a signal waveform diagram illustrating the operation of the circuit device 10 of the present embodiment. In the synchronous mode, the switch SW1 is turned on and the switch SW2 is turned off as shown in FIGS. 2 and 6. When the switch SW1 is turned on, a feedback loop of the PLL circuit by the comparison circuit 60, the processing circuit 20, the digital control oscillation circuit 80, and the frequency dividing circuit 52 is formed, and a synchronous operation for synchronizing the clock signal CLK with the reference clock signal RCLK is formed. Is done. At this time, the frequency control data DFC1 from the digital loop filter 40 is input to the digital control oscillation circuit 80 as the frequency control data DFC2. During the synchronization period in this synchronization mode, the frequency control data DFC1 = DFC2 is finely adjusted so that the clock signal CLK is phase-locked with respect to the reference clock signal RCLK.

When the synchronous mode is switched to the output mode, the switch SW1 is turned off and the switch SW2 is turned on as shown in FIGS. 3 and 6. When the switch SW1 is turned off, the feedback loop of the PLL circuit is disconnected. When the switch SW2 is turned on, the clock signal CLK generated by the digital control oscillation circuit 80 is output to the wireless transmission unit 100 via the output circuit 54 and the terminal TCQ. In this output mode, the frequency control data DFC1 adjusted in the synchronization mode is held, and the processing circuit 20 processes the frequency control data DFC1 to output a clock signal CLK of an arbitrary frequency. become. For example, in FIG. 6, the retained frequency control data DFC1 is subjected to modulation processing based on the modulation data DM, and the frequency control data DFC2 after the modulation processing is input to the digital control oscillation circuit 80, whereby the FSK It becomes possible to continuously output the modulated clock signal CLK. By inputting the frequency control data DFC2, which is obtained by adding the modulation data DM to the frequency control data DFC1 finely adjusted in the synchronization period, to the digital control oscillation circuit 80, it becomes possible to generate a clock signal CLK with high frequency accuracy. .. Then, by providing a wireless transmission unit 100 having a transmission circuit 102 such as a power amplifier and an antenna ANT, wireless transmission of transmission data becomes possible. The modulation data DM can be managed by the processing circuit 20 which is a microcomputer, the timekeeping circuit 90 and the interface circuit 92 of FIG. 10 which will be described later. In FIG. 6, when the wireless transmission in the output mode is completed, the output mode returns to the synchronous mode, the switch SW1 is turned on, and the switch SW2 is turned off. When the switch SW1 is turned on, the clock signal CLK is synchronized with the reference clock signal RCLK, and the frequency accuracy of the clock signal CLK can be maintained with high accuracy. For example, frequency fluctuation due to temperature change or aging. Can be prevented. Further, when the switch SW2 is turned off, the clock signal CLK generated by the digital control oscillation circuit 80 is not transmitted to the wireless transmission unit 100, and the clock signal CLK is buffered by the output circuit 54. Since there is no such thing, power consumption can be reduced.

Further, the processing circuit 20 determines whether or not the clock signal CLK is synchronized with the reference clock signal RCLK in the synchronization mode. Then, after determining that they have been synchronized, the operation mode of the circuit device 10 is switched from the synchronous mode to the output mode. For example, as shown in FIG. 6, in the synchronous mode, the fluctuating frequency control data DFC1 gradually converges to a predetermined value. The processing circuit 20 monitors, for example, the frequency control data DFC1 and determines that the clock signal CLK is synchronized with the reference clock signal RCLK when the frequency control data DFC1 converges within a certain range centered on a predetermined value. .. Then, after determining that the processing circuit 20 has been synchronized, the synchronization mode is switched to the output mode, the frequency control data DFC 1 is modulated, and the modulated frequency control data DFC 2 is output to the digital control oscillation circuit 80. To do. In this way, the operation mode is switched from the synchronization mode to the output mode after the appropriate frequency control data DFC1 that synchronizes the clock signal CLK with the reference clock signal RCLK is generated. Therefore, it becomes possible to perform modulation processing on the frequency control data DFC1 when synchronized with the reference clock signal RCLK and output the modulated clock signal CLK for wireless transmission. The processing circuit 20 holds the frequency control data DFC1 when the clock signal CLK is synchronized with the reference clock signal RCLK in the synchronization mode. As the timing of this holding, for example, the processing circuit 20 holds the clock signal in the reference clock signal RCLK. It is possible to adopt the timing when it is determined that the CLK is synchronized.

2. FLL
FIG. 7 shows another configuration example of the circuit device 10 of the present embodiment. In FIG. 7, the comparison circuit 60 performs frequency comparison comparing the frequency of the reference clock signal RCLK and the frequency of the feedback clock signal FBCLK, and outputs the comparison result data CQ obtained by the frequency comparison to the processing circuit 20. In FIG. 7, the clock signal CLK is input to the comparison circuit 60 as the feedback clock signal FBCLK via the switch SW1. The comparison circuit 60, the processing circuit 20, and the digital control oscillation circuit 80 having such a configuration realize an FLL circuit that synchronizes the frequencies of the reference clock signal RCLK and the clock signal CLK. This makes it possible to realize frequency synchronization in which the frequency of the clock signal CLK is set to a frequency corresponding to the frequency of the reference clock signal RCLK. That is, in the feedback loop of the FLL circuit formed by the comparison circuit 60, the processing circuit 20, and the digitally controlled oscillation circuit 80, the clock signal CLK is frequency-synchronized with the reference clock signal RCLK, and the frequency of the reference clock signal RCLK is synchronized. It becomes possible to generate a clock signal CLK with a frequency accuracy corresponding to the accuracy. By synchronizing the frequency of the clock signal CLK with the reference clock signal RCLK having high frequency accuracy in this way, it becomes possible to output the clock signal CLK with high frequency accuracy.

Further, in FIG. 7, the comparison circuit 60 includes a frequency counter 64. The frequency counter 64 performs count processing based on the reference clock signal RCLK and the feedback clock signal FBCLK, and outputs count data. For example, the frequency counter 64, which is a counting circuit, performs counting processing based on the reference clock signal RCLK and the feedback clock signal FBCLK which is the clock signal CLK, and outputs count data. Then, the comparison circuit 60 outputs the comparison result data CQ based on the count data to the processing circuit 20. As an example, the frequency counter 64 counts the number of pulses of the other clock signal in the period set by one clock signal of the reference clock signal RCLK and the feedback clock signal FBCLK, and outputs the count data obtained by the count. .. For example, in the period set based on the reference clock signal RCLK, the number of pulses of the feedback clock signal FBCLK is counted, and the count data obtained by the counting is output. Alternatively, the count data may be output by counting the number of pulses of the reference clock signal RCLK in the period set based on the feedback clock signal FBCLK. The period set by one of the reference clock signal RCLK and the feedback clock signal FBCLK is, for example, the period from the initial value to the predetermined value of the count number by one clock signal.

By providing such a frequency counter 64, the frequency of one clock signal of the reference clock signal RCLK and the feedback clock signal FBCLK can be measured based on the other clock signal. As a result, frequency comparison for comparing the frequency of the reference clock signal RCLK and the frequency of the feedback clock signal FBCLK can be realized by the count processing of the frequency counter 64, and the comparison result data CQ obtained by the frequency comparison is sent to the processing circuit 20. You will be able to output.

As shown in FIG. 8, the time digital conversion circuit 67 may be further provided in the comparison circuit 60 in addition to the frequency counter 64. For example, in FIG. 8, the comparison circuit 60 includes a frequency counter 64, a time digital conversion circuit 67, and an arithmetic circuit 68. The frequency counter 64 performs counting processing based on the reference clock signal RCLK and the feedback clock signal FBCLK. The time digital conversion circuit 67 outputs the time difference information TMD between the transition timing of the start signal STA and the transition timing of the stop signal STP from the frequency counter 64. The arithmetic circuit 68 performs arithmetic processing based on the count data CntM and CntT from the frequency counter 64 and the time difference information TMD from the time digital conversion circuit 67, and outputs the comparison result data CQ of the frequency comparison.

The frequency counter 64 performs counting processing based on the reference clock signal RCLK and the feedback clock signal FBCLK, and outputs the count data CntM and CntT obtained by the counting processing. Specifically, the frequency counter 64 includes a first counter 65 and a second counter 66. The first counter 65 performs count processing based on the feedback clock signal FBCLK and outputs count data CntM. The second counter 66 performs count processing based on the reference clock signal RCLK and outputs count data CntT.

The calculation circuit 68 obtains the comparison result data CQ by performing a calculation based on the time difference information TMD and the count data CntM and CntT. The count data CntM corresponds to the time having the period of the feedback clock signal FBCLK as the resolution, and the count data CntT corresponds to the time having the period of the reference clock signal RCLK as the resolution. In addition to these, the arithmetic circuit 68 can accurately determine the period of the feedback clock signal FBCLK based on the period of the reference clock signal RCLK by using the time difference information TMD measured with a time resolution smaller than the clock period. The frequency can be determined by the reciprocal of the period.

FIG. 9 is a signal waveform diagram illustrating the operation of the comparison circuit 60 of FIG. The first counter 65 counts the number of pulses of the feedback clock signal FBCLK, and transitions the start signal STA in an Nm + 1 count cycle. The first counter 65 outputs the count value Nm as the count data CntM. Nm is a predetermined count value, and may be set in advance, for example, or may be set by register setting.

Specifically, the first counter 65 resets the count value to 0 at the transition timing of the feedback clock signal FBCLK and shifts the start signal STA from the low level to the high level. The first counter 65 counts the number of pulses of the feedback clock signal FBCLK to the count value Nm, resets the count value to 0 again at the transition timing of the feedback clock signal FBCLK, and shifts the start signal STA from the low level to the high level. .. The start signal STA has a high level for, for example, one cycle of the feedback clock signal FBCLK, but the number of cycles may be arbitrary.

After the start signal STA has transitioned, the second counter 66 transitions the stop signal STP at the transition timing of the reference clock signal RCLK. The second counter 66 counts the number of pulses of the reference clock signal RCLK in the period from the transition of the stop signal STP to the next transition of the stop signal STP, and outputs the count value Nt as the count data CntT.

Specifically, the second counter 66 shifts the signal FlgM from the low level to the high level at the second falling edge of the reference clock signal RCLK after the start signal STA transitions from the low level to the high level. At the falling edge of the next reference clock signal RCLK, the signal FlgM is transitioned from high level to low level. The signal FlgM is an internal signal of the second counter 66. The second counter 66 shifts the stop signal STP from the low level to the high level at the rising edge of the reference clock signal RCLK when the signal FlgM is at a high level.

The second counter 66 resets the count value to 0 at the timing of transitioning the stop signal STP from the low level to the high level. The second counter 66 counts the number of pulses of the reference clock signal RCLK until the timing at which the stop signal STP is next transitioned to a high level, and outputs the count value Nt at that time as count data CntT.

The time digital conversion circuit 67 measures the time difference between the transition timing of the start signal STA and the transition timing of the stop signal STP. Since the start signal STA transitions periodically, the time difference is measured corresponding to each transition timing. Let the time difference of this time series be tp1 and tp2. The time digital conversion circuit 67 outputs the time difference information TMD indicating the time difference tp1 and tp2.

The arithmetic circuit 68 obtains the frequency fm of the feedback clock signal FBCLK by the following equations (1) and (2). T0 is the period of the reference clock signal RCLK, which is a known value. Tm is the period of the feedback clock signal FBCLK, and its reciprocal is the frequency fm. Then, the arithmetic circuit 68 outputs the comparison result data CQ based on the frequency f0 = 1 / T0 of the reference clock signal RCLK and the frequency fm of the feedback clock signal FBCLK. For example, the frequency ratio data of the frequency f0 and the frequency fm is output as the comparison result data CQ.

Tm = {T0 (Nt + 1) + (tp1-tp2)} / Nm + 1 (1)

fm = 1 / Tm (2)

According to the comparison circuit 60 having the configuration described with reference to FIGS. 8 and 9, the frequency counter 64 measures the period Tm of the feedback clock signal FBCLK with reference to the period T0 of the reference clock signal RCLK, but the time digital conversion circuit 67 further measures the period Tm. , The time difference tp1 and tp2 are measured with a resolution smaller than the period T0. As a result, the arithmetic circuit 68 can calculate the period Tm of the feedback clock signal FBCLK with a resolution smaller than the period T0, can obtain the accurate frequency fm of the feedback clock signal FBCLK, and process the accurate comparison result data CQ of the frequency. It becomes possible to output to the circuit 20.

3. 3. Sleep Mode FIG. 10 shows another detailed configuration example of the circuit device 10 of the present embodiment. In the circuit device 10 of FIG. 10, a timekeeping circuit 90 and an interface circuit 92 are further provided. Note that this embodiment is not limited to the configuration shown in FIG. 10, and for example, only one of the timing circuit 90 and the interface circuit 92 may be provided.

The timekeeping circuit 90 is a circuit that performs timekeeping processing and the like, and is a circuit for managing a schedule. This timekeeping circuit 90 can be realized by, for example, an RTC (Real Time Clock) circuit. The timekeeping circuit 90 may be an RTC circuit provided in the microcomputer. Then, the timekeeping circuit 90 gives a mode setting instruction for setting the operation mode of the circuit device 10. For example, the timekeeping circuit 90 outputs mode setting instructions for the synchronization mode and the output mode. The timekeeping circuit 90 also gives a mode setting instruction for the sleep mode, which will be described later. The mode setting instruction indicates in which operation mode the circuit device 10 is operated, and is realized by, for example, the timekeeping circuit 90 outputting a mode setting signal or mode setting data.

The interface circuit 92 is a circuit for performing interface processing with the outside. As an example, the interface circuit 92 can be realized by a serial interface circuit such as SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit). Alternatively, the interface circuit 92 may be a serial interface circuit using a differential signal or a parallel interface circuit. Then, the interface circuit 92 receives the mode setting instruction from the outside. For example, the interface circuit 92 receives commands for mode setting instructions such as synchronization mode and output mode from the outside by serial interface communication such as SPI and I2C.

Then, the processing circuit 20 sets the operation mode of the circuit device 10 to the synchronous mode and then to the output mode based on the mode setting instruction. For example, the processing circuit 20 sets the operation mode to the synchronous mode and then to the output mode based on the mode setting instruction by the scheduling operation of the timekeeping circuit 90. Alternatively, the processing circuit 20 sets the operation mode to the synchronous mode and then to the output mode based on the mode setting instruction input from the outside via the interface circuit 92. For example, as described above, the processing circuit 20 determines whether or not the clock signal CLK is synchronized with the reference clock signal RCLK in the synchronization mode. In this case, the processing circuit 20 operates according to the mode setting instruction from the timekeeping circuit 90 and the mode setting instruction input via the interface circuit 92 after determining that the clock signal CLK is synchronized with the reference clock signal RCLK. Switch the mode from synchronous mode to output mode. In this way, the operation mode is switched from the synchronous mode to the output mode according to the scheduling by the timekeeping operation of the timekeeping circuit 90, or the operation mode is synchronized according to the mode setting instruction input from the outside via the interface circuit 92. It is possible to switch from mode to output mode. Then, by switching from the synchronous mode to the output mode according to the mode setting instruction in this way, the clock signal CLK for wireless transmission can be output to the wireless transmission unit 100, and the transmission data can be wirelessly transmitted. In this way, at a desired timing, the operation mode is switched from the synchronous mode to the output mode by the mode setting instruction from the timekeeping circuit 90 or the mode setting instruction from the outside via the interface circuit 92, and the transmission data is wirelessly transmitted. Will be done.

As an example, the timekeeping circuit 90 gives a mode setting instruction to switch from the synchronous mode to the output mode, for example, once or a plurality of times a day according to a schedule. As a result, wireless transmission is performed once or a plurality of times a day. Taking IOT (Internet of Things) as an example, the detection data of the sensor is set to 1 by the wireless transmitter 200 of the present embodiment by instructing the mode setting to switch to the output mode once or multiple times a day. It will be transmitted wirelessly to the outside once or multiple times a day. Alternatively, when an external device gives a mode setting instruction at a desired timing, the mode setting instruction is input via the interface circuit 92, the synchronous mode is switched to the output mode at the desired timing, and wireless transmission is performed. Will come to be.

Further, the circuit device 10 of the present embodiment can include a sleep mode as an operation mode. FIG. 11 is a signal waveform diagram illustrating the operation of the circuit device 10 of the present embodiment in that case. In FIG. 11, for example, based on a mode setting instruction from the timekeeping circuit 90 or an external mode setting instruction via the interface circuit 92, the circuit device 10 is set to the sleep mode in which the circuit device 10 is put into a sleep state, and then the synchronous mode and the output The operation mode is set in the order of mode and sleep mode.

Specifically, in FIG. 11, after the synchronization mode is set and the synchronization operation is performed, the sleep mode is set. In sleep mode, switches SW1 and SW2 are both turned off. Then, as will be described later in FIG. 14, most of the circuits of the circuit device 10 are set to a state of disable or power saving. Then, when shifting to the output mode, as shown in FIG. 11, the sleep mode is first switched to the synchronous mode, and then the synchronous mode is switched to the output mode. In this way, after the sleep mode, the synchronization operation of the clock signal CLK to the reference clock signal RCLK in the synchronization mode is first performed. After that, the mode is switched to the output mode, and the clock signal CLK based on the frequency control data DFC1 held in the synchronous mode is output. For example, it becomes possible to output a modulated clock signal CLK for wireless transmission. Then, as shown in FIG. 11, the operation mode is switched to the sleep mode after the output mode. By doing so, the low power consumption operation of the circuit device 10 becomes possible. Then, when shifting from this sleep mode to the output mode, as described above, the sleep mode is first switched to the synchronous mode, the clock signal CLK is synchronized with the reference clock signal RCLK, and then the synchronous mode is performed. The mode is switched to the output mode, and wireless transmission is performed. In this way, by switching the operation mode in the order of sleep mode, synchronization mode, output mode, and sleep mode, the clock signal CLK set to higher frequency accuracy by the synchronization mode while reducing the power consumption of the circuit device 10. Will be used to enable wireless transmission.

Further, in each operation mode such as the synchronization mode, the output mode, and the sleep mode of the present embodiment, each circuit of the circuit device 10 is set to a disable or power saving state. The disable setting is realized by shutting off the power supply to the circuit, turning off the current flowing through the circuit, turning off the transistors that make up the circuit, and so on. The power saving setting is realized by limiting the power supply and current supplied to the circuit, setting the circuit operation so as to operate with low power consumption, and the like.

FIG. 12 is an explanatory diagram of a state of disable or power saving in the synchronous mode. In the synchronous mode, the wireless transmitter 100 is set to a state of disable or power saving. In this way, in the synchronization mode in which only the synchronization operation of the clock signal CLK with respect to the reference clock signal RCLK is performed and the wireless transmission is not performed, the wireless transmission unit 100 operates wastefully and wastes power. It is possible to prevent the situation where it ends up. Further, in the synchronous mode, the output circuit 54 is set to a state of disable or power saving. Since the output circuit 54 buffers and outputs, for example, a high frequency clock signal CLK, it consumes a large amount of power. Therefore, in the synchronous mode in which it is not necessary to output the clock signal CLK to the wireless transmission unit 100, setting the output circuit 54 to a disable or power saving state prevents a situation in which power is wasted. .. Further, in the synchronous mode, the modulation data output unit 32 and the interface circuit 92 are also set to a diseasable or power saving state to prevent unnecessary power consumption.

FIG. 13 is an explanatory diagram of a state of disable or power saving in the output mode. In the output mode, the comparison circuit 60 is set to a disable or power saving state. For example, in the output mode, the synchronous operation by the PLL circuit or the FLL circuit is unnecessary, and the processing circuit 20 modulates the clock signal CLK by performing the modulation processing on the frequency control data DFC1 held during the synchronous operation in the synchronous mode. It is carried out. Therefore, since it is not necessary to operate the comparison circuit 60 used in the synchronous mode in the output mode, the comparison circuit 60 is set to a disable or power saving state to prevent unnecessary power consumption. In particular, when the time digital conversion circuits 62 and 67 are provided in the comparison circuit 60 as shown in FIGS. 2 to 4 and 8, the time digital conversion circuits 62 and 67 whose power consumption is larger than those of other circuits are dissected. By setting to the Able or power saving state, the power consumption in the output mode can be effectively suppressed.

Further, in the output mode, since the synchronous operation by the PLL circuit and the FLL circuit is unnecessary, the digital loop filter 40 and the frequency dividing circuit 52 are also set to the disable or power saving state. As a result, wasteful power consumption in the output mode can be prevented. In the output mode, it is necessary to hold the frequency control data DFC1 at the time of synchronous operation. Therefore, for example, the holding circuits 42 of FIGS. 2 and 3 are supplied with power as usual to obtain the frequency control data. The DFC1 can be held properly.

FIG. 14 is an explanatory diagram of a state of disable or power saving in the sleep mode. In the sleep mode, for example, the circuits of the circuit device 10 other than the timekeeping circuit 90 are set to a disable or power saving state. In this way, most of the circuits of the circuit device 10 can be set to the disable or power saving state, and the power consumption in the sleep mode can be significantly reduced. On the other hand, the timekeeping circuit 90 is not set to the disable or power saving state even in the sleep mode, but is set to the normal operation mode, so that the sleep mode is switched to the synchronous mode and the output is output as described in FIG. Operation control that shifts to the mode becomes possible. Even in the sleep mode, a part or all of the interface circuit 92 may be set to the normal operation mode without being set to the disable or power saving state. In this way, the mode setting instruction from the outside can be properly received in the sleep mode, and the operation control such as switching from the sleep mode to the synchronous mode and shifting to the output mode by the mode setting instruction from the outside can be performed. It will be possible.

4. Time-digital conversion circuit Next, a configuration example of the time-digital conversion circuit 62 will be described with reference to FIGS. 15 to 18. Since the time digital conversion circuit 67 described with reference to FIG. 8 has the same configuration, detailed description thereof will be omitted. FIG. 15 is a first configuration example of the time digital conversion circuit 62. The time digital conversion circuit 62 includes a measurement circuit 230, a signal generation circuit 240, and an integration processing circuit 260.

The signal generation circuit 240 generates a signal for integration processing based on the start signal STA which is the first signal, the stop signal STP which is the second signal, and the clock signal CLK. In the first configuration example, the clock signal CLK is used as a reference clock signal that serves as a reference for time measurement. The signal generation circuit 240 includes integration period signal generation circuits 241 and 243, and polarity switching signal generation circuits 242 and 244. The clock signal used by the time-digital conversion circuit 62 is not limited to, for example, the clock signal generated by the digital control oscillation circuit 80. For example, a vibrator different from the vibrator XTAL described in FIG. 5 is provided to perform time digital. The clock signal CLK used by the conversion circuit 62 may be generated.

The integration period signal generation circuit 241 generates the signal SINT1 based on the start signal STA. The polarity switching signal generation circuit 242 generates signals SPH1 and SPH2 based on the signal SINT1 and the clock signal CLK. The integration period signal generation circuit 243 generates the signal SINT2 based on the stop signal STP. The polarity switching signal generation circuit 244 generates signals SPH3 and SPH4 based on the signal SINT2 and the clock signal CLK. The signals SINT1 and SINT2 are integration period signals, and the signals SPH1, SPH2, SPH3, and SPH4 are integration polarity switching signals.

The integration processing circuit 260 outputs voltages QA1 to QA4, which are the first to fourth integrated values, by performing integration processing based on the signals SINT1, SPH1, SPH2, SINT2, SPH3, and SPH4. The voltages QA1 and QA2 indicate the phases corresponding to the time difference between the transition timings of the start signal STA and the clock signal CLK. The voltages QA3 and QA4 indicate the phases corresponding to the time difference between the transition timings of the stop signal STP and the clock signal CLK. The integrator processing circuit 260 includes integrator circuits 261 to 264.

The integrator circuit 261 performs the first integration process based on the signals SINT1 and SPH1. The integrator circuit 262 performs the second integration process based on the signals SINT1 and SPH2. The integrator circuit 263 performs the third integration process based on the signals SINT2 and SPH3. The integrator circuit 264 performs the fourth integration process based on the signals SINT2 and SPH4.

The measurement circuit 230 performs A / D conversion of each of the voltages QA1 to QA4 which are the results of the first to fourth integration processes, and calculates the time difference information TMD from the A / D conversion value. The time difference information TMD indicates the time difference between the transition timings of the start signal STA and the stop signal STP.

FIG. 16 is a signal waveform diagram illustrating the operation of the first configuration example of the time digital conversion circuit 62. Here, the operation of obtaining the voltages QA1 and QA2 indicating the phase of the start signal STA will be described as an example.

The integration period signal generation circuit 241 shifts the signal SINT1 from the low level to the high level at the transition timing of the start signal STA, maintains the signal SINT1 at the high level during the integration period TP1, and then lowers the signal SINT1. The length of the integration period TP1 may be four times or more the period of the clock signal CLK, and may not be an integral multiple of the period of the clock signal CLK.

The phase detection range RDET of the start signal STA corresponds to one cycle of the clock signal CLK. When the start signal STA transitions, the period of the clock signal CLK to which the transition timing belongs becomes the detection range RDET.

The polarity switching signal generation circuit 242 shifts the signal SPH1 from the low level to the high level at the timing synchronized with the clock signal CLK in the integration period TP1. The transition timing of the signal SPH1 is synchronized from the rising edge of the clock signal CLK in the detection range RDET to the rising edge after the number of clocks PCI. The number of clocks PCI may be set arbitrarily. In FIG. 16, PCI = 6.

It is assumed that the transition timing of the signal SPH1 is regarded as a phase reference, that is, 0 degree. This corresponds to considering the phase of the start signal STA as 0 degree when the transition timing of the start signal STA coincides with the rising edge of the clock signal CLK. In FIG. 16, the length of the integration period TP1 corresponds to 24 cycles of the clock signal CLK. Assuming that the integration period TP1 is 360 degrees in phase, one period of the clock signal CLK corresponds to 15 degrees in phase. Each pulse of the clock signal CLK in FIG. 16 is numbered with the transition timing of the signal SPH1 as a reference "0", and if the number is different by 1, the phase is different by 15 degrees.

The polarity switching signal generation circuit 242 shifts the signal SPH2 from the low level to the high level after the clock number NCK of the clock signal CLK from the transition timing of the signal SPH1 in the integration period TP1. In FIG. 16, NCK = 6, and the phases of the signal SPH1 and the signal SPH2 are different by 90 degrees. This corresponds to obtaining two integral values whose phase is shifted by 90 degrees.

The integration period TP1 is divided into a period TPP1 and a period TPM1 according to the transition timing of the signal SPH1. The integrator circuit 261 performs the first integration process at the first polarity in the period TPP1 and performs the first integration process at the second polarity which is opposite to the first polarity in the period TPM1. In FIG. 16, the first polarity is positive and the second polarity is negative. The integrator circuit 261 outputs the voltage QA1 of the integrator result.

The integration period TP1 is divided into a period TPP2 and a period TPM2 according to the transition timing of the signal SPH2. The integrator circuit 262 performs the second integration process at the first polarity in the period TPP2, and performs the second integration process at the second polarity in the period TPM2. The integrator circuit 262 outputs the voltage QA2 of the integrator result.

In the above, the operation of obtaining the voltages QA1 and QA2 indicating the phase of the start signal STA has been described, but the voltages QA3 and QA4 indicating the phase of the stop signal STP are also obtained by the same operation.

The time difference between the transition timings of the start signal STA and the stop signal STP is defined as TDF. The measurement circuit 230 obtains the time difference TDF by TDF = TC × (QA3 / AZ2-QA1 / AZ1). TC is the period of the clock signal CLK, and AZ1 = QA2-QA1 and AZ2 = QA4-QA3. AZ1 and AZ2 are constant regardless of the value of the time difference TDF. In FIG. 16, the integration period TP1 is an unknown number, and offsets due to this unknown number occur in QA1 / AZ1 and QA3 / AZ2. However, since the integration period TP1 when obtaining QA1 and QA3 is common, the offset of QA1 / AZ1 and the offset of QA3 / AZ2 have the same value and are canceled by subtraction.

FIG. 17 is a second configuration example of the time digital conversion circuit 62. The time digital conversion circuit 62 includes ring oscillators 271 and 281, a measurement circuit 291 and a reference clock counter 292 and adjustment circuits 272 and 282.

In the second configuration example, the time digital conversion circuit 62 has a measurement mode and an adjustment mode. The measurement mode is a mode for measuring the time difference, and the adjustment mode is a mode for adjusting the oscillation frequencies of the ring oscillators 271 and 281.

First, the measurement mode will be described. The ring oscillator 271 enables the oscillation loop at the transition timing of the start signal STA. As a result, the ring oscillator 271 starts oscillating and generates the clock signal CLKS. The ring oscillator 281 enables the oscillation loop at the transition timing of the stop signal STP. As a result, the ring oscillator 281 starts oscillating and generates the clock signal CLKF. Let the frequency of the clock signal CLKS be f1 and the frequency of the clock signal CLKF be f2. f2 is higher than f1.

The measurement circuit 291 obtains the time difference information TMD based on the clock signal CLKS and the clock signal CLKF. The time difference information TMD indicates the time difference between the transition timings of the start signal STA and the stop signal STP. The method for obtaining the time difference information TMD will be described later with reference to FIG.

Next, the adjustment mode will be described. In the second configuration example, the clock signal CLK is used as a reference clock signal that serves as a reference for the oscillation frequencies of the ring oscillators 271 and 281. The reference clock counter 292 counts the number of clocks of the clock signal CLK and outputs an enable signal ENA that becomes active during the period of counting the given number of clocks.

The adjustment circuit 272 counts the number of clocks of the clock signal CLKS during the period when the enable signal ENA is active. The adjustment circuit 272 integrates the difference between the count value and the first target value, and outputs the control data FCS obtained by the integration. The first target value is a value for setting the oscillation frequency of the ring oscillator 271. The ring oscillator 271 oscillates at an oscillation frequency corresponding to the control data FCS. For example, a variable capacitance circuit is provided as a load of the oscillation loop of the ring oscillator 271, and the capacitance value of the variable capacitance circuit is controlled by the control data FCS. In this way, the oscillation frequency of the ring oscillator 271 is adjusted.

The adjustment circuit 282 counts the number of clocks of the clock signal CLKF during the period when the enable signal ENA is active. The adjustment circuit 272 integrates the difference between the count value and the second target value, and outputs the control data FCF obtained by the integration. The second target value is a value for setting the oscillation frequency of the ring oscillator 281. The ring oscillator 281 oscillates at an oscillation frequency corresponding to the control data FCF. For example, a variable capacitance circuit is provided as a load of the oscillation loop of the ring oscillator 281, and the capacitance value of the variable capacitance circuit is controlled by the control data FCF. In this way, the oscillation frequency of the ring oscillator 281 is adjusted.

When the time digital conversion circuit 62 is set to the measurement mode after the adjustment mode, the control data FCS and FCF obtained in the adjustment mode are input to the ring oscillators 271 and 281. As a result, the ring oscillators 271 and 281 oscillate at the oscillation frequency adjusted in the adjustment mode, and the measurement circuit 291 can measure the time using the clock signals CLKS and CLKF with accurate frequencies.

FIG. 18 is a signal waveform diagram illustrating the operation of the second configuration example of the time digital conversion circuit 62. FIG. 18 shows a signal waveform diagram in the measurement mode.

The measurement circuit 291 compares the phases of the clock signal CLKS and the clock signal CLKF, and changes the phase comparison result signal QP from high level to low level when it is determined that the phase of the clock signal CLKS and the phase of the clock signal CLKF are interchanged. The phase comparison result signal QP is an internal signal of the measurement circuit 291.

The measurement circuit 291 counts the number of clocks of the clock signal CLKS. Let this count value be CTS. Further, the measurement circuit 291 counts the number of clocks of the clock signal CLKF. Let this count value be CTF.

The measurement circuit 291 acquires the count values CTS and CTF at the falling edge of the phase comparison result signal QP. Let this count value be N1 and N2. Assuming that the period of the clock signal CLKS is Δt1 = 1 / f1 and the period of the clock signal CLKF is Δt2 = 1 / f2, the difference is the resolution Δt = | Δt1-Δt2 |. Assuming that N3 = N1-N2, the measurement circuit 291 obtains the time difference between the transition timings of the start signal STA and the stop signal STP by N3 × Δt1 + N2 × Δt. In FIG. 18, since N1 = 5, N2 = 4, and N3 = 1, the time difference is Δt1 + 4 × Δt.

5. Oscillator, Electronic Equipment FIG. 19 shows a configuration example of the oscillator 4 of the present embodiment. The oscillator 4 includes the circuit device 10 of this embodiment and the oscillator XTAL. Then, as described with reference to FIG. 5, the digitally controlled oscillator circuit 80 of the circuit device 10 generates the clock signal CLK using the vibrator XTAL. An oscillator 4 having such a configuration can realize a wireless transmitter 200 that generates a clock signal CLK synchronized with the reference clock signal RCLK and outputs the generated clock signal CLK as a modulated clock signal for wireless transmission. Become.

Specifically, the oscillator 4 has an oscillator XTAL, a circuit device 10 which is a semiconductor chip, and a package 15 which houses the oscillator XTAL and the circuit device 10. The package 15 is formed of, for example, ceramic or the like, and has a storage space inside, and the vibrator XTAL and the circuit device 10 are housed in this storage space. The accommodation space is hermetically sealed and is preferably in a reduced pressure state, which is close to vacuum. The package 15 can suitably protect the oscillator XTAL and the circuit device 10 from impact, dust, heat, humidity and the like.

Package 15 has a base 16 and a lid 17. Specifically, the package 15 is composed of a base 16 that supports the vibrator XTAL and the circuit device 10, and a lid 17 that is joined to the upper surface of the base 16 so as to form a storage space between the base 16 and the base 16. There is. The oscillator XTAL is supported by a step portion provided inside the base 16 via a terminal electrode. Further, the circuit device 10 is arranged on the inner bottom surface of the base 16. Specifically, the circuit device 10 is arranged so that the active surface faces the inner bottom surface of the base 16. The active surface is a surface on which the circuit element of the circuit device 10 is formed. Further, bumps are formed on the pads of the circuit device 10. The circuit device 10 is then supported on the inner bottom surface of the base 16 via conductive bumps. The conductive bump is, for example, a metal bump, and the vibrator XTAL and the circuit device 10 are electrically connected via the bump, the internal wiring of the package 15, the terminal electrode, and the like. Further, the circuit device 10 is electrically connected to the external terminals 18 and 19 of the oscillator 4 via bumps and internal wiring of the package 15. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to an external device via external wiring. The external wiring is, for example, wiring formed on a circuit board on which an external device is mounted. As a result, the clock signal CLK can be output to an external device, and the reference clock signal RCLK can be input from a GNSS, a network receiver, or the like.

FIG. 20 shows a configuration example of the electronic device 500 of the present embodiment. The electronic device 500 includes the circuit device 10 of the present embodiment and the processing device 520 that controls the circuit device 10. Further, the electronic device 500 can include a communication interface 510, an operation interface 530, a display unit 540, and a memory 550.

The electronic device 500 includes, for example, a sensor device, a measuring device that measures physical quantities such as distance, time, flow velocity, or flow rate, a biological information measuring device that measures biological information, a portable device for an electronic key system, and an in-vehicle device mounted on a vehicle. A device or a network-related device such as a base station or a router. A sensor device is a device that has a sensor and detects various physical information. The biological information measuring device is, for example, an ultrasonic measuring device, a pulse wave meter, a blood pressure measuring device, or the like. The on-board unit is, for example, a device mounted on a vehicle. The electronic device 500 includes wearable devices such as head-mounted display devices and clock-related devices, robots, printing devices, projection devices, mobile information terminals such as smartphones, content providing devices for distributing content, and digital cameras or video cameras. It may be a video device such as.

The communication interface 510 includes a wireless transmission unit 100 that wirelessly transmits transmission data. Further, the communication interface 510 may include a wireless receiving unit that receives received data wirelessly. The processing device 520 performs control processing of the electronic device 500, various digital processing of data transmitted and received via the communication interface 510, and the like. The function of the processing device 520 can be realized by a processor such as a microcomputer. The operation interface 530 is for the user to perform an input operation, and can be realized by an operation button, a touch panel display, or the like. The display unit 540 displays various types of information, and can be realized by a display such as a liquid crystal or an organic EL. The memory 550 stores data, and its function can be realized by a semiconductor memory such as a RAM or a ROM.

As described above, the circuit device of the present embodiment includes a processing circuit for generating frequency control data and a synchronization circuit having a digitally controlled oscillation circuit for generating a clock signal of an oscillation frequency corresponding to the frequency control data. .. Then, in the synchronization mode, the synchronization circuit synchronizes the clock signal generated by the digital control oscillation circuit with the reference clock signal input from the outside. In the output mode, the processing circuit performs modulation processing on the frequency control data, and the synchronization circuit transmits the clock signal generated by the digital control oscillation circuit based on the modulated frequency control data for the modulated wireless transmission. Output as a clock signal.

In the circuit device of the present embodiment, in the synchronization mode, the clock signal generated based on the frequency control data is synchronized with the reference clock signal. Then, in the output mode, the frequency control data is modulated, and the clock signal generated based on the modulated frequency control data is output as a modulated clock signal for wireless transmission. Therefore, it is possible to generate a clock signal for wireless transmission with high frequency accuracy synchronized with the reference clock signal by a circuit device having a simple configuration without providing a communication format such as a preamble.

Further, in the present embodiment, the processing circuit may hold the frequency control data when the clock signal is synchronized with the reference clock signal in the synchronization mode, and may perform the modulation processing on the held frequency control data in the output mode.

In this way, the frequency control data when synchronized with the reference clock signal can be modulated and output as a clock signal for wireless transmission.

Further, in the present embodiment, the synchronization circuit may include a comparison circuit that compares the reference clock signal with the feedback clock signal based on the clock signal and outputs the comparison result data obtained by the comparison to the processing circuit.

If such a comparison circuit is provided, frequency control data corresponding to the comparison result data of the reference clock signal and the feedback clock signal based on the clock signal can be generated, and a clock signal having a frequency corresponding to the frequency control data can be generated. Will be.

Further, in the present embodiment, the processing circuit may include a digital loop filter that performs digital loop filter processing on the comparison result data to generate frequency control data.

By providing such a digital loop filter, it becomes possible to set the loop response characteristic in the feedback loop formed by the comparison circuit, the processing circuit, the digital control oscillation circuit, and the like, and set the synchronization characteristic in the synchronization mode.

Further, in the present embodiment, the comparison circuit may perform phase comparison comparing the phase of the reference clock signal and the phase of the feedback clock signal, and output the comparison result data obtained by the phase comparison to the processing circuit.

In this way, in the feedback loop formed by the comparison circuit, the processing circuit, the digitally controlled oscillation circuit, etc., the clock signal is phase-locked with respect to the reference clock signal, and corresponds to the frequency accuracy of the reference clock signal. It becomes possible to generate a clock signal with frequency accuracy.

Further, in the present embodiment, the comparison circuit may include a time digital conversion circuit that converts the phase difference between the reference clock signal and the feedback clock signal into a digital value and outputs the digital value as comparison result data to the processing circuit.

If such a time-digital conversion circuit is provided, the phase difference between the reference clock signal and the feedback clock signal can be accurately measured, and a phase-locked loop operation based on the phase difference can be realized.

Further, in the present embodiment, the comparison circuit may perform frequency comparison comparing the frequency of the reference clock signal and the frequency of the feedback clock signal, and output the comparison result data obtained by the frequency comparison to the processing circuit.

In this way, in the feedback loop formed by the comparison circuit, the processing circuit, the digitally controlled oscillation circuit, etc., the clock signal is frequency-synchronized with the reference clock signal, and corresponds to the frequency accuracy of the reference clock signal. It becomes possible to generate a clock signal with frequency accuracy.

Further, in the present embodiment, the comparison circuit has a frequency counter that performs count processing based on the reference clock signal and the feedback clock signal and outputs count data, and even if the comparison result data based on the count data is output to the processing circuit. Good.

By providing such a frequency counter, the frequency of one clock signal of the reference clock signal and the feedback clock signal can be measured based on the other clock signal, and the frequency comparison between the reference clock signal and the feedback clock signal can be performed. This can be achieved by counting the frequency counter.

Further, in the present embodiment, the comparison circuit may be set to the disabled or power saving state in the output mode.

In this way, the comparison circuit used in the synchronous mode is set to the disabled or power saving state in the output mode, so that the power consumption in the output mode can be effectively suppressed.

Further, in the present embodiment, the synchronization circuit includes a first switch provided between the digital control oscillation circuit and the comparison circuit, and the first switch may be turned on in the synchronization mode and turned off in the output mode.

In this way, when the first switch is turned on in the synchronization mode, a feedback loop is formed by the comparison circuit, processing circuit, digital control oscillation circuit, etc., and a synchronization operation that synchronizes the clock signal with the reference clock signal is realized. become able to.

Further, in the present embodiment, the processing circuit determines whether or not the clock signal is synchronized with the reference clock signal in the synchronization mode, and after determining that the clock signal is synchronized, switches the operation mode of the circuit device from the synchronization mode to the output mode. May be good.

In this way, the operation mode can be switched from the synchronization mode to the output mode after the appropriate frequency control data for synchronizing the clock signal with the reference clock signal is generated.

Further, the present embodiment includes a timekeeping circuit that outputs a mode setting instruction for setting the operation mode of the circuit device, or an interface circuit that receives the mode setting instruction from the outside, and the processing circuit is a circuit device based on the mode setting instruction. The operation mode of may be set to the output mode after being set to the synchronous mode.

In this way, the operation mode can be switched from the synchronous mode to the output mode according to the scheduling by the timekeeping operation of the timekeeping circuit, or the operation mode can be changed from the synchronous mode according to the mode setting instruction input from the outside via the interface circuit. It is possible to switch to the output mode.

Further, in the present embodiment, the operation mode may be set in the order of the synchronization mode, the output mode, and the sleep mode after the circuit device is set to the sleep mode in which the circuit device is in the sleep state based on the mode setting instruction.

In this way, when shifting from sleep mode to output mode, the sleep mode is first switched to synchronous mode for synchronous operation, and then the synchronous mode is switched to output mode for wireless transmission. become.

Further, the present embodiment relates to the circuit device described above and a wireless transmitter including a wireless transmitter that performs wireless transmission based on a clock signal.

Further, the present embodiment includes the above-mentioned circuit device and an oscillator, and the digitally controlled oscillator circuit relates to an oscillator that generates a clock signal using the oscillator.

The present embodiment also relates to an electronic device including the circuit device described above and a processing device that controls the circuit device.

Although the present embodiment has been described in detail as described above, those skilled in the art will easily understand that many modifications that do not substantially deviate from the novel matters and effects of the present disclosure are possible. Therefore, all such variations are included in the scope of the present disclosure. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by that different term anywhere in the specification or drawing. All combinations of the present embodiment and modifications are also included in the scope of the present disclosure. Further, the configuration / operation of the circuit device, the processing circuit, the synchronization circuit, the digital control oscillation circuit, the wireless transmitter, the oscillator, the electronic device, and the like are not limited to those described in the present embodiment, and various modifications can be performed.

4 ... oscillator, 10 ... circuit device, 15 ... package, 16 ... base, 17 ... lid,
18, 19 ... External terminal, 20 ... Processing circuit, 30 ... Adder, 32 ... Modulation data output unit,
40 ... Digital loop filter, 42 ... Holding circuit, 50 ... Synchronous circuit,
52 ... frequency dividing circuit, 54 ... output circuit, 60 ... comparison circuit, 62 ... time digital conversion circuit,
64 ... Frequency counter, 65 ... 1st counter, 66 ... 2nd counter,
67 ... time digital conversion circuit, 68 ... arithmetic circuit, 70 ... start signal generation circuit,
72 ... Stop signal generation circuit, 80 ... Digital control oscillation circuit, 82 ... Frequency adjustment circuit,
84 ... D / A conversion circuit, 86 ... drive circuit, 90 ... timekeeping circuit,
92 ... interface circuit, 100 ... wireless transmitter, 102 ... transmitter circuit,
230 ... measurement circuit, 240 ... signal generation circuit, 241 ... integration period signal generation circuit,
242 ... Polarity switching signal generation circuit, 243 ... Integration period signal generation circuit,
244 ... Polarity switching signal generation circuit, 260 ... Integral processing circuit,
261, 262, 263, 264 ... Integrator circuit, 271 ... Ring oscillator,
272 ... Adjustment circuit, 281 ... Ring oscillator, 282 ... Adjustment circuit,
291 ... Measurement circuit, 292 ... Reference clock counter,
500 ... Electronic equipment, 510 ... Communication interface, 520 ... Processing device,
530 ... Operation interface, 540 ... Display, 550 ... Memory,
ANT ... antenna, CLK ... clock signal, CQ ... comparison result data,
CV ... Variable Capacitor, DFC, DFC1, DFC2 ... Frequency Control Data,
DM ... Modulation data, FBCLK ... Feedback clock signal,
RCLK ... reference clock signal, STA ... start signal, STP ... stop signal,
SW1, SW2 ... Switch, TE, TCQ, TX1, TX2 ... Terminal, XTAL ... Oscillator,

Claims (16)

A processing circuit that generates frequency control data and
A synchronization circuit having a digitally controlled oscillation circuit that generates a clock signal of an oscillation frequency corresponding to the frequency control data, and
Including
In sync mode
The synchronization circuit synchronizes the clock signal generated by the digital control oscillation circuit with a reference clock signal input from the outside.
In output mode
The processing circuit performs modulation processing on the frequency control data and performs modulation processing.
The synchronous circuit is a circuit characterized in that the clock signal generated by the digital control oscillation circuit based on the frequency control data subjected to the modulation process is output as the clock signal for modulated wireless transmission. apparatus. In the circuit device according to claim 1,
The processing circuit
In the synchronization mode, the frequency control data when the clock signal is synchronized with the reference clock signal is retained.
A circuit device characterized in that the modulation processing is performed on the held frequency control data in the output mode. In the circuit device according to claim 1 or 2.
The synchronization circuit
A circuit device including a comparison circuit that compares the reference clock signal with a feedback clock signal based on the clock signal and outputs the comparison result data obtained by the comparison to the processing circuit. In the circuit device according to claim 3,
The processing circuit
A circuit device including a digital loop filter that generates the frequency control data by performing a digital loop filter process on the comparison result data. In the circuit device according to claim 3 or 4.
The comparison circuit
A circuit device characterized in that a phase comparison is performed by comparing the phase of the reference clock signal and the phase of the feedback clock signal, and the comparison result data obtained by the phase comparison is output to the processing circuit. In the circuit device according to claim 5,
The comparison circuit
A circuit device including a time digital conversion circuit that converts a phase difference between the reference clock signal and the feedback clock signal into a digital value and outputs the digital value as the comparison result data to the processing circuit. In the circuit device according to claim 3 or 4.
The comparison circuit
A circuit device characterized in that frequency comparison is performed by comparing the frequency of the reference clock signal and the frequency of the feedback clock signal, and the comparison result data obtained by the frequency comparison is output to the processing circuit. In the circuit device according to claim 7.
The comparison circuit
A circuit device having a frequency counter that performs count processing based on the reference clock signal and the feedback clock signal and outputs count data, and outputs the comparison result data based on the count data to the processing circuit. .. In the circuit device according to any one of claims 3 to 8.
The comparison circuit
A circuit device characterized in that it is set to a disabled or power saving state in the output mode. In the circuit device according to any one of claims 3 to 9.
The synchronization circuit
A first switch provided between the digitally controlled oscillator circuit and the comparison circuit is included.
A circuit device characterized in that the first switch is turned on in the synchronous mode and turned off in the output mode. In the circuit device according to any one of claims 1 to 10.
The processing circuit
A circuit characterized by determining whether or not the clock signal is synchronized with the reference clock signal in the synchronization mode, and after determining that the clock signal is synchronized, the operation mode of the circuit device is switched from the synchronization mode to the output mode. apparatus. In the circuit device according to any one of claims 1 to 11.
Includes a timekeeping circuit that outputs a mode setting instruction that sets the operation mode of the circuit device, or an interface circuit that receives the mode setting instruction from the outside.
The processing circuit
A circuit device characterized in that the operation mode of the circuit device is set to the synchronous mode and then to the output mode based on the mode setting instruction. In the circuit device according to claim 12,
The circuit device is characterized in that the operation mode is set in the order of the synchronization mode, the output mode, and the sleep mode after the circuit device is set to the sleep mode in which the circuit device is in the sleep state based on the mode setting instruction. .. The circuit device according to any one of claims 1 to 13.
A wireless transmitter that performs wireless transmission based on the clock signal,
A wireless transmitter characterized by including. The circuit device according to any one of claims 1 to 13.
Oscillator and
Including
The digitally controlled oscillator circuit is an oscillator characterized in that the clock signal is generated by using the oscillator. The circuit device according to any one of claims 1 to 13.
A processing device that controls the circuit device and
An electronic device characterized by including.

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