JP2021009958A - Solar cell, laminate, multi-junction solar cell, solar cell module and photovoltaic power generation system - Google Patents
Solar cell, laminate, multi-junction solar cell, solar cell module and photovoltaic power generation system Download PDFInfo
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- 238000010248 power generation Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 156
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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- 229920002492 poly(sulfone) Polymers 0.000 description 1
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- NIFIFKQPDTWWGU-UHFFFAOYSA-N pyrite Chemical compound [Fe+2].[S-][S-] NIFIFKQPDTWWGU-UHFFFAOYSA-N 0.000 description 1
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/03529—Shape of the potential jump barrier or surface barrier
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0725—Multiple junction or tandem solar cells
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- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/032—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
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- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/0328—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032
- H01L31/0336—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032 in different semiconductor regions, e.g. Cu2X/CdX hetero- junctions, X being an element of Group VI of the Periodic Table
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
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- H01L31/078—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers including different types of potential barriers provided for in two or more of groups H01L31/062 - H01L31/075
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Abstract
Description
実施形態は太陽電池、積層体、多接合型太陽電池、太陽電池モジュール及び太陽光発電システムに関する。 Embodiments relate to solar cells, laminates, multijunction solar cells, solar cell modules and photovoltaic systems.
高効率な太陽電池として多接合型（タンデム）太陽電池がある。タンデム太陽電池は、波長帯毎に分光感度が高いセルを用いることができるため、単接合よりも高効率化できる。またタンデム太陽電池のトップセルとして、安価な材料でかつバンドギャップが広い亜酸化銅化合物などが期待されている。 There is a multi-junction (tandem) solar cell as a highly efficient solar cell. Since a tandem solar cell can use a cell having high spectral sensitivity for each wavelength band, it can be made more efficient than a single junction. Further, as a top cell of a tandem solar cell, a cuprous oxide compound which is an inexpensive material and has a wide bandgap is expected.
実施形態は、変換効率を向上させた太陽電池、積層体、多接合型太陽電池、太陽電池モジュール及び太陽光発電システムを提供する。 The embodiment provides a solar cell, a laminate, a multi-junction solar cell, a solar cell module, and a photovoltaic power generation system with improved conversion efficiency.
実施形態の太陽電池は、透明な第１電極と、第１電極上に第１半導体層と、第１半導体層上に第２半導体層と、第２半導体層上に透明な第２電極とを有し、第１半導体層の第２半導体層側を向く面には、規則的な溝が形成されている。 The solar cell of the embodiment has a transparent first electrode, a first semiconductor layer on the first electrode, a second semiconductor layer on the first semiconductor layer, and a transparent second electrode on the second semiconductor layer. A regular groove is formed on the surface of the first semiconductor layer facing the second semiconductor layer.
（第１実施形態）
第１実施形態は、太陽電池に関する。図１に、第１実施形態の太陽電池１００の概念図を示す。図１に示すように、本実施形態に係る太陽電池１００は、第１電極１と、第１電極１上に第１半導体層２と、第１半導体層２上に第２半導体層３と、第２半導体層３上に第２電極４と、を備える。第１電極１と第１半導体層２との間や第２半導体層３と第２電極４との間には、図示しない中間層が含まれていてもよい。光は第１電極１側から入射しても第２電極４側から入射してもよい。光が太陽電池１００に入射して発電することができる。
(First Embodiment)
The first embodiment relates to a solar cell. FIG. 1 shows a conceptual diagram of the solar cell 100 of the first embodiment. As shown in FIG. 1, the solar cell 100 according to the present embodiment includes a first electrode 1, a first semiconductor layer 2 on the first electrode 1, and a second semiconductor layer 3 on the first semiconductor layer 2. A second electrode 4 is provided on the second semiconductor layer 3. An intermediate layer (not shown) may be included between the first electrode 1 and the first semiconductor layer 2 or between the second semiconductor layer 3 and the second electrode 4. The light may be incident from the first electrode 1 side or the second electrode 4 side. Light can enter the solar cell 100 to generate electricity.
（第１電極）
実施形態の第１電極１は、第１半導体層２側に設けられた透明な導電層である。図１では、第１電極１は、第１半導体層２と直接接している。第１電極１としては、透明導電膜、金属膜と透明導電膜と金属膜を積層したものが好ましい。透明導電膜としては、酸化インジウムスズ（Indium Tin Oxide；ＩＴＯ）、アルミニウムドープ酸化亜鉛（Al-doped Zinc Oxide；ＡＺＯ）、ボロンドープ酸化亜鉛（Boron-doped Zinc Oxide；ＢＺＯ）、ガリウムドープ酸化亜鉛（Gallium-doped Zinc Oxide；ＧＺＯ）、フッ素ドープ酸化スズ（Fluorine-doped Tin Oxide；ＦＴＯ）、アンチモンドープ酸化スズ（Antimony-doped Tin Oxide；ＡＴＯ）、チタンドープ酸化インジウム（Titanium-doped Indium Oxide；ＩＴｉＯ）、酸化インジウム酸化亜鉛（Indium Zinc Oxide；ＩＺＯ）や酸化インジウムガリウム亜鉛（Indium Gallium Zinc Oxide；ＩＧＺＯ）、タンタルドープ酸化スズ（Ta-doped Tin Oxide；ＳｎＯ２：Ｔａ）、ニオブドープ酸化スズ（Nb-doped Tin Oxide；ＳｎＯ２：Ｎｂ）、タングステンドープ酸化スズ（W-doped Tin Oxide；ＳｎＯ２：Ｗ）、モリブデンドープ酸化スズ（Mo-doped Tin Oxide；ＳｎＯ２：Ｍｏ）、フッ素ドープ酸化スズ（F-doped Tin Oxide；ＳｎＯ２：Ｆ）、水素ドープ酸化インジウム（Hydrogen-doped Indium Oxide；ＩＯＨ）など特に限定されない。透明導電膜は、複数の膜を持つ積層膜であってもよく、上記酸化物の他に酸化スズなどの膜が積層膜に含まれていてもよい。酸化スズなどの膜へのドーパントとしては、Ｉｎ、Ｓｉ、Ｇｅ、Ｔｉ、Ｃｕ、Ｓｂ、Ｎｂ、Ｆ、Ｔａ、Ｗ、Ｍｏ、Ｆ、Ｃｌなど特に限定されない。金属膜としては、Ｍｏ、Ａｕ、Ｃｕ、Ａｇ、Ａｌ、ＴａやＷの膜など特に限定されない。また、第１電極１は、透明導電膜上にドット状、ライン状もしくはメッシュ状の金属を設けた電極でもよい。このとき、ドット状、ライン状もしくはメッシュ状の金属は、透明導電膜と第１半導体層２の間や透明導電膜の第１半導体層２とは反対側に配置される。ドット状、ライン状もしくはメッシュ状の金属は、透明導電膜に対して開口率が５０％以上であることが好ましい。ドット状、ライン状もしくはメッシュ状の金属は、Ｍｏ、Ａｕ、Ｃｕ、Ａｇ、Ａｌ、ＴａやＷなど特に限定されない。第１電極１に金属膜を用いる場合、透過性の観点から５ｎｍ以下程度の膜厚とすることが好ましい。ライン状やメッシュ状の金属膜を用いる場合、透過性は開口部で確保されるため、金属膜の膜厚に関してはこの限りではない。
(1st electrode)
The first electrode 1 of the embodiment is a transparent conductive layer provided on the side of the first semiconductor layer 2. In FIG. 1, the first electrode 1 is in direct contact with the first semiconductor layer 2. As the first electrode 1, a transparent conductive film, a metal film, a transparent conductive film, and a metal film laminated is preferable. Examples of the transparent conductive film include Indium Tin Oxide (ITO), Al-doped Zinc Oxide (AZO), Boron-doped Zinc Oxide (BZO), and Gallium-doped Zinc Oxide (Gallium). -doped Zinc Oxide (GZO), Fluorine-doped Tin Oxide (FTO), Antimony-doped Tin Oxide (ATO), Titanium-doped Indium Oxide (ITIO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Tantal-doped Tin Oxide (SnO 2 : Ta), Niob-doped Tin (Nb-doped Tin) Oxide; SnO 2 : Nb), Tungsten-doped Tin Oxide (SnO 2 : W), Mo-doped Tin Oxide (SnO 2 : Mo), Fluorodoped Tin Oxide (F-doped) Tin Oxide; SnO 2 : F), Hydrogen-doped Indium Oxide (IOH), and the like are not particularly limited. The transparent conductive film may be a laminated film having a plurality of films, and a film such as tin oxide may be contained in the laminated film in addition to the above oxide. The dopant on the film such as tin oxide is not particularly limited to In, Si, Ge, Ti, Cu, Sb, Nb, F, Ta, W, Mo, F, Cl and the like. The metal film is not particularly limited, such as a film of Mo, Au, Cu, Ag, Al, Ta or W. Further, the first electrode 1 may be an electrode in which a dot-shaped, line-shaped or mesh-shaped metal is provided on a transparent conductive film. At this time, the dot-shaped, line-shaped or mesh-shaped metal is arranged between the transparent conductive film and the first semiconductor layer 2 or on the side opposite to the first semiconductor layer 2 of the transparent conductive film. The dot-shaped, line-shaped or mesh-shaped metal preferably has an aperture ratio of 50% or more with respect to the transparent conductive film. The dot-shaped, line-shaped or mesh-shaped metal is not particularly limited to Mo, Au, Cu, Ag, Al, Ta and W. When a metal film is used for the first electrode 1, the film thickness is preferably about 5 nm or less from the viewpoint of permeability. When a line-shaped or mesh-shaped metal film is used, the film thickness of the metal film is not limited to this because the permeability is ensured at the opening.
（第１半導体層）
実施形態の第１半導体層２は、第１電極１と第２半導体層３の間に配置された半導体層である。第１半導体層２としては、化合物半導体層が好ましい。第１半導体層２は、ｐ型の光電変換層とも言う。第１半導体層２としては、亜酸化銅（Ｃｕ２Ｏ）、カルコパイライト型半導体、ケステライト型半導体、スタナイト型半導体及びペロブスカイト半導体からなる群より選ばれる１種を主体（９０ｗｔ％以上）とする半導体層が挙げられる。第１半導体層２は、より具体的には、ｐ型の光電変換層である。第１半導体層２が厚くなると透過率が低下し、また、スパッタでの成膜を考慮すると１０μｍ以下が実用的であり、化合物半導体層としては、亜酸化銅（Ｃｕ２Ｏ）を主体とする半導体層が好ましい。第１半導体層２の厚さは、５００ｎｍ以上１０μｍ以下であることが好ましい。化合物半導体層としては、亜酸化銅等を主体とする半導体層には、添加物を含んでもよい。第１半導体層２の第２半導体層３側には、一部ｎ型の領域が含まれてもよい。
(First semiconductor layer)
The first semiconductor layer 2 of the embodiment is a semiconductor layer arranged between the first electrode 1 and the second semiconductor layer 3. As the first semiconductor layer 2, a compound semiconductor layer is preferable. The first semiconductor layer 2 is also referred to as a p-type photoelectric conversion layer. The first semiconductor layer 2 is a semiconductor mainly composed of one type (90 wt% or more) selected from the group consisting of cuprous oxide (Cu 2 O), calcium pyrite type semiconductor, kesterite type semiconductor, stanite type semiconductor and perovskite semiconductor. Layers are mentioned. More specifically, the first semiconductor layer 2 is a p-type photoelectric conversion layer. When the first semiconductor layer 2 becomes thicker, the transmittance decreases, and considering film formation by sputtering, it is practical to have a thickness of 10 μm or less, and the compound semiconductor layer is mainly composed of cuprous oxide (Cu 2 O). A semiconductor layer is preferred. The thickness of the first semiconductor layer 2 is preferably 500 nm or more and 10 μm or less. As the compound semiconductor layer, an additive may be contained in the semiconductor layer mainly composed of cuprous oxide or the like. The second semiconductor layer 3 side of the first semiconductor layer 2 may partially include an n-type region.
化合物半導体層は、透過率を考慮すると大粒径の多結晶体であることが好ましい。粒径（外接円直径）は、第１半導体層２の厚さの９０％以上であることが好ましい。さらに好ましくは第１半導体層２の厚さの９５％以上である。粒径がこのような範囲であることで、粒界での光の反射を抑制することができ、効率的に光を透過することができるからである。また、同じく透過率の観点から第１半導体層２の第２半導体層３側を向く表面において、結晶粒の面積（粒界を境界とする面積で、溝５及び凹凸を考慮しない）が１．０μｍ２以上を満たす結晶の比率（数）が全体の８０％以上であることが好ましい。これらの条件を満たす場合、第１半導体層２は、大部分が大粒径の結晶で構成されているため、透過率に優れる。 The compound semiconductor layer is preferably a polycrystalline material having a large particle size in consideration of transmittance. The particle size (circumscribed circle diameter) is preferably 90% or more of the thickness of the first semiconductor layer 2. More preferably, it is 95% or more of the thickness of the first semiconductor layer 2. This is because when the particle size is in such a range, the reflection of light at the grain boundary can be suppressed and the light can be efficiently transmitted. Similarly, from the viewpoint of transmittance, on the surface of the first semiconductor layer 2 facing the second semiconductor layer 3, the area of crystal grains (the area with the grain boundary as the boundary, without considering the grooves 5 and unevenness) is 1. The ratio (number) of crystals satisfying 0 μm 2 or more is preferably 80% or more of the total. When these conditions are satisfied, the first semiconductor layer 2 is excellent in transmittance because most of the first semiconductor layer 2 is composed of crystals having a large particle size.
第１半導体層２の第２半導体層３側の第２電極４を向く表面には、規則的な溝５が形成されている。図２に第１半導体層２の表面の模式図を示す。図２に示すように、規則的な溝５は、第１半導体層２の結晶粒の粒界方向（いずれかの粒界の方向）に延びている。第１半導体層２の第２半導体層３側の表面には、粒界６の小さな凹みと結晶粒の表面の小さな溝５が存在する。溝５のピッチ（溝の下端間の距離）は、１ｎｍ以上５０ｎｍ以下であることが好ましく、１ｎｍ以上１０ｎｍ以下がより好ましい。溝の下端とは、一つの溝の最も第１電極１側の部分のことである。下端間とはある溝と他の溝の最も第１電極１側の部分どうしを繋げた線の距離のことである。また、溝５の深さ（溝の下端を挟む上端間を結ぶ線分から下端までの最短距離）は、１ｎｍ以上１０ｎｍ以下である。上端とはある溝の下端と、ある溝の隣の溝の下端の間に存在し、下端間を結ぶ線分から第２半導体層３側に垂線を下した際に、その垂線が第１半導体層２と第２半導体層３との界面と交差する点と線分までの距離が最長距離となる部分のことである。溝５の深さの平均値は、溝５のピッチの平均値の半値以下であることが好ましい。ピッチも深さも非常に小さな値の溝５が複数規則的に第１半導体層２の表面に形成されていることで、変換効率と透過率が向上する。変換効率が向上することで、太陽電池単体の変換効率が向上するが、透過率が低下すると透過型の太陽電池としては好ましくない。透過率が高いことで、太陽電池１００の設置用途が増え、また、多接合型太陽電池のトップセル側に用いた際に、ボトムセル側での発電量を増やし、全体の発電量を増やすことができる。 Regular grooves 5 are formed on the surface of the first semiconductor layer 2 facing the second electrode 4 on the second semiconductor layer 3 side. FIG. 2 shows a schematic view of the surface of the first semiconductor layer 2. As shown in FIG. 2, the regular groove 5 extends in the grain boundary direction (direction of any grain boundary) of the crystal grains of the first semiconductor layer 2. On the surface of the first semiconductor layer 2 on the side of the second semiconductor layer 3, there are small dents at grain boundaries 6 and small grooves 5 on the surface of crystal grains. The pitch of the grooves 5 (distance between the lower ends of the grooves) is preferably 1 nm or more and 50 nm or less, and more preferably 1 nm or more and 10 nm or less. The lower end of the groove is the portion of one groove on the 1st electrode 1 side. The distance between the lower ends is the distance of a line connecting a groove and the portion of the other groove on the first electrode 1 side. Further, the depth of the groove 5 (the shortest distance from the line connecting the upper ends sandwiching the lower end of the groove to the lower end) is 1 nm or more and 10 nm or less. The upper end exists between the lower end of a certain groove and the lower end of the groove next to a certain groove, and when a perpendicular line is drawn from the line segment connecting the lower ends to the second semiconductor layer 3 side, the perpendicular line is the first semiconductor layer. This is the portion where the distance between the point where the interface between 2 and the second semiconductor layer 3 intersects with the line segment and the line segment is the longest distance. The average value of the depths of the grooves 5 is preferably not more than half the average value of the pitches of the grooves 5. Since a plurality of grooves 5 having a very small pitch and depth are regularly formed on the surface of the first semiconductor layer 2, the conversion efficiency and the transmittance are improved. By improving the conversion efficiency, the conversion efficiency of the solar cell alone is improved, but when the transmittance is lowered, it is not preferable as a transmissive solar cell. Due to the high transmittance, the installation application of the solar cell 100 increases, and when it is used on the top cell side of the multi-junction solar cell, the amount of power generation on the bottom cell side can be increased to increase the total amount of power generation. it can.
発明者らの研究によって、第１半導体層２の表面の溝５が規則的であるとき、より好ましくは、溝５が微細で粒界方向に延びる場合に透過率と変換効率が向上することを見いだした。 According to the research by the inventors, when the grooves 5 on the surface of the first semiconductor layer 2 are regular, more preferably, the transmittance and the conversion efficiency are improved when the grooves 5 are fine and extend in the grain boundary direction. I found it.
ピッチが１ｎｍ以上５０ｎｍ以下で深さが１ｎｍ以上１０ｎｍ以下の溝が第１半導体層２の表面のごく一部にあったり、溝５がランダムに配置したりしている場合は、好ましくない。光電変換層の表面は、平坦であるほど透過率が高まるという考えは知られていた。しかし、表面のナノスケールの溝が無い場合やナノスケールの溝がランダムな場合などは、実施形態の規則的な溝５が形成された第１半導体層２を有する太陽電池と比べて、透過率だけでなく、変換効率も低下することが本発明により明らかになった。例えば、高さが数百ｎｍ程度（結晶粒の上端から隣接する結晶粒との粒界までの高さ）の凹凸が第１半導体層２の表面にあると、第１半導体層２の表面で入射した光が散乱するため、透過率が低下してしまう。第１半導体層２の表面の凹凸の高さが第１半導体層２の厚さの１０％以下であって、ナノスケールの溝５が規則的な溝が形成された表面を有することが高い透過率と高い変換効率の太陽電池を得る観点から好ましい。ドット状の凹みは、粒界方向に延びていないことから実施形態の溝５には含まれない。 It is not preferable when the grooves having a pitch of 1 nm or more and 50 nm or less and a depth of 1 nm or more and 10 nm or less are present in a small part of the surface of the first semiconductor layer 2 or the grooves 5 are randomly arranged. It has been known that the flatter the surface of the photoelectric conversion layer, the higher the transmittance. However, when there are no nanoscale grooves on the surface or when the nanoscale grooves are random, the transmittance is higher than that of the solar cell having the first semiconductor layer 2 in which the regular grooves 5 of the embodiment are formed. Not only that, it has been clarified by the present invention that the conversion efficiency is also reduced. For example, if the surface of the first semiconductor layer 2 has irregularities having a height of about several hundred nm (the height from the upper end of the crystal grains to the grain boundaries with the adjacent crystal grains), the surface of the first semiconductor layer 2 Since the incident light is scattered, the transmittance is lowered. It is highly transparent that the height of the unevenness on the surface of the first semiconductor layer 2 is 10% or less of the thickness of the first semiconductor layer 2 and the nanoscale grooves 5 have a surface on which regular grooves are formed. It is preferable from the viewpoint of obtaining a solar cell having a high rate and high conversion efficiency. The dot-shaped dents are not included in the groove 5 of the embodiment because they do not extend in the grain boundary direction.
溝５のピッチと溝５の深さの求め方について詳細に説明する。図３に透過型電子顕微鏡（Transmission Electron Microscope；ＴＥＭ）を用いて２００万倍で第１半導体層２と第２半導体層３の境界部分を観察した画像を示す。図３の画像は、得られた画像（グレースケール）をレベル補正（シャドウ入力レベル６０、ハイライト入力レベル７０、中間調入力レベル１．００）した画像である。図３の破線は、第１半導体層２と第２半導体層３の界面の位置を示している。観察位置は、結晶粒の中央であることが好ましい。ＴＥＭには、日立ハイテクノロジーズのＨ−９５００を用い、加速電圧は２００ｋＶで倍率精度は±１０％以下である。 How to obtain the pitch of the groove 5 and the depth of the groove 5 will be described in detail. FIG. 3 shows an image obtained by observing the boundary portion between the first semiconductor layer 2 and the second semiconductor layer 3 at a magnification of 2 million using a transmission electron microscope (TEM). The image of FIG. 3 is an image obtained by level-correcting the obtained image (grayscale) (shadow input level 60, highlight input level 70, halftone input level 1.00). The broken line in FIG. 3 indicates the position of the interface between the first semiconductor layer 2 and the second semiconductor layer 3. The observation position is preferably the center of the crystal grains. Hitachi High-Technologies H-9500 is used as the TEM, the acceleration voltage is 200 kV, and the magnification accuracy is ± 10% or less.
規則的な溝５と規則的ではない溝、言い換えると、ランダムな溝とは、以下のように区別できる。例えば、図２で示されるような第１半導体層２までを作製した部材（第１半導体層２の第１電極１側とは反対側の面が露出している部材）の第１半導体層２の表面をＴＥＭで１μｍ×１μｍの範囲を１０万倍で観察し、筋状の溝５を確認する。そして、１つの溝（第１の溝）に対する当該溝を挟む溝（第２の溝と第３の溝）の角度（測定部位の第１の溝の接線に対する測定部位の第２の溝の接線の角度、測定部位の第１の溝の接線に対する測定部位の第３の溝の接線の角度）がそれぞれ±１０度以内である部分を有することを満たす溝の数が観察領域、つまり粒界に囲まれた部分に確認できる溝の数の９０％以上であるとき、第１半導体層２の表面に形成された溝５が規則的とする。なお、溝５の角度は、溝５が粒界に向かって延びる方向であり、角度を求める際に、端部の溝は除外する。また、ランダムな溝の場合は、溝のピッチのばらつきが１０ｎｍ以内にならないため、ＴＥＭによる断面観察から、溝５が規則的であるかランダムであるかを区別することができる。また、規則的な溝５は、第１半導体層２全体の表面面積の８０％以上に形成されていることが、透過率と変換効率の観点から好ましい。なお、溝５が存在する面積は、上記条件を満たす溝５で挟まれた領域の面積である。図２の模式図のような溝であれば、ほぼ１００％以下の領域が溝の面積に相当する。なお、面積は、溝５の凹み部分を含まない面積であり、結晶粒の面積と同様の概念に基づく面積である。第１半導体層２の表面を溝５の長さは、１００ｎｍ以上が好ましく、５００ｎｍ以上がより好ましい。なお、実施形態の溝５は実質的に交差しない。第１半導体層２の表面には交差する溝５がわずかに含まれる場合もあるが、交差する溝５の数は、多くても全体の１０％以下である。 Regular grooves 5 and non-regular grooves, in other words, random grooves, can be distinguished as follows. For example, the first semiconductor layer 2 of a member (a member whose surface opposite to the first electrode 1 side of the first semiconductor layer 2 is exposed) produced up to the first semiconductor layer 2 as shown in FIG. The surface of the surface is observed with a TEM in a range of 1 μm × 1 μm at a magnification of 100,000, and the streaky groove 5 is confirmed. Then, the angle of the groove (second groove and third groove) sandwiching the groove with respect to one groove (first groove) (tangent of the second groove of the measurement site with respect to the tangent of the first groove of the measurement site). The number of grooves satisfying that each of the angle and the angle of the tangent of the third groove of the measurement site to the tangent of the first groove of the measurement site is within ± 10 degrees is in the observation region, that is, the grain boundary. When the number of grooves that can be confirmed in the enclosed portion is 90% or more, the grooves 5 formed on the surface of the first semiconductor layer 2 are regular. The angle of the groove 5 is the direction in which the groove 5 extends toward the grain boundary, and the groove at the end is excluded when determining the angle. Further, in the case of a random groove, since the variation in the pitch of the groove is not within 10 nm, it is possible to distinguish whether the groove 5 is regular or random from the cross-sectional observation by TEM. Further, it is preferable that the regular grooves 5 are formed in 80% or more of the surface area of the entire first semiconductor layer 2 from the viewpoint of transmittance and conversion efficiency. The area where the groove 5 exists is the area of the region sandwiched by the grooves 5 satisfying the above conditions. In the case of a groove as shown in the schematic view of FIG. 2, a region of about 100% or less corresponds to the area of the groove. The area is an area that does not include the recessed portion of the groove 5, and is an area based on the same concept as the area of crystal grains. The length of the groove 5 on the surface of the first semiconductor layer 2 is preferably 100 nm or more, more preferably 500 nm or more. The grooves 5 of the embodiment do not substantially intersect. The surface of the first semiconductor layer 2 may include a small number of intersecting grooves 5, but the number of intersecting grooves 5 is at most 10% or less of the total.
実施形態の太陽電池１００は、７００ｎｍ以上１０００ｎｍ以下の波長帯の光の透過率が高いことが好ましい。この波長帯の光の透過率が高いと、実施形態の太陽電池１００を多接合型太陽電池のトップセル側に用いた際に、ボトムセル側にＳｉの太陽電池を用いた際に、ボトムセル側での発電量が高くなる。太陽電池１００の７００ｎｍ以上１０００ｎｍ以下の波長帯の光の透過率は、７０％以上が好ましく、８０％以上であることがより好ましい。 The solar cell 100 of the embodiment preferably has high light transmittance in the wavelength band of 700 nm or more and 1000 nm or less. When the light transmittance in this wavelength band is high, when the solar cell 100 of the embodiment is used on the top cell side of the multi-junction solar cell, and when a Si solar cell is used on the bottom cell side, the bottom cell side The amount of power generation will be high. The transmittance of light in the wavelength band of 700 nm or more and 1000 nm or less of the solar cell 100 is preferably 70% or more, and more preferably 80% or more.
ここで、本実施形態にかかる太陽電池の備える第１半導体層２の作製方法について説明する。以下は、一例として亜酸化銅を主体とする半導体層を作製する方法について説明する。 Here, a method for manufacturing the first semiconductor layer 2 included in the solar cell according to the present embodiment will be described. The method for producing a semiconductor layer mainly composed of cuprous oxide will be described below as an example.
第１半導体層２はスパッタリングによって作製する。スパッタ中の雰囲気は、Ａｒなどの不活性ガスと酸素ガスとの混合ガス雰囲気とすることが好ましい。太陽電池１００を保持する基板の種類にもよるが、基板温度を１００℃以上６００℃以下に加熱して、Ｃｕを含むターゲットを用いてスパッタする。例えば、スパッタリングの温度や酸素分圧を調整することによって大粒径で微細な溝５を有する半導体層を得ることができる。１００℃以上の高温状態の成膜した部材を大気中で急冷するなどすると、第１半導体層２の表面の溝５が無くなり平坦化してしまうので、真空中で急冷することが好ましい。また、第１半導体層２の成膜後に真空であってもアニールすることによっても溝５は平坦化し易い。太陽電池１００を作製するために用いる基板としては、アクリル、ポリイミド、ポリカーボネート、ポリエチレンテレフタレート（ＰＥＴ）、ポリプロピレン（ＰＰ）、フッ素系樹脂（ポリテトラフルオロエチレン（ＰＴＦＥ）、パーフルオロエチレンプロペンコポリマー（ＦＥＰ）、エチレンテトラフルオロエチレンコポリマー（ＥＴＦＥ）、ポリクロロトリフルオロエチレン（ＰＣＴＦＥ）、パーフルオロアルコキシアルカン（ＰＦＡ）など）、ポリアリレート、ポリサルフォン、ポリエーテルサルフォンやポリエーテルイミドなどの有機系の基板やソーダライムガラス、白板ガラス、化学強化ガラスや石英などの無機系の基板を用いることができる。 The first semiconductor layer 2 is manufactured by sputtering. The atmosphere during sputtering is preferably a mixed gas atmosphere of an inert gas such as Ar and oxygen gas. Although it depends on the type of the substrate that holds the solar cell 100, the substrate temperature is heated to 100 ° C. or higher and 600 ° C. or lower, and sputtering is performed using a target containing Cu. For example, a semiconductor layer having a large particle size and fine grooves 5 can be obtained by adjusting the sputtering temperature and oxygen partial pressure. When a member formed with a film formed at a high temperature of 100 ° C. or higher is rapidly cooled in the atmosphere, the groove 5 on the surface of the first semiconductor layer 2 disappears and becomes flat, so that it is preferable to rapidly cool in a vacuum. Further, the groove 5 can be easily flattened by annealing even in a vacuum after the film formation of the first semiconductor layer 2. As the substrate used for manufacturing the solar cell 100, acrylic, polyimide, polycarbonate, polyethylene terephthalate (PET), polypropylene (PP), fluororesin (polytetrafluoroethylene (PTFE), perfluoroethylene propene copolymer (FEP)) , Ethylene tetrafluoroethylene copolymer (ETFE), polychlorotrifluoroethylene (PCTFE), perfluoroalkoxyalkane (PFA), etc.), polyallylate, polysulfone, organic substrates and sodas such as polyether sulfone and polyetherimide. Inorganic substrates such as lime glass, white plate glass, chemically strengthened glass, and quartz can be used.
第１半導体層２の９５％以上は亜酸化銅で構成されていることが好ましい。第１半導体層２の９８％以上が亜酸化銅で構成されていることがより好ましい。つまり、第１半導体層２は、ＣｕＯやＣｕ等の異相をほとんど（実質的に）含まないことが好ましい。第１半導体層２には、ＣｕＯやＣｕなどの異相が含まれず、実質的にＣｕ２Ｏ単相の薄膜であると、非常に高い透光性となるため好ましい。第１半導体層２が実質的にＣｕ２Ｏの単相であることは、フォトルミネッセンス法（Photo Luminescence；ＰＬ法）又はＸ線回折法（X-ray Diffraction；ＸＲＤ）により測定することで確認できる。 It is preferable that 95% or more of the first semiconductor layer 2 is composed of cuprous oxide. It is more preferable that 98% or more of the first semiconductor layer 2 is composed of cuprous oxide. That is, it is preferable that the first semiconductor layer 2 contains almost (substantially) no different phases such as CuO and Cu. The first semiconductor layer 2, does not contain heterogeneous phases such as CuO and Cu, the substantially is a thin film of Cu 2 O single phase is preferable because a very high light-transmitting property. It can be confirmed by measuring by the photoluminescence method (PL method) or the X-ray diffraction method (X-ray Diffraction; XRD) that the first semiconductor layer 2 is substantially a single phase of Cu 2 O. ..
（第２半導体層）
第２半導体層３は、第１半導体層２と第２電極４の間に配置された半導体層である。第２半導体層３の第１半導体層２を向く面は、第１半導体層２の第２半導体層３を向く面と直接的に接していることが好ましい。第２半導体層３は、ｎ型層又はバッファー層とも言う。第２半導体層３としては、酸化物又は硫化物のｎ型の半導体層であることが好ましい。第２半導体層３はアモルファスの薄膜であることが好ましい。第２半導体層３に用いられる酸化物としては、特に限定されるものではないが、ＺｎｘＡｙＸｚＯｗ（ＡはＳｉ、Ｇｅ及びＳｎからなる群より選ばれる１種以上の元素、Ｍは、Ｂ、Ａｌ、Ｇａ、Ｉｎ及びＧｅからなる群から選ばれる１種以上の元素、０．９０≦ｘ＋ｙ≦１．００、０．００≦ｚ≦０．３０、０．９０≦ｗ≦１．１０）、Ｃｕ（２−ｘ）ＭｘＯ（Ｍ＝Ｍｎ、Ｍｇ、Ｃａ、Ｚｎ、Ｓｒ、Ｂａ、Ａｌ、Ｇａ、Ｉｎ、Ｎｂ、ランタノイド）、Ｃｕ２Ｏ：Ｆ、Ｃｕ２Ｏ：Ｎ、Ｃｕ２Ｏ：Ｂ、Ｃｕ２Ｏ：Ｃｌ、Ｃｕ２Ｏ：Ｂｒ及びＣｕ２Ｏ：Ｉ、Ａｌ（２−ｘ）ＧａｘＯ３からなる群から選ばれる酸化物が好ましい。第２半導体層３に用いる硫化物としては、特に限定されるものではないが、ＺｎｘＩｎ（２−２ｘ）Ｓ（３−２ｘ）、ＺｎＳ及びＩｎｘＧａ（１−ｘ）Ｓからなる群から選ばれる１種以上の硫化物が好ましい。ｘの範囲は０≦ｘ≦１、ｙの範囲は０≦ｙ≦２である。
(Second semiconductor layer)
The second semiconductor layer 3 is a semiconductor layer arranged between the first semiconductor layer 2 and the second electrode 4. It is preferable that the surface of the second semiconductor layer 3 facing the first semiconductor layer 2 is in direct contact with the surface of the first semiconductor layer 2 facing the second semiconductor layer 3. The second semiconductor layer 3 is also referred to as an n-type layer or a buffer layer. The second semiconductor layer 3 is preferably an oxide or sulfide n-type semiconductor layer. The second semiconductor layer 3 is preferably an amorphous thin film. The oxide used in the second semiconductor layer 3 is not particularly limited, but one or more elements selected from the group consisting of Zn x A y X z Ow (A is Si, Ge and Sn). M is one or more elements selected from the group consisting of B, Al, Ga, In and Ge, 0.90 ≦ x + y ≦ 1.00, 0.00 ≦ z ≦ 0.30, 0.90 ≦ w ≦ 1.10), Cu (2-x) M x O (M = Mn, Mg, Ca, Zn, Sr, Ba, Al, Ga, In, Nb, lanthanoid), Cu 2 O: F, Cu 2 O: Oxides selected from the group consisting of N, Cu 2 O: B, Cu 2 O: Cl, Cu 2 O: Br and Cu 2 O: I, Al (2-x) Ga x O 3 are preferable. The sulfide used for the second semiconductor layer 3 is not particularly limited, but is a group consisting of Zn x In (2-2x) S (3-2x) , ZnS and In x Ga (1-x) S. One or more sulfides selected from the above are preferable. The range of x is 0 ≦ x ≦ 1, and the range of y is 0 ≦ y ≦ 2.
第２半導体層３の膜厚は、典型的には、３ｎｍ以上１００ｎｍ以下である。第２半導体層３の厚さが５ｎｍ以下であると第２半導体層３のカバレッジが悪い場合にリーク電流が発生し、特性を低下させてしまう場合がある。カバレッジが良い場合は上記膜厚に限定されない。第２半導体層３の厚さが１００ｎｍを超えると第２半導体層３の過度の高抵抗化による特性低下や、透過率低下による短絡電流低下が起こる場合がある。従って、第２半導体層３の厚さは５ｎｍ以上５０ｎｍ以下がより好ましく、５ｎｍ以上１０ｎｍ以下がさらにより好ましい。また、カバレッジの良い膜を実現するために第２半導体層３の表面粗さは５ｎｍ以下が好ましい。第２半導体層３の質が高い場合は２００ｎｍ程度の膜厚でも動作する太陽電池１００が構成できる。 The film thickness of the second semiconductor layer 3 is typically 3 nm or more and 100 nm or less. If the thickness of the second semiconductor layer 3 is 5 nm or less, a leak current may occur when the coverage of the second semiconductor layer 3 is poor, and the characteristics may be deteriorated. When the coverage is good, the film thickness is not limited to the above. If the thickness of the second semiconductor layer 3 exceeds 100 nm, the characteristics of the second semiconductor layer 3 may be lowered due to excessively high resistance, or the short-circuit current may be lowered due to the decrease in transmittance. Therefore, the thickness of the second semiconductor layer 3 is more preferably 5 nm or more and 50 nm or less, and even more preferably 5 nm or more and 10 nm or less. Further, in order to realize a film having good coverage, the surface roughness of the second semiconductor layer 3 is preferably 5 nm or less. When the quality of the second semiconductor layer 3 is high, the solar cell 100 that operates even with a film thickness of about 200 nm can be configured.
第１半導体層２と界面を形成する第２半導体層３の第１半導体層２側を向く面には、第１半導体層２の表面の溝５に対応する凹凸がある。第２半導体層３の凹凸も溝５と同様に規則的に形成されている。第２半導体層３の凹凸のピッチは、１ｎｍ以上１０ｎｍ以下であり、凹凸の高さは、１ｎｍ以上１０ｎｍ以下であることが好ましく、どちらも溝５のピッチと深さの範囲と同様である。 The surface of the second semiconductor layer 3 forming an interface with the first semiconductor layer 2 facing the first semiconductor layer 2 has irregularities corresponding to the grooves 5 on the surface of the first semiconductor layer 2. The unevenness of the second semiconductor layer 3 is also regularly formed like the groove 5. The pitch of the unevenness of the second semiconductor layer 3 is preferably 1 nm or more and 10 nm or less, and the height of the unevenness is preferably 1 nm or more and 10 nm or less, both of which are the same as the pitch and depth range of the groove 5.
第２半導体層３は、例えば、原子層堆積法（Atomic Layer Deposition；ＡＬＤ）、スパッタや化学気相成長法（Chemical Vapor Deposition；ＣＶＤ）で成膜することができる。 The second semiconductor layer 3 can be formed by, for example, an atomic layer deposition method (ALD), a sputtering method, or a chemical vapor deposition method (CVD).
第１半導体層２の伝導帯下端（Conduction Band Minimum：ＣＢＭ）の位置（Ｅｃｐ（ｅＶ））と第２半導体層３の伝導帯下の位置（Ｅｃｎ（ｅＶ））の差である伝導帯オフセット（ΔＥ＝Ｅｃｐ−Ｅｃｎ）は、−０．２ｅＶ以上０．６ｅＶ以下（−０．２ｅＶ≦ΔＥ≦＋０．６ｅＶ）であることが好ましい。伝導帯オフセットが０より大きいとｐｎ接合界面の伝導帯が不連続となりスパイクが生じる。伝導帯オフセットが０より小さいとｐｎ接合界面の伝導帯が不連続となりクリフが生じる。スパイク及びクリフはどちらも光生成電子の障壁となるため小さい方が好ましい。従って、伝導帯オフセットは、０．０ｅＶ以上０．４ｅＶ以下（０．０ｅＶ≦ΔＥ≦＋０．４ｅＶ）であることがより好ましい。ただし、ギャップ内準位を利用して伝導する場合はこの限りではない。ＣＢＭの位置は、以下の手法を用いて見積もることができる。電子占有準位の評価法である光電子分光により価電子帯上端（Valence Band Maximum：ＶＢＭ）を実測し、続いて測定対象の材料のバンドギャップを仮定してＣＢＭを算出する。しかしながら、実際のｐｎ接合界面では、相互拡散や陽イオンの空孔発生など理想的な界面を維持していないため、バンドギャップが変化する可能性が高い。このため、ＣＢＭも直接的に光電子放出の逆過程を利用する逆光電子分光により評価することが好ましい。具体的には、太陽電池表面を低エネルギーイオンエッチングと正・逆光電子分光測定の繰り返しにより、ｐｎ接合界面の電子状態を評価できる。 The conduction band offset (Ecn (eV)), which is the difference between the position (Ecp (eV)) of the lower end of the conduction band (CBM) of the first semiconductor layer 2 and the position (Ecn (eV)) below the conduction band of the second semiconductor layer 3. ΔE = Ecp-Ecn) is preferably −0.2 eV or more and 0.6 eV or less (−0.2 eV ≦ ΔE ≦ + 0.6 eV). If the conduction band offset is larger than 0, the conduction band at the pn junction interface becomes discontinuous and spikes occur. If the conduction band offset is less than 0, the conduction band at the pn junction interface becomes discontinuous and cliffs occur. Both spikes and cliffs serve as barriers for photogenerated electrons, so smaller ones are preferable. Therefore, the conduction band offset is more preferably 0.0 eV or more and 0.4 eV or less (0.0 eV ≦ ΔE ≦ + 0.4 eV). However, this does not apply when conducting using the level in the gap. The position of the CBM can be estimated using the following method. The upper end of the valence band (VBM) is actually measured by photoelectron spectroscopy, which is an evaluation method of the electron occupancy level, and then the CBM is calculated assuming the band gap of the material to be measured. However, since the actual pn junction interface does not maintain an ideal interface such as mutual diffusion and generation of cation vacancies, there is a high possibility that the band gap will change. Therefore, it is preferable to evaluate CBM by back photoelectron spectroscopy that directly utilizes the reverse process of photoelectron emission. Specifically, the electronic state of the pn junction interface can be evaluated by repeating low-energy ion etching and forward / reverse photoelectron spectroscopy measurement on the surface of the solar cell.
第２電極４は、第１電極１で挙げた電極と同様の透明電極を用いることが好ましい。第２電極４としては他にも金属ワイヤーを含む取出電極が設けられた多層グラフェン等の他の透明電極を採用することもできる。 As the second electrode 4, it is preferable to use a transparent electrode similar to the electrode mentioned in the first electrode 1. As the second electrode 4, another transparent electrode such as multilayer graphene provided with an extraction electrode containing a metal wire can also be adopted.
（反射防止膜）
実施形態の反射防止膜は、第１半導体層２へ光を導入しやすくするための膜であって、第１電極１上又は第２電極４上の第１半導体層２側とは反対側に形成されていることが好ましい。反射防止膜としては、例えば、ＭｇＦ２やＳｉＯ２を用いることが望ましい。なお、実施形態において、反射防止膜を省くことができる。各層の屈折率に応じて膜厚を調整する必要があるが、７０〜１３０ｎｍ（好ましくは、８０〜１２０ｎｍ）程度の厚さの薄膜を蒸着することが好ましい。
(Anti-reflective coating)
The antireflection film of the embodiment is a film for facilitating the introduction of light into the first semiconductor layer 2, and is on the first electrode 1 or on the side opposite to the first semiconductor layer 2 side on the second electrode 4. It is preferably formed. As the antireflection film, for example, MgF 2 or SiO 2 is preferably used. In the embodiment, the antireflection film can be omitted. It is necessary to adjust the film thickness according to the refractive index of each layer, but it is preferable to deposit a thin film having a thickness of about 70 to 130 nm (preferably 80 to 120 nm).
（第２実施形態）
第２実施形態は、太陽電池に関する。図４に、第２実施形態の太陽電池１０１の概念図を示す。図４に示すように、本実施形態に係る太陽電池１０１は、第１電極１と、第１電極１上に第１半導体層２と、第１半導体層２上に第２電極４と、を備える。第１電極１と第１半導体層２との間などには、図示しない中間層が含まれていてもよい。
(Second Embodiment)
The second embodiment relates to a solar cell. FIG. 4 shows a conceptual diagram of the solar cell 101 of the second embodiment. As shown in FIG. 4, the solar cell 101 according to the present embodiment has a first electrode 1, a first semiconductor layer 2 on the first electrode 1, and a second electrode 4 on the first semiconductor layer 2. Be prepared. An intermediate layer (not shown) may be included between the first electrode 1 and the first semiconductor layer 2.
第１実施形態の太陽電池１００と第２実施形態の太陽電池１０１との違いは、第２実施形態の太陽電池１０１には、第２半導体層３が含まれず、第１半導体層２の第２電極４側には、ｎ型の領域が含まれ、第１半導体層２がホモ接合していることである。このこと以外は第１実施形態と第２実施形態は共通する。 The difference between the solar cell 100 of the first embodiment and the solar cell 101 of the second embodiment is that the solar cell 101 of the second embodiment does not include the second semiconductor layer 3 and is the second of the first semiconductor layer 2. The electrode 4 side includes an n-type region, and the first semiconductor layer 2 is homobonded. Other than this, the first embodiment and the second embodiment are common.
第１半導体層２のｎ型の領域には、Ｍｎ、Ｍｇ、Ｃａ、Ｚｎ、Ｓｒ、Ｂａ、Ａｌ、Ｇａ、Ｉｎ、Ｎｂとランタノイドからなる群より選ばれる１種以上の元素が含まれることが好ましい。ｎ型の領域の厚さは、典型的には、５ｎｍ以上１００ｎｍ以下である。 The n-type region of the first semiconductor layer 2 may contain one or more elements selected from the group consisting of Mn, Mg, Ca, Zn, Sr, Ba, Al, Ga, In, Nb and lanthanoids. preferable. The thickness of the n-type region is typically 5 nm or more and 100 nm or less.
第１半導体層２のｎ型の領域側の表面で第２電極４を向く面に上記の規則的な溝５が形成されている。溝５については、第１実施形態と同様であるためその説明を省略する。 The regular groove 5 is formed on the surface of the first semiconductor layer 2 on the n-type region side facing the second electrode 4. Since the groove 5 is the same as that of the first embodiment, the description thereof will be omitted.
（第３実施形態）
第３実施形態は、積層体に関する。図５に第３実施形態の積層体１０２の概念図を示す。図５に示すように、本実施形態に係る積層体１０２は、第１電極１と、第１電極１上に第１半導体層２を備える。第１半導体層２の第１電極１側とは反対側の面には、溝５が形成されている。第２半導体層３及び第２電極４が含まれないこと以外は、第３実施形態と第１実施形態と共通する。
(Third Embodiment)
The third embodiment relates to a laminated body. FIG. 5 shows a conceptual diagram of the laminated body 102 of the third embodiment. As shown in FIG. 5, the laminate 102 according to the present embodiment includes a first electrode 1 and a first semiconductor layer 2 on the first electrode 1. A groove 5 is formed on the surface of the first semiconductor layer 2 opposite to the first electrode 1 side. It is common to the third embodiment and the first embodiment except that the second semiconductor layer 3 and the second electrode 4 are not included.
（第４実施形態）
第４実施形態は、多接合型太陽電池に関する。図６に第３実施形態の多接合型太陽電池２００の断面概念図を示す。図６の多接合型太陽電池２００は、光入射側に第１実施形態の太陽電池（第１太陽電池）１００と、第２太陽電池２０１を有する。第２太陽電池１０１の光電変換層のバンドギャップは、第１実施形態の太陽電池１００の第１半導体層２よりも小さいバンドギャップを有する。なお、実施形態の多接合型太陽電池は、３以上の太陽電池を接合させた太陽電池も含まれる。なお、第１実施形態の太陽電池１００の代わりに第２実施形態の太陽電池１０１を使用することができる。
(Fourth Embodiment)
A fourth embodiment relates to a multi-junction solar cell. FIG. 6 shows a conceptual cross-sectional view of the multi-junction solar cell 200 of the third embodiment. The multi-junction solar cell 200 of FIG. 6 has the solar cell (first solar cell) 100 of the first embodiment and the second solar cell 201 on the light incident side. The bandgap of the photoelectric conversion layer of the second solar cell 101 has a bandgap smaller than that of the first semiconductor layer 2 of the solar cell 100 of the first embodiment. The multi-junction solar cell of the embodiment also includes a solar cell in which three or more solar cells are joined. The solar cell 101 of the second embodiment can be used instead of the solar cell 100 of the first embodiment.
第１実施形態の太陽電池１０１の第１半導体層２のバンドギャップが約２．０ｅＶであるため、第２太陽電池１０１の光電変換層のバンドギャップは、１．０ｅＶ以上１．４ｅＶ以下であることが好ましい。第２太陽電池２０１の光電変換層としては、Ｉｎの含有比率が高いＣＩＧＳ系、ＣＩＴ系及びＣｄＴｅ系、酸化銅系のうちのいずれか１種以上の化合物半導体層又は結晶シリコンであることが好ましい。 Since the band gap of the first semiconductor layer 2 of the solar cell 101 of the first embodiment is about 2.0 eV, the band gap of the photoelectric conversion layer of the second solar cell 101 is 1.0 eV or more and 1.4 eV or less. Is preferable. The photoelectric conversion layer of the second solar cell 201 is preferably a compound semiconductor layer or crystalline silicon of any one or more of CIGS-based, CIT-based and CdTe-based, and copper oxide-based having a high In content ratio. ..
第１実施形態に係る太陽電池１００を第１太陽電池とすることで、第１太陽電池での意図しない波長域の光を吸収してしまうことによりボトムセル（第２太陽電池）の変換効率を低下させることを防ぐことができるので、効率の良い多接合型太陽電池とすることができる。 By using the solar cell 100 according to the first embodiment as the first solar cell, the conversion efficiency of the bottom cell (second solar cell) is lowered by absorbing light in an unintended wavelength range of the first solar cell. Since it can be prevented from being caused, an efficient multi-junction solar cell can be obtained.
（第５実施形態）
第５実施形態は、太陽電池モジュールに関する。図７に第５実施形態の太陽電池モジュール３００の斜視概念図を示す。図７の太陽電池モジュール３００は、第１太陽電池モジュール３０１と第２太陽電池モジュール３０２を積層した太陽電池モジュールである。第１太陽電池モジュール３０１は、光入射側であり、第１実施形態の太陽電池１００又は第２実施形態の太陽電池１０１を用いている。第２太陽電池モジュール３０２には、第２太陽電池２０１を用いることが好ましい。
(Fifth Embodiment)
A fifth embodiment relates to a solar cell module. FIG. 7 shows a perspective conceptual diagram of the solar cell module 300 of the fifth embodiment. The solar cell module 300 of FIG. 7 is a solar cell module in which the first solar cell module 301 and the second solar cell module 302 are laminated. The first solar cell module 301 is on the light incident side, and uses the solar cell 100 of the first embodiment or the solar cell 101 of the second embodiment. It is preferable to use the second solar cell 201 for the second solar cell module 302.
図８に太陽電池モジュール３００の断面概念図を示す。図８では、第１太陽電池モジュール３０１の構造を詳細に示し、第２太陽電池モジュール３０２の構造は示していない。第２太陽電池モジュール３０２では、用いる太陽電池の光電変換層などに応じて適宜、太陽電池モジュールの構造を選択する。図８の太陽電池モジュールは、複数の太陽電池１００（太陽電池セル）が横方向に並んで電気的に直列に接続した破線で囲われたサブモジュール３０３が複数含まれ、複数のサブモジュール３０３が電気的に並列もしくは直列に接続している。 FIG. 8 shows a conceptual cross-sectional view of the solar cell module 300. In FIG. 8, the structure of the first solar cell module 301 is shown in detail, and the structure of the second solar cell module 302 is not shown. In the second solar cell module 302, the structure of the solar cell module is appropriately selected according to the photoelectric conversion layer of the solar cell to be used and the like. The solar cell module of FIG. 8 includes a plurality of submodules 303 surrounded by broken lines in which a plurality of solar cells 100 (solar cell cells) are arranged side by side and electrically connected in series, and the plurality of submodules 303 are included. They are electrically connected in parallel or in series.
太陽電池１００は、スクライブされていて、隣り合う太陽電池１００は、上部側の第２電極４と下部側の第１電極１が接続している。第５実施形態の太陽電池１００も第１実施形態の太陽電池１００と同様に、基板１０、第１電極１、第１半導体層２、第２半導体層３と第２電極４を有する。 The solar cell 100 is scribed, and the adjacent solar cells 100 are connected to the second electrode 4 on the upper side and the first electrode 1 on the lower side. Like the solar cell 100 of the first embodiment, the solar cell 100 of the fifth embodiment also has a substrate 10, a first electrode 1, a first semiconductor layer 2, a second semiconductor layer 3, and a second electrode 4.
モジュール毎に出力電圧が異なると電圧の低い部分に電流が逆流したり、余計な熱を発生させたりすることがあるためモジュールの出力低下につながる。 If the output voltage is different for each module, the current may flow back to the low voltage part or extra heat may be generated, which leads to a decrease in the output of the module.
また、本願の太陽電池を用いると各波長帯に適した太陽電池を用いることができるため、トップセルやボトムセルの太陽電池を単体で用いたときと比較して効率良く発電できるようになり、モジュールの全体の出力が増大するため望ましい。 Further, when the solar cell of the present application is used, a solar cell suitable for each wavelength band can be used, so that it becomes possible to generate electricity more efficiently than when a top cell or bottom cell solar cell is used alone, and the module. This is desirable because it increases the overall output of.
モジュール全体の変換効率が高いと、照射された光エネルギーのうち、熱になるエネルギー割合を低くすることができる。そのためモジュール全体の温度が上昇による効率の低下を抑制することができる。 When the conversion efficiency of the entire module is high, the ratio of energy that becomes heat to the irradiated light energy can be reduced. Therefore, it is possible to suppress a decrease in efficiency due to an increase in the temperature of the entire module.
（第６実施形態）
第６実施形態は太陽光発電システムに関する。第５実施形態の太陽電池モジュール３００は、第６実施形態の太陽光発電システムにおいて、発電を行う発電機として用いることができる。実施形態の太陽光発電システムは、太陽電池モジュールを用いて発電を行うものであって、具体的には、発電を行う太陽電池モジュールと、発電した電気を電力変換する手段と、発電した電気をためる蓄電手段又は発電した電気を消費する負荷とを有する。図９に実施形態の太陽光発電システム４００の構成概念図を示す。図９の太陽光発電システムは、太陽電池モジュール４０１（３００）と、電力変換装置４０２と、蓄電池４０３と、負荷４０４とを有する。蓄電池４０３と負荷４０４は、どちらか一方を省略しても良い。負荷４０４は、蓄電池４０３に蓄えられた電気エネルギーを利用することもできる構成にしてもよい。電力変換装置４０２は、変圧や直流交流変換などの電力変換を行う回路又は素子を含む装置である。電力変換装置４０２の構成は、発電電圧、蓄電池４０３や負荷４０４の構成に応じて好適な構成を採用すればよい。
(Sixth Embodiment)
The sixth embodiment relates to a photovoltaic power generation system. The solar cell module 300 of the fifth embodiment can be used as a generator for generating electricity in the photovoltaic power generation system of the sixth embodiment. The photovoltaic power generation system of the embodiment uses a solar cell module to generate electricity. Specifically, the photovoltaic cell module that generates electricity, a means for converting the generated electricity into electric power, and the generated electricity are used. It has a storage means for storing electricity or a load for consuming the generated electricity. FIG. 9 shows a conceptual diagram of the configuration of the photovoltaic power generation system 400 of the embodiment. The photovoltaic power generation system of FIG. 9 includes a solar cell module 401 (300), a power conversion device 402, a storage battery 403, and a load 404. Either one of the storage battery 403 and the load 404 may be omitted. The load 404 may be configured so that the electric energy stored in the storage battery 403 can be used. The power conversion device 402 is a device including a circuit or element that performs power conversion such as transformation or DC / AC conversion. As the configuration of the power conversion device 402, a suitable configuration may be adopted according to the configuration of the generated voltage, the storage battery 403, and the load 404.
太陽電池モジュール３００に含まれる受光したサブモジュール３０１に含まれる太陽電池セルが発電し、その電気エネルギーは、コンバーター４０２で変換され、蓄電池４０３で蓄えられるか、負荷４０４で消費される。太陽電池モジュール４０１には、太陽電池モジュール４０１を常に太陽に向けるための太陽光追尾駆動装置を設けたり、太陽光を集光する集光体を設けたり、発電効率を向上させるための装置等を付加することが好ましい。 The solar cell included in the received submodule 301 included in the solar cell module 300 generates electricity, and the electric energy is converted by the converter 402 and stored in the storage battery 403 or consumed by the load 404. The solar cell module 401 is provided with a solar tracking drive device for always directing the solar cell module 401 toward the sun, a condenser for condensing sunlight, a device for improving power generation efficiency, and the like. It is preferable to add it.
太陽光発電システム４００は、住居、商業施設や工場などの不動産に用いられたり、車両、航空機や電子機器などの動産に用いられたりすることが好ましい。実施形態の変換効率に優れた太陽電池を太陽電池モジュール４０１に用いることで、発電量の増加が期待される。 The photovoltaic power generation system 400 is preferably used for real estate such as houses, commercial facilities and factories, and is preferably used for movables such as vehicles, aircraft and electronic devices. It is expected that the amount of power generation will be increased by using the solar cell having excellent conversion efficiency of the embodiment for the solar cell module 401.
太陽光発電システム４００の利用例として車両を示す。図１０に車両５００の構成概念図を示す。図１０の車両５００は、車体５０１、太陽電池モジュール５０２、電力変換装置５０３、蓄電池５０４、モーター５０５とタイヤ（ホイール）５０６を有する。車体５０１の上部に設けられた太陽電池モジュール５０１で発電した電力は、電力変換装置５０３変換されて、蓄電池５０４にて充電されるか、モーター５０５等の負荷で電力が消費される。太陽電池モジュール５０１又は蓄電池５０４から供給される電力を用いてモーター５０５によってタイヤ（ホイール）５０６を回転させることにより車両５００を動かすことができる。太陽電池モジュール５０１としては、多接合型ではなく、第１実施形態又は第２実施形態の太陽電池１００、１０１を備えた第１太陽電池モジュールだけで構成されていてもよい。透過性のある太陽電池モジュール５０１を採用する場合は、車体５０１の上部に加え、車体５０１の側面に発電する窓として太陽電池モジュール５０１を使用することも好ましい。 A vehicle is shown as an example of use of the photovoltaic power generation system 400. FIG. 10 shows a conceptual diagram of the configuration of the vehicle 500. The vehicle 500 of FIG. 10 has a vehicle body 501, a solar cell module 502, a power conversion device 503, a storage battery 504, a motor 505, and a tire (wheel) 506. The electric power generated by the solar cell module 501 provided on the upper part of the vehicle body 501 is converted by the electric power conversion device 503 and charged by the storage battery 504, or the electric power is consumed by a load such as a motor 505. The vehicle 500 can be moved by rotating the tire (wheel) 506 by the motor 505 using the electric power supplied from the solar cell module 501 or the storage battery 504. The solar cell module 501 may be composed of only the first solar cell module including the solar cells 100 and 101 of the first embodiment or the second embodiment, instead of the multi-junction type. When a transmissive solar cell module 501 is adopted, it is also preferable to use the solar cell module 501 as a window for generating electricity on the side surface of the vehicle body 501 in addition to the upper part of the vehicle body 501.
以下、実施例に基づき本発明をより具体的に説明するが、本発明は以下の実施例に限定されるものではない。 Hereinafter, the present invention will be described in more detail based on Examples, but the present invention is not limited to the following Examples.
（実施例１）
白板ガラス基板上に、裏面側の第１電極としてＩＴＯ透明導電膜、その上にＳｂドープしたＳｎＯ２透明導電膜を堆積する。透明な第１電極上に酸素とアルゴンガスの混合ガス雰囲気中でスパッタリング法により基板を４５０℃で加熱して亜酸化銅化合物を成膜し、穏やかな条件で冷却する。その後、電子堆積法によりｐ−亜酸化銅層上にｎ型のＺｎ０．８Ｇｅ０．２Ｏｘを堆積する。その後表面側の第２電極としてＡＺＯ透明導電膜を堆積する。その上に反射防止膜としてＭｇＦ２を堆積して太陽電池を得る。
(Example 1)
An ITO transparent conductive film is deposited on a white plate glass substrate as a first electrode on the back surface side, and an Sb-doped SnO 2 transparent conductive film is deposited therein. A substrate is heated at 450 ° C. by a sputtering method in a mixed gas atmosphere of oxygen and argon gas on a transparent first electrode to form a cuprous oxide compound, and the substrate is cooled under mild conditions. Then, n-type Zn 0.8 Ge 0.2 Ox is deposited on the p-copper oxide layer by an electron deposition method. After that, an AZO transparent conductive film is deposited as a second electrode on the surface side. MgF 2 is deposited on it as an antireflection film to obtain a solar cell.
（実施例２）
白板ガラス基板上に、裏面側の第１電極としてＩＴＯ透明導電膜、その上にＳｂドープしたＳｎＯ２透明導電膜を堆積する。透明な第１電極上に酸素とアルゴンガスの混合ガス雰囲気中でスパッタリング法により基板を６００℃で加熱して亜酸化銅化合物を成膜し、穏やかな条件で冷却する。その後、電子堆積法によりｐ−亜酸化銅層上にｎ型のＺｎ０．８Ｇｅ０．２Ｏｘを堆積する。その後表面側の第２電極としてＡＺＯ透明導電膜を堆積する。その上に反射防止膜としてＭｇＦ２を堆積して太陽電池を得る。
(Example 2)
An ITO transparent conductive film is deposited on a white plate glass substrate as a first electrode on the back surface side, and an Sb-doped SnO 2 transparent conductive film is deposited therein. A substrate is heated at 600 ° C. by a sputtering method in a mixed gas atmosphere of oxygen and argon gas on a transparent first electrode to form a cuprous oxide compound, and the substrate is cooled under mild conditions. Then, n-type Zn 0.8 Ge 0.2 Ox is deposited on the p-copper oxide layer by an electron deposition method. After that, an AZO transparent conductive film is deposited as a second electrode on the surface side. MgF 2 is deposited on it as an antireflection film to obtain a solar cell.
（実施例３）
白板ガラス基板上に、裏面側の第１電極としてＩＴＯ透明導電膜、その上にＳｂドープしたＳｎＯ２透明導電膜を堆積する。透明な第１電極上に酸素とアルゴンガスの混合ガス雰囲気中でスパッタリング法により基板を３００℃で加熱して亜酸化銅化合物を成膜し、穏やかな条件で冷却する。その後、電子堆積法によりｐ−亜酸化銅層上にｎ型のＺｎ０．８Ｇｅ０．２Ｏｘを堆積する。その後表面側の第２電極としてＡＺＯ透明導電膜を堆積する。その上に反射防止膜としてＭｇＦ２を堆積して太陽電池を得る。
(Example 3)
An ITO transparent conductive film is deposited on a white plate glass substrate as a first electrode on the back surface side, and an Sb-doped SnO 2 transparent conductive film is deposited therein. A substrate is heated at 300 ° C. by a sputtering method in a mixed gas atmosphere of oxygen and argon gas on a transparent first electrode to form a cuprous oxide compound, and the substrate is cooled under mild conditions. Then, by the electron deposition method, n-type Zn 0.8 Ge0 was applied on the p-copper oxide layer . 2 Ox is deposited. After that, an AZO transparent conductive film is deposited as a second electrode on the surface side. MgF 2 is deposited on it as an antireflection film to obtain a solar cell.
（比較例１）
亜酸化銅化合物の成膜後、大気中で急冷したこと以外は、実施例１と同条件で太陽電池を得る。
(Comparative Example 1)
After forming the cuprous oxide compound, a solar cell is obtained under the same conditions as in Example 1 except that it is rapidly cooled in the atmosphere.
（比較例２）
亜酸化銅化合物の成膜後、大気中で急冷したこと以外は、実施例２と同条件で太陽電池を得る。
(Comparative Example 2)
After forming the cuprous oxide compound, a solar cell is obtained under the same conditions as in Example 2 except that it is rapidly cooled in the atmosphere.
（比較例３）
亜酸化銅化合物の成膜後、大気中で急冷したこと以外は、実施例３と同条件で太陽電池を得る。
(Comparative Example 3)
After forming the cuprous oxide compound, a solar cell is obtained under the same conditions as in Example 3 except that it is rapidly cooled in the atmosphere.
（比較例４）
亜酸化銅化合物の成膜後、真空アニールを実施したこと以外は、実施例１と同条件で太陽電池を得る。
(Comparative Example 4)
A solar cell is obtained under the same conditions as in Example 1 except that vacuum annealing is performed after forming the cuprous oxide compound.
実施例の太陽電池には規則的な溝が形成されるが、比較例の太陽電池には規則的な溝が形成されない。より具体的には、比較例１−３の太陽電池は、溝がほとんど確認できず、比較例４の太陽電池は、規則的ではない溝が一部形成され、その溝のピッチや深さは好適な範囲内ではない。規則的な溝が形成されていない比較例4の太陽電池は、実施例の太陽電池と比べて透過率及び変換効率が劣る。実施例の太陽電池の溝は、溝のピッチ及び深さがいずれも好適な範囲内であり、規則的な溝が太陽電池の特性向上に寄与する。第１半導体層の表面に規則的な溝を形成することによって、規則的な溝を有しない同構成の太陽電池よりも透過率及び変換効率が高い太陽電池を得ることができる。規則的な溝ができるように、亜酸化銅膜の成膜後は穏やかな条件で冷却することが好ましい。亜酸化銅を用いた太陽電池は透過率に優れるため、亜酸化銅を用いた太陽電池をトップセルに用いた多接合型太陽電池において、太陽電池全体の発電量向上にも寄与する。
明細書中、一部の元素は元素記号のみで表している。
The solar cells of Examples form regular grooves, but the solar cells of Comparative Examples do not form regular grooves. More specifically, in the solar cell of Comparative Example 1-3, grooves could hardly be confirmed, and in the solar cell of Comparative Example 4, some irregular grooves were formed, and the pitch and depth of the grooves were different. Not within a suitable range. The solar cell of Comparative Example 4 in which regular grooves are not formed is inferior in transmittance and conversion efficiency to the solar cell of Example. In the grooves of the solar cell of the embodiment, the pitch and the depth of the grooves are both within a suitable range, and the regular grooves contribute to the improvement of the characteristics of the solar cell. By forming regular grooves on the surface of the first semiconductor layer, it is possible to obtain a solar cell having higher transmittance and conversion efficiency than a solar cell having the same configuration without regular grooves. After forming the cuprous oxide film, it is preferable to cool it under mild conditions so that regular grooves are formed. Since a solar cell using cuprous oxide has excellent transmittance, it also contributes to an improvement in the power generation amount of the entire solar cell in a multijunction type solar cell using a solar cell using cuprous oxide as a top cell.
In the specification, some elements are represented only by element symbols.
以上、本発明の実施形態を説明したが、本発明は上記実施形態そのままに限定解釈されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより種々の発明を形成することができる。例えば、変形例の様に異なる実施形態にわたる構成要素を適宜組み合わせても良い。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments as they are, and at the implementation stage, the components can be modified and embodied without departing from the gist thereof. In addition, various inventions can be formed by an appropriate combination of the plurality of components disclosed in the above-described embodiment. For example, components over different embodiments may be appropriately combined as in the modified example.
１００、１０１…太陽電池（第１太陽電池、トップセル）、１…第１電極、２…第１半導体層、３…第２半導体層、４…第２電極、５…溝、１０２…積層体、２００…多接合型太陽電池、２０１…第２太陽電池（ボトムセル）、３００…太陽電池モジュール、３０１第１太陽電池モジュール、３０２…第２太陽電池モジュール、１０…基板、３０３…サブモジュール、４００…太陽光発電システム、４０１…太陽電池モジュール、４０２…電力変換装置、４０３…蓄電池、４０４…負荷、５００…車両、５０１…車体、５０２…太陽電池モジュール、５０３…電力変換装置、５０４…蓄電池、５０５…モーター、５０６…タイヤ（ホイール）
100, 101 ... Solar cell (first solar cell, top cell), 1 ... 1st electrode, 2 ... 1st semiconductor layer, 3 ... 2nd semiconductor layer, 4 ... 2nd electrode, 5 ... groove, 102 ... Laminate , 200 ... Multi-junction solar cell, 201 ... Second solar cell (bottom cell), 300 ... Solar cell module, 301 First solar cell module, 302 ... Second solar cell module, 10 ... Board, 303 ... Submodule, 400 ... Solar power generation system, 401 ... Solar cell module, 402 ... Power converter, 403 ... Storage battery, 404 ... Load, 500 ... Vehicle, 501 ... Body, 502 ... Solar cell module, 503 ... Power converter, 504 ... Storage battery, 505 ... motor, 506 ... tire (wheel)
Claims (11)
前記第１電極上に第１半導体層と、
前記第１半導体層上に第２半導体層と、
前記第２半導体層上に透明な第２電極とを有し、
前記第１半導体層の第２半導体層側を向く面には、規則的な溝が形成されている太陽電池。 With a transparent first electrode
A first semiconductor layer on the first electrode,
On the first semiconductor layer, a second semiconductor layer and
It has a transparent second electrode on the second semiconductor layer.
A solar cell in which regular grooves are formed on the surface of the first semiconductor layer facing the second semiconductor layer.
前記溝は、第１半導体層の結晶粒の粒界方向に延びる請求項１ないし５のいずれか１項に記載の太陽電池。 The first semiconductor layer is a semiconductor layer containing crystal grains mainly composed of Cu 2 O.
The solar cell according to any one of claims 1 to 5, wherein the groove extends in the grain boundary direction of the crystal grains of the first semiconductor layer.
前記第１電極上に第１半導体層とを有し、
前記第１半導体層の前記第１電極側とは反対側を向く面には、規則的な溝が形成されている積層体。 With a transparent first electrode
It has a first semiconductor layer on the first electrode.
A laminate in which regular grooves are formed on the surface of the first semiconductor layer facing the side opposite to the first electrode side.
A photovoltaic power generation system that generates electricity using the solar cell module according to claim 10.
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| PCT/JP2020/010296 WO2021002058A1 (en) | 2019-07-02 | 2020-03-10 | Solar cell, laminated body, multi-junction solar cell, solar cell module, and solar power generation system |
| EP20714710.9A EP3994732A1 (en) | 2019-07-02 | 2020-03-10 | Solar cell, laminated body, multi-junction solar cell, solar cell module, and solar power generation system |
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| US11908970B2 (en) | 2020-03-23 | 2024-02-20 | Kabushiki Kaisha Toshiba | Process for manufacturing multilayered thin film, method of manufacturing solar cell, and method for manufacturing solar cell module |
| WO2024090555A1 (en) * | 2022-10-28 | 2024-05-02 | 三菱マテリアル株式会社 | Method for producing cuprous oxide, and cuprous oxide film |
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| JP2024135402A (en) * | 2023-03-22 | 2024-10-04 | 株式会社東芝 | Solar cells, multi-junction solar cells, solar cell modules and photovoltaic power generation systems |
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