JP2021048411A - Plasma processing device and plasma processing method - Google Patents

Abstract

To provide a plasma processing device and a plasma processing method enhancing yield.SOLUTION: In a plasma processing device or processing method for processing a wafer to be processed placed on a surface of a sample table disposed in a processing chamber inside a vacuum container by using plasma formed in the processing chamber, the wafer is processed while adjusting high frequency power supplied to a first electrode placed inside the sample table during the processing, and to a second electrode placed inside a ring-like member made of a dielectric placed on an outer peripheral side of a placing surface of the sample table and connected via a circuit in which capacitors and coils are arranged in series in this order.SELECTED DRAWING: Figure 1

Description

The present invention is a plasma processing apparatus or plasma processing method for processing a substrate-like sample such as a semiconductor wafer placed and held on a sample table arranged in a processing chamber inside a vacuum vessel using plasma in the processing chamber. In particular, the present invention relates to a plasma processing apparatus or a plasma processing method for processing a sample by supplying high-frequency power to a sample table during processing to form a bias potential above the upper surface of the sample.

In the process of manufacturing a semiconductor device, in the process of forming the circuit or wiring structure of the device, the film layer to be processed is a film structure having a plurality of film layers including a mask formed in advance on the upper surface of a sample such as a semiconductor wafer. Is generally etched using plasma. In recent years, with the improvement of the degree of integration of semiconductor devices, further improvement of the accuracy of processing using such plasma is required, and the portion on the outer peripheral side of the wafer is the center side of the processing result. Reduce the area where the processing variation is out of the permissible range on the outer peripheral side of the wafer so that the number of devices that can be manufactured per wafer can be increased and the processing efficiency can be improved. Is required.

Such a plasma processing apparatus is generally used for processing by exhausting a processing chamber in which plasma is formed in a vacuum vessel and a vacuum container, a processing chamber in which a sample is arranged and a depressurized inner space, and a processing chamber. It is equipped with a vacuum exhaust device, which makes the pressure of a suitable predetermined degree of vacuum. Further, a gas supply device connected to a vacuum vessel or a vacuum processing chamber to supply gas for processing a sample into the processing chamber, a sample table on which a wafer as a material to be processed is placed and held, and a processing chamber. It is provided with a plasma generator or the like that supplies an electric field or a magnetic field for generating plasma to the processing chamber.

Areas where processing characteristics such as the processing speed and the resulting shape after processing vary between the outer peripheral side portion and the central side portion of the wafer, for example, the etching processing speed (rate) changes. In order to make the wafer smaller, it has been considered to make the strength and distribution of the electric field formed above the upper surface of the wafer from the central portion to the outer peripheral side portion closer to more uniform. That is, the change in the etching rate on the outer peripheral side of the wafer increases the rate as a result of the concentration of the electric field occurring in the outer peripheral region of the wafer and the bias of the plasma potential and the distribution of charged particles. Therefore, by suppressing such concentration of the electric field, more uniform processing can be realized up to the outer peripheral side portion of the wafer. For this purpose, the strength of the electric field formed in the region surrounding the outer peripheral portion of the wafer and its distribution are adjusted to adjust the thickness of the sheath formed above the upper surface of the wafer with respect to the in-plane direction of the wafer. In particular, it is effective to bring the area closer to the outer peripheral side in the radial direction more uniformly.

As a conventional technique of such a plasma processing apparatus, as disclosed in Japanese Patent Application Laid-Open No. 2007-258417 (Patent Document 1), a member having conductivity is arranged so as to surround the outer peripheral side of the wafer. It is known that a DC voltage is applied to a focus ring to control an electric field between the outer peripheral edge of a wafer and a region in the vicinity thereof during etching. In this conventional technique, the DC voltage value is changed so as to maintain the initial performance according to the amount of the focus ring whose upper surface faces the plasma is scraped and consumed by the interaction with the plasma.

Further, as shown in Japanese Patent Application Laid-Open No. 2012-227278 (Patent Document 2), a conductor ring arranged on the outer peripheral side of the wafer mounting surface of the sample table and surrounding the wafer and a dielectric covering the upper surface of the ring above the ring. A configuration is disclosed in which a ring cover made of a body is provided, and a high-frequency power is supplied to a ring made of a conductor so as not to be electrically coupled with plasma formed above the ring cover in a processing chamber. Further, in the present prior art, the height of the conductor ring is made higher than the upper surface of the wafer or the sample table on which the wafer is placed, and the height of the bias isopotential surface formed above the wafer and the conductor ring and the resulting plasma. It is disclosed that the variation in the angle at which the charged particles inside the wafer is incident on the wafer is reduced in the range from the center side to the outer periphery side of the wafer to reduce the variation in the shape after processing as a result of processing.

Further, in Japanese Patent Application Laid-Open No. 2011-9351 (Patent Document 3), the amount of high-frequency power for forming a bias potential applied to a conductor-made focus ring arranged around a wafer on the outer peripheral side of a sample table is the focus ring. It is disclosed that it is adjusted according to the amount of consumption of.

JP-A-2007-258417 Japanese Unexamined Patent Publication No. 2012-227278 Japanese Unexamined Patent Publication No. 2011-9351

The above-mentioned prior art has caused problems because the following points have not been sufficiently considered.

That is, as a result of the examination by the inventors, it was found that although all of them have some effect on improving the uniformity of the outer peripheral portion of the wafer, they can be used only for a limited purpose and there is a limit to the performance improvement. ..

Patent Document 1 describes a conductor ring arranged on the outer peripheral side of the surface on which the wafer of the sample table is placed and to which DC power is applied, in order to combine plasma and DC power formed above the upper surface thereof. The upper surface is exposed to the space above the treatment chamber. In such a configuration, the conductor ring is scraped due to the interaction with the plasma such as the charged particles inside the plasma colliding with the upper surface of the conductor, and the material is deteriorated. In order to suppress this, when the upper surface of the conductor ring is covered with a member made of a dielectric or an insulator as described in Patent Document 2, it becomes difficult for the DC power to be coupled with the plasma, and the wafer by the ring is formed. It becomes difficult to adjust the strength and distribution of the electric field on the outer peripheral side or above the ring.

Further, in Patent Document 2, the conductor ring arranged on the outer peripheral side of the wafer mounting surface of the sample table is described on the base material which is a metal electrode arranged inside the sample table below the mounting surface. It is mounted on a step (recessed portion) arranged on the outer peripheral side of the mounting surface, and has a configuration in which high-frequency power for forming a bias potential supplied to the base material is distributed and supplied. However, in such a configuration, since the configuration for appropriately changing the value of the voltage formed above the upper surface of the ring is not provided, the bias potential formed by the electrodes below the mounting surface may be too large. However, the potential of the bias above the conductor ring arranged on the outer peripheral side of the wafer cannot be adjusted to an appropriate range and becomes larger than necessary, and the degree of concentration of the electric field on the outer peripheral side of the wafer increases and the etching rate increases. There was a risk that the uniformity of the treatment characteristics would be impaired, such as local increase and bias, and the treatment yield would decrease.

Further, Patent Document 3 includes a distributor on a supply path of high-frequency power for forming a bias potential supplied to a base material which is an electrode inside a sample table, and is adjusted to a predetermined ratio by the distributor and divided. The generated high-frequency power is arranged on the outer peripheral side of the wafer mounting surface of the base material and supplied to the conductor ring surrounded by the insulator cover. However, in this configuration, it was found that most of the high-frequency power is cut by the insulator of the cover surrounding the conductor ring, so that the outer peripheral portion cannot be efficiently controlled as it is.

In the above-mentioned conventional technique, high-frequency power cannot be adjusted and supplied to a conductor ring arranged on the outer peripheral side of the wafer so as to obtain a desired electric field distribution, and the processing characteristics on the outer peripheral side of the wafer cannot be supplied. No consideration was given to the problem that the variation in the central part of the wafer becomes large and the processing yield is impaired. An object of the present invention is to provide a plasma processing apparatus or plasma processing method with improved yield.

The above purpose is plasma treatment in which the wafer to be processed placed on the mounting surface located on the upper part of the sample table arranged in the processing chamber inside the vacuum vessel is treated by using the plasma formed in the processing chamber. An apparatus, which is a ring-shaped member arranged on the upper part of the sample table and arranged on the outer peripheral side of the previously described mounting surface on which the wafer is mounted, and is made of a dielectric material arranged so as to surround the mounting surface. The ring-shaped member of the above and the first electrode arranged inside the sample table below the above-mentioned mounting surface, which is electrically connected to the first high-frequency power source and has a bias potential on the wafer during processing of the wafer. A second electrode to which high-frequency power is supplied to form a ring, and a second electrode arranged inside the ring-shaped member so as to surround the above-mentioned mounting surface in a ring shape and electrically connected to a second high-frequency power source. The electrode, the second electrode, and the second high-frequency power supply are electrically connected, and power from the second high-frequency power supply is supplied to the second electrode during processing of the wafer to supply power. This is achieved by including a circuit arranged on the path and having capacitors and coils arranged in series in this order in the direction from the second high frequency power source toward the second electrode.

Further, it is a plasma processing method in which a wafer to be processed placed on a sample table surface arranged in a processing chamber inside a vacuum vessel is processed by using plasma formed in the processing chamber, and during processing of the wafer. , The high-frequency power supply supplies power from the first high-frequency power supply to the first electrode arranged inside the sample table, and the dielectric arranged on the outer peripheral side of the surface on which the wafer of the sample table is placed. The second electrode arranged inside the ring-shaped member of the body is provided with a step of supplying electric power from the second high-frequency power source to process the wafer, and the electric power from the second high-frequency power source is the capacitor and the electric power from the second high-frequency power source. This is achieved by feeding the coils to the second electrode through circuits connected in series in this order.

According to the present invention, by providing a coil in front of the conductive ring to which a high frequency is applied, it is possible to form an insulating susceptor ring and an LC circuit which become a capacitive capacitor, and the high frequency is efficiently contributed to the wafer edge. It becomes possible.

It is a vertical sectional view schematically showing the outline of the structure of the plasma processing apparatus which concerns on embodiment of this invention. FIG. 5 is a vertical cross-sectional view schematically showing an outline of a configuration of a modified example of the plasma processing apparatus according to the embodiment shown in FIG. 1. It is a vertical cross-sectional view schematically showing the configuration of the outer peripheral side portion of the sample table according to the embodiment shown in FIG. 1 in an enlarged manner. It is a vertical cross-sectional view schematically showing an enlarged modification of the configuration of the outer peripheral side portion of the sample table according to the embodiment shown in FIG. 1. It is a vertical sectional view which shows the structure of the upper part of the susceptor of an Example shown in FIG. 1 in an enlarged manner. It is a vertical cross-sectional view which shows typically the operation of the Example shown in FIG. It is a vertical cross-sectional view which shows typically the structure of the modification of the upper part of the susceptor of the Example shown in FIG. It is a graph which shows typically the distribution example of the etching rate in the radial direction of the upper surface of the wafer in the Example shown in FIG. 5 and the prior art. FIG. 5 is a vertical cross-sectional view schematically showing an enlarged configuration of another modified example of the outer peripheral side portion of the sample table according to the embodiment shown in FIG. 1. FIG. 10 is a graph showing the result of detecting the distribution of the etching rate in the radial direction of the wafer processed by the plasma processing apparatus according to the embodiment shown in FIG. 5 or 6. 3 is a vertical cross-sectional view schematically showing an outline of a configuration of a susceptor of the plasma processing apparatus according to the embodiment shown in FIG. 1, and a graph schematically showing an example of a data table used by the plasma processing apparatus. 6 is a graph schematically showing another example of a data table used by the plasma processing apparatus according to the embodiment shown in FIG. 1. It is a figure which shows an example of the screen displayed by the display provided in the plasma processing apparatus which concerns on the Example shown in FIG. FIG. 5 is a vertical cross-sectional view schematically showing an outline of the configuration of another modified example in the vicinity of the susceptor of the plasma processing apparatus according to the embodiment shown in FIG. It is a graph which shows typically the result obtained by increasing or decreasing the resistance value of the variable resistance in the load impedance variable box 130 shown in FIG. It is a vertical cross-sectional view which shows typically the action which the structure of the Example shown in FIG. 5 plays.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Hereinafter, examples of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 is a vertical cross-sectional view schematically showing an outline of a configuration of a plasma processing apparatus according to an embodiment of the present invention. In this example, an electric field having a specific frequency in the microwave band is used as the electric field for forming plasma in the processing chamber, and a magnetic field having a strength corresponding to the frequency of the electric field is supplied to the processing chamber by the interaction between them. Shown shows a microwave ECR plasma etching apparatus that generates ECR (Electron Cyclotron Response) to excite atoms or molecules of gas supplied into a processing chamber to form plasma and etch a film to be processed on the upper surface of a semiconductor wafer. There is.

The plasma processing apparatus of this embodiment forms a plasma inside a vacuum container 101 in which a processing chamber 104 having a cylindrical shape is arranged inside, and inside the processing chamber 104 arranged above and around the vacuum container 101. A plasma forming means for supplying an electric field and a magnetic field for the purpose of forming a vacuum, and a vacuum exhausting means having a turbo molecular pump connected below the vacuum vessel 101 to exhaust the inside of the processing chamber 104 and a vacuum pump for roughing such as a rotary pump. I have. A disk-shaped, for example, quartz dielectric window 103 is arranged in the upper part of the processing chamber 104 to airtightly partition the inside and outside of the processing chamber 104, and covers the upper part of the processing chamber 104 to form a ceiling surface thereof. There is.

In the processing chamber 104 below the dielectric window 103, a shower plate 102 made of a dielectric (for example, made of quartz) in which a plurality of through holes for introducing a gas for etching is arranged is arranged. Between the shower plate 102 and the dielectric window 103, a substantially cylindrical space having a small height in which the supplied etching gas is diffused and filled is arranged, and this space supplies the etching gas. It is connected to the gas supply device 117 by a gas introduction pipeline. Further, a vacuum exhaust port 110 communicated with the lower part of the processing chamber 104 is arranged below the vacuum container 101, and a vacuum exhaust device which is a vacuum exhaust means including a turbo molecular pump (not shown) is connected below the vacuum exhaust port 110. Has been done.

As a plasma forming means, a waveguide 107 that propagates an electric field introduced into the processing chamber 104 is arranged above the dielectric window 103. The waveguide 107 of this embodiment is roughly divided into two parts, and the cross section extending vertically upward above the processing chamber 104 is connected to a circular cylindrical tube part and an upper end portion thereof. It has a prismatic section with a rectangular cross section whose axis direction is bent from the cylindrical portion and extends in the horizontal direction. At the end of the prismatic tube portion, an electric field generating power source 106 such as a magnetron formed by transmitting an electric field of microwaves is arranged, and the electric field formed by being oscillated by the electric field generating power source 106 is a waveguide. After propagating through 105 and entering a cylindrical space for resonance connected below the lower end of the cylindrical tube portion and being set to a predetermined electric field mode, it passes through the dielectric window 103 and enters the processing chamber 104. Is supplied to.

The frequency of the electromagnetic wave is not particularly limited, but in this embodiment, a 2.45 GHz microwave is used. Further, on the outer peripheral side of the processing chamber 104 of the vacuum vessel 101, a magnetic field generating coil 107, which is a solenoid coil for forming a magnetic field to be supplied into the processing chamber 104, is arranged so as to surround the upper side and the side of the processing chamber 104. There is. The electric field propagated and introduced into the processing chamber 104 causes an interaction with the magnetic field introduced into the processing chamber 104 formed by the magnetic field generating coil 107, and is also supplied to the processing chamber 104 for etching gas. A plasma is generated in the processing chamber 104 by exciting the particles of the above.

Further, a sample table 108 is arranged at the lower part in the processing chamber 104. The upper surface of the sample table 108 is covered with a dielectric film, which is a film of a material containing a dielectric formed by thermal spraying, and a wafer 109, which is a substrate-like sample to be processed, is placed on the upper surface of the dielectric film. Is retained. The mounting surface on which the wafer 109 is mounted faces the dielectric window 103 or the shower plate 102.

A conductor film 111 made of a conductor material is arranged inside the dielectric film, and a DC power supply 126 is connected via a high frequency filter 125 to form a film-like electrode. Further, the sample table 111 has a substantially cylindrical shape in which the processing chamber 104 and the shaft are arranged together, and an electrode in which the first high frequency power supply 124 is electrically connected via a matching unit 129. A metal base material 131 having a disk shape is arranged.

On the outer peripheral side of the dielectric film (dielectric film) arranged on the upper surface of the base material 131 and having a substantially circular shape in accordance with the shape of the wafer 109, a ring-shaped member made of a dielectric such as quartz is formed. The susceptor 113 is arranged. Therefore, the height of the base material 131 on the outer peripheral side of the dielectric film, which is the mounting surface of the sample table 108, is recessed and lowered to form a step with the upper surface of the dielectric film. The susceptor 113 is placed in the ring-shaped recessed portion, and the upper surface and the side surface of the sample table 108 are covered and protected from plasma.

In such a plasma processing apparatus 100, the vacuum container 101 is connected to a transport vacuum container (not shown) on the side surface thereof via a gate, and is arranged in the transport vacuum container (vacuum transport container). The unprocessed wafer 109 placed and held on the arm of the robot is carried into the processing chamber 104 through the gate. The wafer 109 conveyed into the processing chamber 104 is delivered to the sample table 108 from the arm and placed on the dielectric film constituting the upper surface thereof. After that, the wafer 109 is attracted to and held on the dielectric film by the electrostatic force formed between the conductive film 111 and the conductive film 111 which is supplied from the DC power supply 126 to the conductive film 111 to the DC voltage.

The processing chamber 104 is airtightly closed to the vacuum transfer container by a gate valve that opens and closes a gate (not shown) during processing, and the inside is sealed. After that, the etching gas is introduced into the processing chamber 104 from the shower plate 102, and the vacuum exhaust device 108 is driven, and the pressure inside the processing chamber 104 depends on the balance between the gas supply rate and the exhaust rate. Maintained at a given pressure. In this state, the plasma 116 is formed in the processing chamber 104 by the interaction of the electric field and the magnetic field supplied from the plasma forming means.

When the plasma 116 is formed in the processing chamber 104 above the sample table 108, high-frequency power is supplied to the base material 131 from the high-frequency power supply 124 connected to the base material 131 in the sample table 108, and the high-frequency power is supplied to the base material 131 on the upper surface of the sample table 108. Bias potentials are formed on the dielectric film and on the wafer 108. Due to the potential difference between this bias potential and the potential of the plasma 116, charged particles such as ions in the plasma 116 are attracted toward the upper surface of the wafer 109 and collide with the surface of the film structure formed in advance on the upper surface of the wafer 109 to cause the wafer. The film layer to be processed of the film structure for forming the circuit of the semiconductor device arranged on the upper surface of 109 is etched.

Although not shown, a gas for promoting heat transfer such as helium is introduced between the back surface of the wafer 109 and the upper surface of the dielectric film of the sample table 108 during the etching process, and the sample table is used. The temperature of the wafer 109 can be adjusted to a value in a range suitable for processing by promoting heat exchange with the refrigerant flow path through which the cooling refrigerant flows, which is arranged inside the base material 131 of the 108. It is done. Further, the etching gas and the reaction product generated by the etching are exhausted from the lower part of the processing chamber 104 and the vacuum exhaust port 110 communicated with the vacuum pump inlet of the vacuum exhaust device, which are arranged at the bottom of the vacuum vessel 101.

When the etching process of the film structure on the upper surface of the predetermined wafer 109 is completed, the supply of high-frequency power from the high-frequency power supply 124 is stopped, the supply of power for adsorption from the DC power supply 126 is stopped, and the static electricity is removed. After the wafer 109 is lifted above the sample table 108 and handed over to the arm of the transfer robot that has entered the processing chamber 104 through the gate opened by the gate valve, the unprocessed wafer 109 is again above the sample table 108. Will be carried in. After that, the unprocessed wafer 109 is placed on the sample table 108, and the processing of the wafer 109 is started. When there is no unprocessed wafer 109 to be processed, the operation for wafer processing of the plasma processing apparatus 100 is completed, and a rest / stop or maintenance operation is performed.

Further, a heater (not shown) is arranged inside the base material 131 having a cylindrical shape of the sample table 108 or a disk or a circular dielectric film, and is placed on the sample table 108 or above the upper surface of the dielectric film. The wafer 109 may be configured to be able to be heated to a temperature suitable for processing. Further, in order to reduce or suppress an increase in the temperature of the wafer 109 heated by the heater or by being exposed to the plasma 116 during processing, the temperature inside the base material 131 is determined by a temperature control device (not shown). A heat transfer medium (refrigerant) having a value within the range of the above values flows, and a refrigerant flow path arranged concentrically or spirally around the center of the base material 131 is arranged.

Inside the base material 131 of the sample table 108, a temperature sensor (not shown) or a wafer 109 for detecting the temperature of the base material 131 or the sample table is separated above the dielectric film for adjusting the temperature. Alternatively, a plurality of pins to be lowered to mount the wafer on the upper surface of the film, their position sensors, connectors on the power supply path to the conductor film 111 and the base material 131, etc. are arranged, and these malfunction in an environment with a lot of electrical noise. There is a risk of doing. In addition, the refrigerant may also be charged with static electricity in an environment of electrical noise. In this embodiment, the substrate 131 is electrically connected to ground 112 as shown.

Inside the susceptor 113 of this embodiment, a metal conductor ring 132 arranged so as to surround the wafer mounting surface of the dielectric film on the upper surface of the wafer 109 or the base material 131 is arranged, and the high frequency power supply 127 and the matching unit 128 are arranged. It is electrically connected via the load impedance variable box 130. High-frequency power of a predetermined frequency generated from the high-frequency power supply 127 is introduced into the conductor ring 132, and a potential is formed above the upper surface of the conductor ring 132 with the plasma 116. In the example of FIG. 1, the high-frequency power supply 127 and the conductor ring 132 are formed. The power supply path between the two is arranged at a place different from the power supply path between the high frequency power supply 124 and the conductor film 111 in the dielectric film. Instead of such a configuration, as shown in FIG. 2, the matching device 129 and the conductor are connected on a power feeding path that electrically connects the conductor film 111 and the high frequency power supply 124 via the matching device 129. A configuration for introducing high-frequency power 130 into the conductor ring 132 by arranging a power supply path that branches from the film 111 and electrically connects to the conductor ring 131 via the load impedance variable box 130. You may prepare.

FIG. 2 is a vertical cross-sectional view schematically showing an outline of the configuration of a modified example of the plasma processing apparatus according to the embodiment shown in FIG. In the modified example of this figure, the configuration of the high-frequency power feeding path for the conductor ring 132 is a structural difference from the embodiment of FIG. 1, and the other configurations are the same. Is omitted.

In the examples shown in FIGS. 1 and 2, the magnitude of the impedance from the high-frequency power supply 127 to the outer peripheral portion of the wafer 109 is large due to the combination of the load impedance variable box 130 and the high impedance portion arranged on the upper part of the dielectric susceptor 113. By lowering the impedance, it is possible to apply a high frequency to the region on the outer peripheral side of the wafer 109 to attract charged particles such as ions in the plasma 116 toward the outer peripheral side of the wafer 109. As a result, the concentration of the electric field at the outer peripheral edge portion of the wafer 109 is suppressed. The frequency of the high frequency power supply 127 is preferably the same as that of the high frequency power supply 124 or a constant multiple.

The configuration of the load impedance variable box 130 will be described with reference to FIG. FIG. 3 is an enlarged vertical cross-sectional view schematically showing the configuration of the outer peripheral side portion of the sample table according to the embodiment shown in FIG. In this figure, the configuration of the load impedance variable box 130 arranged on the feeding path connected to the conductor ring 132 arranged in the susceptor 113 is shown.

With the plasma 116 formed, a capacitive sheath portion exists between the conductor ring 132 inside the susceptor 113 and the wafer 108. In considering a high-frequency power circuit including the conductor ring 132, the capacitance between the conductor ring 132 and the outer peripheral edge of the wafer 108 is conveniently represented by a capacitor 300.

In this embodiment, by adjusting the inductance of the variable coil 133 arranged inside the load impedance variable box 130 to an appropriate value, series resonance is generated on the equivalent circuit including the capacitor 300, which is a capacitive component. Reduce the impedance on the equivalent circuit. With this configuration, it is possible to efficiently supply the high frequency power from the high frequency power supply 127 to the wafer 109 to form a bias potential.

Further, in the load impedance variable box 130, a variable resistor 135 is further arranged between the variable coil 133 and the high frequency power supply 127, and the resistance value of the variable resistor 135 is adjusted to alleviate the peak value of the series resonance. Since the Q value can be lowered, the controllability can be improved. That is, as shown in FIG. 19, the control robustness can be improved.

FIG. 15 is a graph schematically showing the result obtained by increasing or decreasing the resistance value of the variable resistor in the load impedance variable box 130 shown in FIG. Further, since the capacity of the capacitor 300 changes due to the consumption of the susceptor due to plasma over time, in order to compensate for this, a variable capacitor 134 whose capacity can be changed is placed in the load impedance variable box 130 with a variable resistor 135 and a high frequency. It may be arranged between the power supply 127 and the power supply 127.

Further, a voltage monitor 136, which is a sensor for detecting the voltage of a voltmeter or the like electrically connected to the power supply path in the load impedance variable box 130, is arranged and the detected voltage is used to pass the plasma 116 from the high frequency power supply 127. It is possible to detect fluctuations in the load on the circuit of high-frequency power. Alternatively, from the result of detecting the matching constant (for example, the capacitance value of the variable coil) inside the matching device 128 or the result of detecting the voltage value using the voltage monitor 138, the change in the load from the initial use of the susceptor 113 can be determined. It can be detected indirectly. This makes it possible to estimate the amount of consumption of the susceptor 113 from the initial stage.

Further, the load impedance variable box 130 shown in FIG. 3 may be arranged on the power feeding path branched and connected to the conductor ring 132 shown in FIG. In this case, the impedance seen from the high-frequency power supply 124 of the feeding path for supplying high-frequency power to the conductor film 111 looks relatively low from the case of FIG. 3 because the feeding path to the conductor ring 132 is connected in parallel. The high frequency voltage formed on the conductor film 111 may decrease, and the processing speed (rate) of the wafer 109 may decrease.

In order to prevent this, a voltage monitor 137 is placed inside the load matcher 129 so that the detected voltage value becomes the target value that can realize the characteristics such as the desired processing rate, or the impedance of the load matcher 129. The matching constant may be adjusted. Further, as shown in FIG. 4, in order to synchronously generate the power signals generated by the high frequency power supplies 124 and 127, these and the clock generator 220 are electrically connected, and the clock generator 220 periodically pulses or squares. By outputting a signal such as a wave to these power supplies, the cycle of the electric power oscillated by each of them is synchronized and output, and the beat signal generated by interfering with the wafer 106 is suppressed.

In the above embodiment, the conductor 111 in the dielectric film is provided with the high frequency power from the high frequency power supply 124 and the DC power from the DC power supply 126, but is arranged on the upper surface of the base material 131. Each of the different conductor films arranged at different locations inside the dielectric film may be provided with power supplied from each of these power sources. For example, a film made of a conductor to which DC power for electrostatic adsorption is supplied is arranged above the dielectric film formed by spraying particles of a dielectric material, and high-frequency power is generated below the inside of the dielectric film. It may be configured such that a film made of another conductor to which is supplied is arranged. Even in such a configuration, the clock generator 220 shown in FIG. 4 may be provided and a configuration for transmitting a signal for synchronizing the outputs to the two high-frequency power supplies 124 and 127 may be provided.

Next, the configuration of the susceptor 113 of the above embodiment will be described with reference to FIGS. 5 to 7. FIG. 5 is an enlarged vertical sectional view schematically showing the configuration of the upper part of the susceptor of the embodiment shown in FIG. FIG. 6 is a vertical cross-sectional view schematically showing the operation of the embodiment shown in FIG. FIG. 7 is a vertical cross-sectional view schematically showing the configuration of the upper part of the susceptor of the modified example of the embodiment shown in FIG.

In FIG. 5, the susceptor 113 of the present embodiment is composed of a plurality of members arranged vertically, and the upper susceptor 151 arranged above is a ring-shaped member made of a dielectric material, and is an upper portion of the base material 131. The ring-shaped lower susceptor 150 placed above the recessed portion arranged in a ring shape on the outer peripheral side portion and the conductor ring 132 placed on the upper surface of the lower susceptor 150 are placed so as to cover the lower susceptor 150. In this embodiment, the high-frequency bias potential generated by the high-frequency power supplied from the second high-frequency power source 127 to the conductor ring 132 is efficiently formed above the upper surface of the upper susceptor 151 through the inside of the upper susceptor 151 by such a configuration. Can be generated.

By such an ion sheath 160, it is suppressed that a sheath having a peculiar shape is formed due to the electric field concentration generated on the outer peripheral edge of the wafer 106, which is generated in the conventional technique, and the equipotential surface formed in the sheath 160 is formed. The portion of the outer peripheral side portion of the wafer 106 that is not parallel to the upper surface of the wafer 106 is reduced. As a result, the range in which the angle at which the ions are incident on the wafer 106 is a desired angle, for example, a vertical angle is expanded to the outer peripheral edge, and the processing characteristics of the wafer 106, for example, the etching rate is set with respect to the in-plane direction of the wafer 106. Variation can be reduced.

Further, the upper susceptor 151 needs to have a sufficient thickness so that high frequency power is not applied to the lower susceptor 150 side. In this embodiment, the thickness of the upper susceptor 151 on the conductor ring is set to a value within the range of 1 to 3 mm, and the thickness of the lower susceptor 150 below the conductor ring 132 is set to a value within the range of 3 to 10 mm. The magnitude relationship of such thickness is such that the distance between the conductor ring 132 and the plasma sheath 160 via the upper susceptor 151 is smaller than the distance between the conductor ring 132 and the base material 131 in the lower susceptor 150. It is desirable to be configured.

The principle of operation of the configuration shown in FIG. 5 will be described with reference to FIG. FIG. 16 is a vertical cross-sectional view schematically showing the action exerted by the configuration of the embodiment shown in FIG.

In FIG. 16A, the configuration of the upper part of the susceptor 113 of this embodiment is enlarged and schematically shown as a vertical cross section. In the equivalent circuit in the configuration of this figure, as the path through which the high-frequency power supplied from the second high-frequency power supply 127 to the conductor ring 132 flows, the path 1 and the path 2 are as shown by arrows in FIG. 16 (a). Conceivable. FIG. 16B schematically shows the relationship between VLc, which is the voltage of the variable coil 133 in the embodiment shown in FIG. 5, and the voltage value V1 detected from the output of the voltage monitor 136. In this figure, the correlation is shown for each of Route 1 and Route 2.

It is preferable that the electric power transmitted to the path 2 is small in order to improve the efficiency of the electric power supplied to the wafer 106 for attracting ions in the plasma. For this purpose, in this embodiment, the difference VL12 between the VLc value of the resonance point on the path 2 and the resonance point value on the path 1 is made larger than the VLc value VL11 of the resonance point on the path 1.

This makes it possible to make the ratio of the electric power supplied to the path 2 in the control unit of the path 1 substantially negligible. In this embodiment, in order to realize the condition of VL12> VL11, the capacitance C1 of the upper susceptor 151 in the path 1 is sufficiently increased on the equivalent circuit, while the capacitance of the lower susceptor 150 in the path 2 is sufficiently increased. Dimensions such as the thickness and width of the material and its shape are selected so as to sufficiently reduce the capacitance C2. In this state, the desired sheath 160 thickness and region are within a predetermined allowable range in the region where V1 of the path 1 in FIG. 16B is monotonically increased with respect to the change in VLc. As described above, the control device 180 described later adjusts VLc according to the detected value of C1.

Further, a gap 155 is arranged between the lower susceptor 150 and the upper susceptor 151 so that energy is transferred between the sheath 160 and the metal conductor ring 132. However, when the end of the gap 155 is communicated with the processing chamber 104 facing the processing chamber 104, highly reactive particles such as charged particles and active species in the plasma 116 formed in the processing chamber 104 are formed. May enter the gap 155 and interact with the wall surface of the member constituting the gap 115.

To solve such a problem, as in the modified example shown in FIG. 6A, the insulator ring 153 made of ceramics such as quartz, alumina, or yttria instead of the metal conductor ring 132 shown in FIG. A metal conductor film 153'may be arranged inside the. According to this configuration, the contact of the metal conductor ring 132 with the plasma 116 is reduced, and the wafer 106 is suppressed from being contaminated by the product generated by the interaction between the two. The impedance to the lower susceptor 150 side can be made relatively high, energy can be efficiently transferred to the upper susceptor 151 side, and the gap 155 is surrounded by a member made of an insulator or a dielectric. Therefore, the interaction between the conductor ring 132 and the plasma 116 suppresses the occurrence of metal contamination of the wafer 106.

Furthermore, in order to enhance the controllability of the thickness and distribution of the sheath 160 or the characteristics of the processing obtained with respect to the supplied electric power, the lower surface of the upper susceptor 150 and the conductor film are arranged inside as shown in FIG. 6 (b). A gap 210 may be arranged between the insulator ring 153 and the upper surface. In this example, the insulator ring has a configuration in which the upper side wall surface on the inner peripheral side, the side wall surface on the outer peripheral side, and the upper surface of the insulator ring 153 are covered with the upper susceptor 151 mounted on the lower susceptor 150. The 153 is suppressed from facing the plasma, and the metal film can be shielded from the plasma. In this example, the gap of the space 210 is selected and set from the range of 0.01 to 1 mm.

Next, the mode of controlling the electric power supplied to the conductor ring 132 of the plasma processing apparatus of this embodiment and its action / effect will be described with reference to FIGS. 7 to 12. FIG. 7 is a vertical cross-sectional view schematically showing the action performed in the vicinity of the outer peripheral edge of the wafer including the susceptor of the modified example shown in FIG.

FIG. 7A is an enlarged and schematically shown vertical section of the wafer 106 including the prior art susceptor 113 having the upper susceptor 153 and the lower susceptor 150 in which the conductor ring 132 is not arranged inside. It is a top view. As shown in this figure, in this prior art, the sheath 160 above the upper surface of the upper susceptor 151 on the outer periphery of the wafer 106 is above the inclined surface forming the upper surface of the wafer 116 and the inner peripheral side portion of the ring shape of the upper susceptor 151. The wafer 106 is limited to the outer peripheral edge including the lower surface of the overhang portion protruding from the dielectric film on the upper surface of the convex portion in the upper center portion of the base material 131 to the outer peripheral side, and the ions formed in the plasma 116 are formed. It can be seen that the outer peripheral edge of the wafer 106 collides with the wafer 106 along the orbit 161 inclined from the outer peripheral side toward the center side and concentrates on the portion.

FIG. 7B shows a predetermined number of conductor films included in the insulating ring 153 shown in FIG. 6B via a resonance circuit arranged in the load impedance variable box 130 from the second high-frequency bias power supply 127. It is a vertical cross-sectional view which shows typically the structure of the sheath 160 which occurs in the modification which high frequency power of a frequency is supplied. As shown in this figure, in this example, an AC voltage submerged in a negative potential is generated above the conductor film on the upper surface of the upper susceptor 151, and the potential difference from the positive potential plasma becomes large and has a thickness equal to or greater than a predetermined value. The sheath 160 is formed. As a result, in the example of FIG. 7A, the concentration of the electric field generated on the outer peripheral edge of the wafer 106 or the descent accompanying the sheath 160 toward the outer peripheral side of the equipotential surface is alleviated, and the upper edge of the outer peripheral edge of the wafer 106 is relaxed. Charged particles such as ions are drawn from above along the orbit 161 in the direction toward the upper surface of the upper susceptor 151 outside the wafer 106, and the processing characteristics such as the etching rate are between the central portion and the outer peripheral edge of the wafer 106. Fluctuation is suppressed.

FIG. 7 (c) shows, as compared with FIG. 7 (b), via a resonant circuit including a variable coil 200 without a second high frequency power supply 127 that supplies high frequency power to the conductor film inside the insulator ring 153. It is a vertical cross-sectional view which shows typically the structure of the sheath 160 which occurs in the thing which is grounded. In this configuration, the potential on the upper surface of the upper susceptor 151 is set to the ground potential and the potential difference from the potential of the plasma 116 becomes smaller, so that the sheath 160 on the upper surface of the upper susceptor 113 is more difficult to form than that shown in FIG. 7A. The sheath 160 grows only around the upper surface of the wafer 106 and the outer peripheral edge including the overhang portion. Therefore, in the configuration of this example, charged particles such as ions in the plasma 116 are more likely to be concentrated on the outer peripheral edge portion of the wafer 106, and the processing characteristics of the wafer 106 near the outer peripheral edge portion are further improved from those in the central portion. The gap will be large.

In each of the configurations shown in FIG. 7, an example of the characteristics of such processing, particularly the etching rate, is shown in FIG. FIG. 8 is a graph schematically showing a distribution example of the etching rate in the radial direction of the upper surface of the wafer 106 in the example shown in FIG. 5 and the prior art.

As shown in FIG. 8 (a), the etching rate in the examples of FIGS. 7 (a) and 7 (c) increases in the outer peripheral side portion with respect to the central side portion which is made substantially constant. On the other hand, in the example of FIG. 7B, the thickness of the sheath 160 formed above the upper surface of the upper susceptor 151 depending on the voltage value VLc of the variable coil 133 and the magnitude and frequency value of the output from the second high frequency power supply 127. The height of the pod equipotential surface can be adjusted. In this embodiment in which such adjustment is performed, the etching rate in the outer peripheral side portion of the wafer 106 is as shown in the distribution increasing in the outer peripheral side region as shown in FIG. 8 (a) and in FIG. 8 (b). It is formed to the desired one with the decreasing one.

Further, in the above embodiment, as shown in FIG. 9, the conductor film shown in FIG. 7B is passed through a variable RLC circuit including the variable coil 133 by the switch 201 arranged inside the load impedance variable box 130. The wafer edge variable release that is switched between the feeding path connected to the second high frequency power supply 127 and the path in which the conductor film shown in FIG. 7C is grounded via the variable coil 200, and functions by each. A configuration that can be switched between the mode and the wafer edge access mode may be provided.

FIG. 10 will explain the result of processing the wafer 106 using the embodiment having the configuration shown in FIG. 5 or 6. FIG. 10 is a graph showing the result of detecting the distribution of the etching rate in the radial direction of the wafer processed by the plasma processing apparatus according to the embodiment shown in FIG. 5 or 6.

In this example, the results of detection are shown for a plurality of cases in which the magnitudes of the high-frequency power for bias formation are different with VLc = 53 μH. The one on the left side of each of the graphs shown in FIGS. 10A to 10C is a graph showing the distribution of the etching rate from the center to the outer periphery of the wafer 106 having a diameter of 300 mm, and the one on the right side is on the drawing. It is a graph which enlarged and shows the size distribution of the etching rate in the vicinity of the outer peripheral edge of the right end.

In FIG. 10A, high-frequency power of 200 W is supplied from the first high-frequency power source 124 to the conductor film 111 in the dielectric film arranged on the upper surface of the convex portion of the base material 131, and further, the outer peripheral side of the conductor film 111. It shows the case where 0W high-frequency power is supplied to the conductor ring 132 in the susceptor 113 or the conductor film in the insulator ring 153 arranged in. 10 (b) shows that when 200 W of high frequency power is supplied to the conductor film 111 and 20 W of high frequency power is supplied to the conductor ring 132 or the conductor film in the susceptor 113, 200 W and 50 W are supplied in FIG. 10 (c), respectively. The result of detecting the characteristic during processing when it is done is shown.

As shown in these figures, the magnitude of the high frequency power supplied to the conductor ring 132 or the conductor film inside the insulator ring 153 is adjusted via the load impedance variable box 130 including the variable coil 133 of this embodiment. As a result, the etching rate in the region of about 10 mm from the outer peripheral edge of the wafer 106 is increased or decreased while suppressing the influence on the rate of the central portion.

Further, the inventors have detected the distribution of the etching rate in a plurality of cases in which the voltage value VLc of the variable coil 133 is different while the magnitude of the high frequency power for bias formation is constant. In these cases as well, it was shown that the distribution of the etching rate on the outer peripheral side portion of the wafer 106 can be adjusted independently of that on the central portion side, similar to that shown in FIG. Further, it was found that, as a processing characteristic, in addition to the etching rate, the etching shape, particularly the angle in the shape of the film structure after processing, can be realized as desired by adjusting the high frequency power or the load impedance in the above embodiment. ..

Next, in the above embodiment, the high frequency power supply supplied from the second high frequency power supply 127 to the susceptor 113 is adjusted with respect to the amount of consumption of the susceptor 113 as the processing time or the number of wafers 106 increases. Will be described with reference to FIGS. 11 and 12.

The upper surface and the outer peripheral side surface of the upper susceptor 151 face the plasma 116, and are members that are scraped or altered by interaction with the plasma 116 and are consumed. Therefore, the shape of the sheath 160 changes due to such wear, and the distribution of processing characteristics changes.

For example, when the portion above the conductor ring 132 or the insulator ring 153, which is a dielectric, is consumed and the thickness is reduced, the value Cv of the capacitance 170 with respect to the high frequency power of this portion increases, and the upper susceptor The potential on the top surface of 151 increases. Therefore, when high-frequency power of the same value as before is supplied to the conductor film in the conductor ring 132 or the insulator ring 153 in a state of being consumed, there arises a problem that the same processing characteristics are not realized.

In order to solve such a problem, in this embodiment, a predetermined portion of the wafer 106 that serves as a reference for a change in the Cv value in advance before starting processing of the wafer 106 for a product to be processed for manufacturing a semiconductor device. Information indicating the correlation with the characteristics of the processing averaged in or in the in-plane direction, for example, the value of the etching rate was detected, and this data was arranged as a target or standard data in a control device (not shown as a table or database). It is stored in a storage device such as a hard disk, RAM, or a removable disk. FIG. 11 is a vertical cross-sectional view schematically showing the outline of the configuration of the susceptor of the plasma processing apparatus according to the embodiment shown in FIG. 1 and a graph schematically showing an example of a data table used by the plasma processing apparatus. is there.

The wafer 106 for obtaining the reference data has a film structure arranged on the upper surface having a structure that is similar to or similar to that for the product, and has different thicknesses. In the specifications of a plurality of devices using the susceptor 151, the value of the voltage VLc of the variable coil 133 is changed to be carried out in advance before the start of processing of the wafer 106 for the product. From the relative relationship between the value of the treatment characteristics such as the etching rate obtained during or after the treatment under each of these conditions, the distribution thereof, the distribution of the processing shape, and the VLc value, the value of the characteristics of the target processing and its distribution Data showing the correspondence between the capacitance Cv of the upper susceptor 153 and the value of VLc, which can obtain the distribution of the etching shape and the processed shape, is extracted as a table. A plurality of reference wafers 106 to be processed for extracting such target data may be used.

In this embodiment, the control device 180 calculates the value Pf of the output from VLc or the second high-frequency power supply based on the information of this data table stored as a database, and sets a command signal as a value to be set in these values. Send. The control device 180 is communicably connected to elements and devices such as a variable coil 133, a variable capacitor 134, and a variable resistor 135 arranged in the load impedance variable box 130 or the variable load impedance box 130, and further, a second high frequency power supply 127 and a matching unit. 128, It is communicably connected to the voltage monitors 136 and 138, and the signal is communicated by being electrically connected to the interface of the signal to be communicated, the storage device such as RAM and hard disk, the arithmetic unit such as the capacitor made of semiconductor, and these. It has a communication path to be used. The storage device does not have to be housed inside the unit of the control device 180, and may be arranged at a remote location and connected so as to be able to communicate.

Specifically, the control device 180 is a high-frequency power source for forming a bias potential from the second high-frequency power source 127 to the upper surface of the upper susceptor 151 before the start of the predetermined period during which the plasma processing device of the present embodiment is operated. The initial load of the power supply path to which the power supply is supplied and the impedance value Zs are detected and stored in the storage device constituting the control device 180. Further, by detecting the load Zp of the power feeding path detected before or during the processing of an arbitrary number of wafers 106 and comparing this with the Zs stored in the storage device, the conductor ring on the feeding path Capacitance Cv between 132 or the conductor film and the upper surface of the upper susceptor 151 or between the plasma 116 via the upper susceptor 151 is detected.

Specifically, the arithmetic unit of the control device detects the amount of the upper susceptor 151 consumed and reduced in thickness from Zs-Zp according to the software algorithm stored and stored in the storage device in advance. , The current Cv is calculated using this. The target VLc value is calculated using this Cv and the data table stored in the storage device. Further, a command for setting the inductance of the VLc so as to be the calculated target value is transmitted to the variable coil 133 or the element in the load impedance variable box 130.

In the example of FIG. 11, a data table showing the corresponding relationship between the capacitance value Cv on the equivalent circuit of the feeding path via the upper susceptor 153 and the voltage value VLc of the variable coil 133 of the load impedance variable box 130 is used. However, as shown in FIG. 12, the output value V1 from the voltage monitor 136 arranged connected to the feeding path between the load impedance variable box 130 and the conductor ring 132 or the conductor film in the insulator ring 153. Data showing the relationship with the capacitance Cv may be used. FIG. 12 is a graph schematically showing another example of the data table used by the plasma processing apparatus according to the embodiment shown in FIG.

In this example, when Cv changes, the voltage value V1 that indirectly affects the processing characteristics such as the etching rate changes. Therefore, as in the example described with reference to FIG. 11, prior to the start of processing of the wafer 106 for a product to be processed for manufacturing a semiconductor device, the wafer 106 may be at a predetermined position as a reference for a change in the Cv value. A control device (not shown as a table or database) that detects data that correlates with the in-plane averaged processing characteristics, such as the V1 value corresponding to the target value of the etching rate, and uses this data as target or standard data. It is stored in a storage device such as a hard disk, RAM, or a removable disk arranged inside.

Such data detection is performed prior to the start of processing of the product wafer 106 in the specifications of the plurality of devices using the upper susceptors 151 of different thicknesses before the start of processing of the product wafer 106. To. From the relative relationship between the value of the treatment characteristics such as the etching rate obtained during or after the treatment under each of these conditions and the distribution or processing shape distribution and the detected V1 value, the target processing characteristic value. Data showing the correspondence between the capacitance Cv of the upper susceptor 153 and the value of V1 from which the distribution of the etching and the processing shape can be obtained is extracted as a table and stored as the data of the database.

The control device 180 receives the output from the voltage monitor 136 and sets the voltage value of the variable coil 133 in the load impedance variable box 130 so as to have a predetermined V1 value capable of realizing the desired processing characteristics and processing shape. A command signal is transmitted to the load impedance variable box 130 so as to change the VLc. The control device 180 may adjust the value of V1 to be constant in the processing of the product wafer 106, and as in the example of FIG. 11, the initial stage before or immediately after the start of the processing. The load and impedance values Zs of the above are compared with the load Zp of the feeding path detected before or during the processing of an arbitrary number of wafers 106, and the conductor on the feeding path is obtained from the obtained Zs-Zp value. Capacitive Cv between the ring 132 or the conductor film and the upper surface of the upper susceptor 151 or between the plasma 116 via the upper susceptor 151 is detected, and the above data table is used to detect the capacitance Cv of V1 corresponding to the value of this Cv. The load impedance variable box 130 may be subjected to feedback control so as to calculate a value and obtain this value.

Further, when the value Pf of the magnitude of the high frequency power from the second high frequency power source changes, V1 also fluctuates, but even when such an increase or decrease of V1 occurs, the load impedance variable box 130 and The VLc so that the ratio V1 / V2 of the voltage value V2 and V1 detected from the output of the voltage monitor 138 arranged connected to the power supply path between the matching unit 128 is within the allowable range of the predetermined value. By adjusting the value, the desired processing characteristics and processing shape can be realized. Further, the value of the ratio V1 / V3 of the voltage values V3 and V1 detected from the output of the voltage monitor 137 connected to the power supply path between the conductor film 111 and the first high frequency power supply 124 is set to the wafer. The ratio of the etching rate on the central side portion of the upper surface of 106 to the etching rate on the outer peripheral side portion may be adjusted so as to be a value within a predetermined allowable range.

Furthermore, the value A of the high-frequency power current flowing in the feeding path between the load impedance variable box 130 and the conductor ring 132 or the conductor film in the insulator ring 153 is detected, and the voltage inside the matching unit 129 is detected. Then, the voltage value VLc of the variable coil 133 of the load impedance variable box 130 can be adjusted so that the product of these is constant or a value within a predetermined allowable range. However, in this embodiment, the output value Pf from the second high-frequency power supply 127 is adjusted to a value within a predetermined allowable range, and the impedance is matched in the matching unit 129 in response to a change in the load. By adjusting the product of the current value A and the voltage value of the matching device 129 to be constant, the conductor ring 132 via the upper susceptor 151 or the capacitance value Cv between the conductor film and the plasma is provided. It is the power of the local part that greatly affects the processing characteristics such as the etching rate and the processed shape.

Further, since the thickness of the sheath 160 at the outer peripheral edge of the wafer 106 increases or decreases due to the synergistic effect of V3 and V1, the etching rate of the outer peripheral edge of the wafer 106 can be adjusted by using this. That is, the relationship between the amount to be corrected for the etching rate (the difference between the detected etching rate at an arbitrary time during processing and the target etching rate) and the amount of change in the voltage value V1 is expressed by the following equation (1). ), It was found by the examination of the inventors.

ΔER = K × (V3 × ΔV1) × Ks + B (1)
Here, ΔER = the difference between the etching rate at an arbitrary time during processing and the target etching rate, K = proportionality constant, and KS = proportionality constant indicating the magnitude of the influence of V3 on the thickness of the sheath 160. B = constant, ΔV1 = control amount for realizing the desired etching rate. It is generally known that the constant power of voltage contributes to the thickness of the sheath 160, and this constant power is expressed as Ks.

According to the inventors, as a result of the examination, it was found that the constant power of (V3 × V1) is proportional to the correction amount of the etching rate in the correction of the etching rate of the outer peripheral edge side portion of the wafer 106. From this, in order to obtain the correction amount of the desired etching rate, the change amount of V1 required by the control device 180 is obtained by using the equation (1), and the change amount of V1 can be realized by the VLc or the high frequency power supply 127. By controlling these so as to be Pf, it is possible to bring the etching rate value and its distribution closer to the target one, or to reduce the deviation from the future.

Next, the user interface displayed when the user uses the plasma processing apparatus of this embodiment will be described with reference to FIG. FIG. 13 is a diagram showing an example of a screen displayed by a display provided in the plasma processing apparatus according to the embodiment shown in FIG.

Using the user interface with such a display, the user of the above embodiment switches the rate mode of the outer peripheral side portion between automatic control and manual control, and in the auto mode, the rate of the outer peripheral side portion of the wafer 106 is set to the center side portion. Choose whether to lower, increase, or equalize the rate. Further, by setting the rate ratio and setting the consumption limit of the susceptor 113, the susceptor replacement alarm is automatically displayed when the consumption limit is reached.

Further, in the manual mode, the inductance value (voltage value) VLc of the variable coil 133 is directly set after selecting whether to raise, lower, or equalize the rate in the region on the outer peripheral side of the wafer to the rate in the region on the center side. Set to, and the VLc is directly adjusted to be constant. Further, in this embodiment, the value of Cv indicating the amount of consumption and the potential Vpp of the conductor ring 132 inside the susceptor 113 can be displayed on the monitor in both the auto mode and the manual mode.

Next, another modification of the above embodiment will be described with reference to FIG. FIG. 14 is a vertical cross-sectional view schematically showing an outline of the configuration of another modified example in the vicinity of the susceptor of the plasma processing apparatus according to the embodiment shown in FIG.

In this example, it is aligned with the conductor ring 132 or conductor film and the load impedance variable box 130 on the feeding path between the second high frequency power supply and the conductor ring 132 or the conductor film in the insulator ring 153. It has a portion connected to a power supply path to which high-frequency power from a third high-frequency power source 333 is supplied via a device 332. This connection is located between the voltage monitor 136; the connection and the load impedance variable box 130.

In this modification, the high frequency power of the third high frequency power supply 333 is 10 times or more higher than that of the first or second high frequency power supply, and the power can generate plasma in the processing chamber 104. It has. That is, according to such a configuration, the impedance due to the value Cv of the capacitance 170 is relatively small, so that the plasma 116 formed by using the electric field or the magnetic field supplied from above the processing chamber 104 Separately, a second plasma 331 is generated on the outer peripheral side portion of the wafer 106 and above the upper susceptor 151.

At this time, the voltage value VLc133 of the variable coil 133 can cut off the high-frequency power supplied from the third high-frequency power supply 333 so that it does not flow to the matching unit 129 and the second high-frequency power supply 127. It has an inductance value.

The second plasma 331 is a plasma generated in the processing chamber 104 above the wafer 106 from above the central portion to the vicinity of the outer peripheral edge and above the upper susceptor 151 on the outer peripheral side thereof, and its intensity and strength. The density value and its distribution are adjusted by any of the configurations of the above examples or a combination thereof. With this configuration, the plasma processing apparatus of this example covers a wide range from the central portion to the outer peripheral side portion of the upper surface of the wafer 106, and the values of the processing characteristics such as the etching rate, their distribution, and the dimensions of the processed shape obtained after the processing. It is possible to keep the variation within the expected range.

Further, in place of the conductor film 111 to which power is supplied from the first high-frequency power source 124 in the above embodiment, a conductor film divided into a plurality of regions in the in-plane direction is provided, and the region on the center side is provided. A power supply path is electrically connected to the arranged conductor film, and high-frequency power from the first high-frequency power source 124 is supplied through the electric power supply path. A configuration may be provided in which high-frequency power for forming the plasma is supplied from the third high-frequency power source 333 through a power supply path electrically connected to the ring-shaped conductor film on the outer peripheral side arranged in the region. .. Even with such a configuration, the second plasma 331 is formed above the outer peripheral side portion of the upper surface of the wafer 106, and the high frequency power supplied to the ring-shaped conductor film is adjusted to obtain the second plasma. The strength and density values and their distribution can be adjusted to the desired values, and the processing yield can be improved by reducing variations in the dimensions of the processed shape of the wafer 106 and the processing characteristic values or their distribution. ..

In this embodiment, the material to be etched is a silicon oxide film, and for example, the above-mentioned tetrafluoride methane gas, oxygen gas, and trifluoromethane gas are used as the etching gas and the cleaning gas, but only the silicon oxide film is used as the material to be etched. Not polysilicon film, photoresist film, antireflection organic film, antireflection inorganic film, organic material, inorganic material, silicon oxide film, silicon nitride oxide film, silicon nitride film, Low-k material, High-k The same effect can be obtained with materials, amorphous carbon films, Si substrates, metal materials, and the like.

Examples of the gas to be etched include chlorine gas, hydrogen bromide gas, methane tetrafluoride gas, methane trifluoride, methane difluoride, argon gas, helium gas, oxygen gas, nitrogen gas, and carbon dioxide. , Carbon monoxide, hydrogen, ammonia, propane octafluoride, nitrogen trifluoride, sulfur hexafluoride gas, methane gas, silicon tetrafluoride gas, silicon tetrachloride gas, chlorine gas, hydrogen bromide gas, methane gas tetrafluoride , Methane trifluoride, methane difluoride, argon gas, helium gas, oxygen gas, nitrogen gas, carbon dioxide, carbon monoxide, hydrogen, ammonia, propane octafluoride, nitrogen trifluoride, sulfur hexafluoride gas, Methane gas, silicon tetrafluoride gas, silicon tetrachloride gas, helium gas, neon gas, krypton gas, xenon gas, radon gas and the like can be used.

In the above example, an example of a plasma processing device that performs etching processing using microwave ECR discharge has been described, but other discharges (magnetic field UHF discharge, capacitance coupling type discharge, induction coupling type discharge, magnetron discharge, surface) have been described. A similar effect can be obtained by applying the above configuration to a plasma processing device using (wave excitation discharge, transfer coupled discharge), for example, a plasma CVD device, an ashing device, a surface modification device, or the like.

101 ... Vacuum container 102 ... Shower plate 103 ... Insulator window 104 ... Processing room 105 ... Waveguide tube 106 ... Power supply for electric field generation 107 ... Magnetic field generation coil 108 ... Sample stand 109 ... Wafer 110 ... Vacuum exhaust port 111 ... Conductive film 112 ... Grounding 113 ... Suceptor 116 ... Plasma 124 ... High frequency power supply 125 ... High frequency filter 126 ... DC power supply 127 ... High frequency power supply 128 ... Matching device 129 ... Matching device 130 ... Load impedance variable box 131 ... Base material 132 ... Conductor ring 133 ... Variable Coil 134 ... Variable capacitor 135 ... Variable resistance 136 ... Voltage monitor 137 ... Voltage monitor 150 ... Insulator 151 ... Upper susceptor 152 ... Wafer 153 ... Insulator ring 155 ... Sheath access space 160 ... Ion sheath 161 ... Orbit 170 ... Capacitance 200 ... Variable coil 210 ... Gap 220 ... Clock generator 331 ... Second plasma 332 ... Matcher 333 ... High-voltage power supply.

Claims (6)

A plasma processing device that processes a wafer to be processed placed on a mounting surface located above a sample table placed in a processing chamber inside a vacuum vessel using plasma formed in the processing chamber. ,
A ring-shaped member arranged on the upper part of the sample table and arranged on the outer peripheral side of the previously described mounting surface on which the wafer is mounted, and a ring-shaped member made of a dielectric material arranged around the mounting surface. , The first electrode arranged inside the sample table below the mounting surface, which is electrically connected to the first high-frequency power source, for forming a bias potential on the wafer during processing of the wafer. A first electrode to which high-frequency power is supplied, a second electrode arranged inside the ring-shaped member so as to surround the above-mentioned mounting surface in a ring shape, and electrically connected to a second high-frequency power source, and the second electrode. The second electrode and the second high-frequency power source are electrically connected, and during the processing of the wafer, the power from the second high-frequency power source is supplied to the second electrode and arranged on the power supply path. A plasma processing apparatus including a circuit in which capacitors and coils are arranged in series in this order in a direction from the second high-frequency power source toward the second electrode. Item 2. The plasma processing apparatus according to Item 1.
A plasma processing apparatus in which electric power is synchronously output from each of the first and second high-frequency power supplies. Item 2. The plasma processing apparatus according to Item 1 or 2.
A plasma processing device in which the coil is configured so that the inductance can be adjusted, and the inductance is adjusted in advance within a range in which the voltage due to the electric power from the second high-frequency power source on the feeding path monotonically increases or decreases. A plasma processing method for processing a wafer to be processed placed on a sample table surface arranged in a processing chamber inside a vacuum vessel using plasma formed in the processing chamber.
During processing of the wafer, power from the first high-frequency power source is supplied from the high-frequency power source to the first electrode arranged inside the sample table, and the outer periphery of the surface of the sample table on which the wafer is placed is placed. A step of processing the wafer by supplying electric power from a second high-frequency power source to a second electrode arranged inside a ring-shaped member made of a dielectric material arranged on the side is provided.
A plasma processing method in which electric power from the second high-frequency power source is supplied to the second electrode through a circuit in which capacitors and coils are connected in series in this order. Item 4. The plasma processing method according to Item 4.
A plasma processing method in which electric power is synchronously output from each of the first and second high-frequency power supplies. Item 4. The plasma treatment method according to Item 4 or 5.
The coil is configured so that the inductance can be adjusted, and the inductance is adjusted in advance within the range in which the voltage due to the electric power from the second high-frequency power source on the feeding path monotonically increases or decreases to process the wafer. Plasma processing method.

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