JP2021044464A - Nitride semiconductor transistor device - Google Patents

Abstract

To provide a normally-off nitride semiconductor transistor device with excellent performance as a switch.SOLUTION: A nitride semiconductor transistor device includes a substrate 101, an element separation region 114 provided on the substrate, a first nitride semiconductor layer 103 provided on the substrate, a second nitride semiconductor layer 104 provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, a first insulating film 110 provided on the second nitride semiconductor layer, a charge accumulation gate electrode 111 provided on the first insulating film, a second insulating film 112 provided on the charge accumulation gate electrode, a first gate electrode 116 provided on the second insulating film, a source electrode 109 and a drain electrode 210 provided on the second nitride semiconductor layer with the charge accumulation gate electrode held therebetween in a plane direction, a third insulating film 115 provided on the charge accumulation gate electrode, and a second gate electrode 117 provided on the third insulating film.SELECTED DRAWING: Figure 1

Description

The present invention relates to a nitride semiconductor transistor device, and in particular, in a field effect nitride semiconductor transistor, the conductive channel under the gate electrode is substantially turned off without applying a voltage to the gate electrode, so-called. The present invention relates to a nitride semiconductor transistor apparatus that realizes normalization.

Nitride semiconductors such as GaN, AlN, InN, or a semiconductor composed of a mixture of these have a wide bandgap and conduction electrons have high carrier mobility, and are therefore suitable for high-voltage and high-power electronic devices. Is. In particular, high electron transfer using conduction electrons induced in semiconductor heterojunction interfaces such as field-effect transistors (FETs, Field-Effect Transistors) made of nitride semiconductors and AlGaN / GaN, which is a form thereof, as conductive channels. High Electron Mobility Transistors (HEMTs) are capable of high voltage, high current, and low on-resistance operation, and are used as high output power amplifiers and high power switching elements.

However, a normal nitride semiconductor FET is a so-called normalion in which the conductive channel under the gate electrode is turned on without applying a voltage to the gate electrode. As a switching element used in devices such as power supplies, the switch opens when the control voltage applied to the gate electrode is lost due to malfunction or failure, which leads to the destruction of the entire device, which is safe. Not preferable from the viewpoint of sex.

Therefore, some techniques for normalizing the nitride semiconductor FET have been developed. As one of the techniques, a method of realizing a normalization-off operation by inserting a p-type nitride semiconductor layer directly under the gate of the FET to form a pn junction type gate electrode is known (see Non-Patent Document 1). In this technique, the operating range of the gate electrode is limited by the flat band voltage determined by the band gap of the semiconductor. Therefore, when the threshold value is a positive voltage, the value stays at 2 V or less, and a positive threshold value of 3 V or more is desired in a normal power supply device, whereas a sufficient threshold value cannot be obtained. Further, since the positive voltage that can be applied to the gate voltage is limited by the on-voltage of the pn junction, the operating voltage amplitude of the gate becomes small, and the current that can be passed through the conductive channel while the FET is on is limited.

As another method for realizing normalization, a method is known in which an insulating film is inserted directly under the gate of the FET to form a metal / insulator / semiconductor (MIS, Metal-Insulator-Semiconductor) junction type gate electrode (. See Non-Patent Document 2). In this method, since the insulator exists under the gate metal, the leakage current flowing through the gate electrode can be suppressed to a low level, and a large positive gate voltage can be applied. Therefore, as compared with the case where a pn junction is used for the gate electrode, the operating voltage amplitude of the gate can be sufficiently large even when the threshold voltage is set to a large positive value.

FIG. 6 shows a cross-sectional structure of a main part of a GaN FET having a conventional MIS type gate electrode. As the material of the substrate 1001, silicon carbide (SiC), silicon (Si), sapphire, GaN and the like are used. A buffer layer 1002, a GaN layer 1003, and an AlGaN layer 1004 formed by epitaxial growth are sequentially laminated on the substrate 1001. The AlGaN layer 1004 of the gate electrode forming portion is partially removed by recess etching. A gate electrode 1007 is formed in the recess etching portion 1006 with the insulating film 1005 sandwiched between them. Further, if the source electrode 1008 and the drain electrode 1009 are formed, the main part of the GaN HEMT is completed. As the material of the insulating film 1005, for example, aluminum oxide, silicon oxide, silicon nitride, or other conventionally known gate insulating materials are used. The conductive channel 1010 is formed by the conduction electrons induced on the GaN layer 1003 side of the interface between the GaN layer 1003 and the AlGaN layer 1004 having a bandgap larger than that of the GaN layer 1003. Transistor operation can be obtained by changing the conduction electron density immediately below the gate electrode 1007 of the conductive channel 1010 with the voltage applied to the gate electrode 1007. This conventional FET uses a conductive channel formed at the AlGaN / GaN semiconductor hetero interface, and is a kind of so-called HEMT.

FIG. 7 shows the cross-sectional structure of the main part of the GaN FET having another conventional MIS type gate electrode. Similar to the conventional example shown in FIG. 6, silicon carbide (SiC), silicon (Si), sapphire, GaN and the like are used as the material of the substrate 1101. The buffer layer 1102, the GaN layer 1103, and the AlGaN layer 1104 formed by epitaxial growth are sequentially laminated on the substrate 1101. Further, as the material of the insulating film 1105, for example, aluminum oxide, silicon oxide, silicon nitride, or other conventionally known gate insulating materials are used. The difference from the conventional example shown in FIG. 6 of this conventional example is that the recess etching portion 1106 is deep, and the bottom portion thereof penetrates the AlGaN layer 1104 and reaches the GaN layer 1103. The source electrode 1108 and the gate electrode 1107 and the drain electrode 1109 and the gate electrode 1107 are electrically connected by a conductive channel 1110 formed at the AlGaN / GaN interface, and the conductive channel 1111 directly under the gate electrode is insulated. It is formed by conduction electrons induced at the interface between the film 1105 and the GaN layer 1103. Transistor operation can be obtained by changing the density of the conduction electrons with the voltage applied to the gate electrode 1107.

Y. Umemoto et al. , IEEE Transitions on Electron Devices Volume 54, Number 12, December 2007, p. 3393. M. Kanamura et al. , IEEE Electronics Letters, Volume 31, Number 3, March 2010, p. 189. Bongmook Lee, et al, International Electrical Device Meeting, 2010, P.M. 484.

In the conventional example shown in FIG. 6, the purpose of forming the recess etching portion 1006 on the gate electrode portion is to normalize off by setting the threshold voltage of the FET to a positive value. Nitride semiconductors used in conventional electronic devices have a hexagonal crystal structure, and a layer grown in the c-axis direction is usually used because of the ease of epitaxial growth. In this case, large polarization due to piezo polarization and spontaneous polarization occurs in the AlGaN layer 1004 in the substrate direction along the direction orthogonal to the plane (c-axis direction).

8 (a) and 8 (b) show band diagrams of the semiconductor layer below the gate electrode. This band diagram shows the case where no voltage is applied to the gate. FIG. 8B shows a case where the thickness of the AlGaN layer 1004 is made thinner than that of the structure of FIG. 8A. In FIGS. 8 (a) and 8 (b), the energy value of the lower end of the conduction band 1201 decreases as the distance from the gate electrode increases due to the polarization (P) 1202 existing in the AlGaN layer 1004. Therefore, as shown in FIG. 8A, when the thickness of the AlGaN layer 1004 is thick, the basal quantum level formed in the triangular potential well at the contact interface between the AlGaN layer 1004 and the GaN layer 1003 is Fermi. It is located below the level 1203 (indicated as "EF" in the figure), and conduction electrons are induced in the quantum well to form the conduction channel 1010. In order to make the conduction electrons induced in the conductive channel substantially zero and normalize off without applying the gate voltage, it is necessary to reduce the thickness of the AlGaN layer 1004 as shown in FIG. 8 (b).

As described in Non-Patent Document 2, for example, when the AlN mixed crystal ratio of the AlGaN layer 1004, that is, _x when the chemical composition is expressed as Al x Ga _1-x N is 20%, the lower part of the gate electrode 1007. The thickness of the AlGaN layer 1004 of the above needs to be about 2 nanometers. As x increases, the AlGaN layer 1004 needs to be made even thinner. On the other hand, in FIG. 6, in the region between the source electrode 1008 and the gate electrode 1007, and the drain electrode 1009 and the gate electrode 1007, the thickness of the AlGaN layer 1004 is about 10 nanometers or more, which is a sufficient amount. It is necessary to induce conduction electrons in the conductive channel 1010 at the AlGaN / GaN interface to reduce the resistance in this region. Therefore, as shown in FIG. 6, it is necessary to grow the thick AlGaN layer 1004 in advance and recess-etch only the portion forming the gate electrode to thin the AlGaN layer. However, since the threshold voltage changes depending on the thickness of the remaining AlGaN layer after etching, when actually manufacturing a transistor, the etching depth of the recess etching section 1006 must be strictly controlled, and the etching depth must be strictly controlled on the substrate 1001. When a large number of transistors are manufactured all at once, it is difficult to suppress in-plane variation in the etching amount.

The conventional example shown in FIG. 6 has yet another problem. Usually, at the interface between the nitride semiconductor and the insulator, a large number of trap levels exist in the range of several hundred millielectronvolts from the lower end of the conduction band of the nitride semiconductor. In FIG. 8C, when the AlGaN layer 1004 is sufficiently thinned and the transistor is normalized off, a positive gate voltage 1205 (indicated as “V” in the figure) is applied to the gate electrode 1007 to conduct conductive electrons. Although it is a band diagram showing the state induced in the channel 1010, since the trap level 1204 exists at the interface between the insulating film 1005 and the AlGaN layer 1004, the Fermi level 1203 traps when a positive gate voltage 1205 is applied. It is fixed by level 1204 and inhibits the induction of conducted electrons into the conductive channel 1010 by the positive gate voltage 1205. As a result, the on-resistance does not decrease and the on-current does not increase, and the performance as a switch is significantly deteriorated.

On the other hand, in the conventional example shown in FIG. 7, unlike the case of FIG. 6, the recess etching portion 1106 penetrates the AlGaN layer 1104 and reaches the GaN layer 1103. Therefore, the influence of the polarization of the AlGaN layer 1004 can be avoided, and the problem of controlling the thickness of the AlGaN layer after etching is eliminated. However, the mobility of the conduction electrons in the conductive channel 1111 formed at the interface between the insulating film 1105 and the GaN layer 1103 is as small as a fraction of the mobility of the conduction electrons at the AlGaN / GaN interface. Therefore, there is a problem that the performance of the transistor is significantly lowered as compared with the so-called HEMT shown in FIG. Further, also in this conventional example, as in the conventional example shown in FIG. 6, the trap level existing at the interface between the insulating film 1105 and the GaN layer 1103 inhibits the accumulation of conductive electrons in the conductive channel 1111 and causes on-resistance. However, there was a problem that the on-current did not increase and the performance as a switch deteriorated.

As another prior art, Non-Patent Document 3 describes a method of realizing a normalization-off operation by using a structure in which a charge storage electrode is provided under a gate electrode of a nitride semiconductor FET. The nitride semiconductor FET that enables normalization by this method is obtained from the first nitride semiconductor layer provided on the substrate and the first nitride semiconductor layer provided on the first nitride semiconductor layer. It has a second nitride semiconductor layer with a large band gap, and has a gate insulating film (hereinafter referred to as the first insulating film) provided on the second nitride semiconductor layer and a charge storage film provided on the first insulating film. It has a gate electrode, and a control gate electrode is provided on the charge storage gate electrode via a block insulating film. Further, a source electrode and a drain electrode are provided on the second nitride semiconductor layer with the charge storage gate electrode interposed therebetween in the plane direction. By injecting electrons from the second nitride semiconductor layer into the charge storage gate electrode and accumulating negative charges in the charge storage gate electrode, the space between the source electrode and the drain electrode can be normalized. .. During operation, the current flowing between the source electrode and the drain electrode through the conductive channel is controlled by the voltage applied to the control gate electrode.

However, in the conventional structure as described above, the injection of electrons from the second nitride semiconductor layer into the charge storage gate electrode is actually inhibited, and a sufficient amount of electrons are accumulated in the charge storage gate electrode. It turned out that it could not be put into practical use. This is due to the following reasons. To inject electrons into the charge storage gate electrode, a positive voltage is applied to the control gate electrode and the charge storage gate electrode is placed in a forward bias state with respect to the second nitride semiconductor layer by electrostatic capacitance coupling. By doing so, it is necessary to tunnel the conduction electrons in the second nitride semiconductor layer to the charge storage gate electrode. However, the Fermi level is fixed at the trap level existing at the interface between the second nitride semiconductor layer and the first insulating film, and the forward bias voltage is not transmitted to the second nitride semiconductor layer. The electrons required for injection are not induced in the second nitride semiconductor layer. In addition, it has been pointed out that the device reliability is affected by applying a high electric field to the first insulating film during electron injection, the threshold holding time is short, and it is difficult to make the threshold uniform. ing.

Therefore, an object of the present invention is to provide a normally-off nitride semiconductor transistor apparatus capable of solving the problems in the conventional nitride semiconductor FET as described above.

The nitride semiconductor transistor device according to the present invention for solving the above problems includes a substrate, an electrically inactive element separation region provided on the substrate, and a nitride semiconductor layer provided on the substrate. A first insulating film provided on the nitride semiconductor layer, a charge storage gate electrode provided on at least the first insulating film, and a first charge storage gate electrode provided on the charge storage gate electrode. A source electrode and a drain provided on the nitride semiconductor layer with the insulating film 2 and the first gate electrode provided on the second insulating film, and the charge storage gate electrode sandwiched in the plane direction. It has an electrode, a third insulating film provided on the charge storage gate electrode, and a second gate electrode provided on the third insulating film.

The nitride semiconductor layer is preferably provided on the first nitride semiconductor layer provided on the substrate and at least a part of the first nitride semiconductor layer provided on the first nitride semiconductor layer. It is composed of a second nitride semiconductor layer containing at least a nitride semiconductor having a bandgap larger than that of the nitride semiconductor.

It is preferable that the third insulating film is provided on the charge storage gate electrode provided on the device separation region, and the second gate electrode is provided on the third insulating film on the device separation region.

In the nitride semiconductor transistor device of the present invention, a current is passed between the second gate electrode and the charge storage gate electrode to store the charge in the charge storage gate electrode, whereby the potential of the charge storage gate electrode is reached. To change.

When a current is passed between the second gate electrode and the charge storage gate electrode to store charge in the charge storage gate electrode, a voltage is applied to the first gate electrode to facilitate control of the charge injection amount. You may try to.

In the nitride semiconductor transistor apparatus of the present invention, it is preferable that the electrical capacitance between the first gate electrode and the charge storage gate electrode is larger than the electrical capacitance between the second gate electrode and the charge storage gate electrode.

Further, the electrical capacitance between the first gate electrode and the charge storage gate electrode is the electrical capacitance between the second gate electrode and the charge storage gate electrode, and the electrical capacitance between the source and the charge storage gate electrode. Greater than the sum of the electrical capacitance between the drain and the charge storage gate electrode, or the electrical capacitance between the first gate electrode and the charge storage gate electrode and the electricity between the second gate electrode and the charge storage gate electrode It is preferable that the sum of the target capacitances is larger than the sum of the electrical capacitance between the source and the charge storage gate electrode and the electrical capacitance between the drain and the charge storage gate electrode.

In the nitride semiconductor transistor device of the present invention, by applying a voltage lower than that of the source electrode, the drain electrode and the first gate electrode to the second gate electrode, between the second gate electrode and the charge storage gate electrode. It is preferable to pass a current to change the charge in the charge storage gate electrode.

In the nitride semiconductor transistor device of the present invention, when the package is sealed, the external pins are connected to the first gate electrode, the drain electrode, and the source electrode, respectively, and the second gate electrode is not connected to the external pins. It may be the same potential as the first gate electrode.

The nitride semiconductor transistor apparatus of the present invention is characterized in that the transistor is in the off state when the first gate electrode is 0 V or less.

In the nitride semiconductor transistor device of the present invention, the first gate electrode and the second gate electrode may be insulated.

In the nitride semiconductor transistor device of the present invention, the electrical capacitance formed by the first gate electrode and the charge storage gate electrode is larger than the electrical capacitance formed by the charge storage gate electrode and the nitride semiconductor layer. Is preferable.

In the nitride semiconductor transistor apparatus of the present invention, it is preferable that the area of the first gate electrode is larger than the area of the charge storage gate electrode.

In the nitride semiconductor transistor device of the present invention, it is preferable that the overlapping region of the first gate electrode and the charge storage gate electrode projects from the charge storage gate electrode to the drain electrode side.

In a preferred embodiment of the nitride semiconductor transistor apparatus of the present invention, the first nitride semiconductor layer is composed of GaN, and the second nitride semiconductor layer is Al _x Ga _1-x N (0 <x ≦ 1). Consists of. Since the conductive channel induced at the interface between GaN and Al _x Ga _1-x N has high electron mobility, a normally-off nitride semiconductor transistor apparatus having excellent switch characteristics such as on-resistance and on-current can be obtained.

In another preferred embodiment of the nitride semiconductor transistor apparatus of the present invention, at least the bottom layer of the first insulating film is made of aluminum oxide. Since aluminum oxide is unlikely to generate an interface state at the interface with the nitride semiconductor layer, the positive voltage applied to the first gate electrode is increased to form the first nitride semiconductor layer and the second nitride semiconductor layer. When increasing the current flowing through the conductive channel induced at the interface of the above, the on-resistance is less affected by the interface state existing between the second nitride semiconductor layer and the first insulating film. A normally-off nitride semiconductor transistor device having excellent characteristics as a switch such as an on-current can be obtained.

According to the present invention, by providing the second gate electrode on the charge storage gate electrode via the third insulating film, the electrons are charged from the second gate electrode via the third insulating film. Since it can be injected into the storage gate electrode and such electrons are injected independently of the first insulating film, it is nitrided by the trap level existing at the interface between the first insulating film and the nitride semiconductor layer. Conventional methods such as the injection of electrons from the physical semiconductor layer into the charge storage gate electrode is hindered and a desired amount of negative charge cannot be stored in the charge storage gate electrode, and the first insulating film is damaged during charge injection. The problem due to the structure of the above is solved, and a practical normally-off nitride semiconductor transistor device can be obtained. When the nitride semiconductor layer is composed of the first nitride semiconductor layer and the second nitride semiconductor layer, the thickness of the second nitride semiconductor layer is increased to increase the thickness of the first gate electrode. When the positive voltage applied to is increased to increase the current flowing through the conductive channel, it is less likely to be affected by the interface level existing between the second nitride semiconductor layer and the first insulating film. A normally-off nitride semiconductor transistor device having excellent switch characteristics such as on-resistance and on-current can be obtained.

According to the present invention, a normally-off nitride semiconductor transistor apparatus having excellent characteristics as a switch such as on-resistance and on-current and having little variation in characteristics can be obtained.

FIG. 1 is a plan view showing a normally-off nitride semiconductor transistor apparatus according to an embodiment of the present invention and a cross-sectional view showing AA'and BB' cross sections thereof. FIG. 2 is an equivalent circuit diagram showing the capacitance between each node of the transistor device shown in FIG. (A) shows a case where a channel is formed in the channel region included in the active region, and (b) shows a case where the transistor device is turned off and there are substantially no electrons in the channel region. There is. FIG. 3 is a plan view showing an apparatus in which a plurality of normally-off nitride semiconductor transistors are connected in parallel according to an embodiment of the present invention, and cross-sectional views showing aa'and bb' cross sections thereof, respectively. FIG. 4 is a plan view showing a normally-off nitride semiconductor transistor apparatus according to another embodiment of the present invention. FIG. 5 is a plan view showing a normally-off nitride semiconductor transistor apparatus according to another embodiment of the present invention, and a cross-sectional view showing AA'and BB' cross sections thereof, respectively. FIG. 6 is a plan view and a cross-sectional view of a conventional FET. FIG. 7 is a cross-sectional view of another conventional example FET. FIG. 8A is a diagram showing a band diagram of a FET which is a conventional example. FIG. 8B is a diagram showing a band diagram of a FET, which is also a conventional example. FIG. 8C is a diagram showing a band diagram of a FET, which is also a conventional example.

FIG. 1 shows a plan view of the FET according to an embodiment of the present invention and a sectional view thereof AA'and BB'. The scale is slightly different between the plan view and the cross-sectional view. The buffer layer 102, the GaN layer 103, and the AlGaN layer 104 are sequentially laminated on the substrate 101. As the material of the substrate 101, silicon carbide (SiC), silicon (Si), sapphire, GaN and the like are used.

Next, as shown in the plan view or the cross-sectional view, the device separation region 114 is formed by electrically inactivating the AlGaN layer 104, the GaN layer 103, or the buffer layer 102 by ion implantation. Here, the region that has not been inactivated is referred to as the active region. A method of removing the AlGaN layer 104 in the element separation region and the GaN layer 103 or the buffer layer 102 below the AlGaN layer 104 may be used. Next, the field insulating film 105 is formed. After that, the field insulating film 105 is removed only in the portion of the channel region 106 which is the channel portion of the FET, and the first insulating film 110 is formed. After that, the charge storage gate electrode 111 is formed from a metal or a conductive semiconductor layer. At this time, the charge storage gate electrode 111 may exist at least on the first insulating film 110 on the channel region 106, and may also exist on the element separation region. Here, the charge storage gate electrode 111 may be formed of a plurality of materials that are electrically connected so that the potentials are substantially the same. Subsequently, a block insulating film 112 is formed on the block insulating film 112. The block insulating film 112 is an insulating film capable of substantially blocking the flow of electrons, and is composed of a silicon oxide film, a silicon nitride film, an alumina film, a zirconium oxide film, a hafnium oxide film, or a laminated film thereof. The thickness is preferably about 40 nm in terms of SiO2 film. After that, the charge injection region 113 is formed by removing the block insulating film 112 on a part of the charge storage gate electrode 111 on the field insulating film 105, and in the region 113, on the charge storage gate electrode 111, A tunnel insulating film 115 is formed on the block insulating film 112 in areas other than the region 113. The tunnel insulating film 115 is an insulating film through which tunnel electrons can flow, and is composed of, for example, a silicon oxide film, and has a thickness of, for example, 20 nm or less. After that, the first gate electrode 116 and the second gate electrode 117 are formed by the metal or the conductive semiconductor layer. The first gate electrode 116 is formed above the main portion of the charge storage gate electrode 111 including above the channel region 106, and the second gate electrode 117 provides the charge storage gate electrode 111 in the charge injection region 113. It is formed in contact with the tunnel insulating film 115 on the portion overhanging the element separation region 114. After forming the insulating film 118 so as to cover these gate electrodes 116 and 117, the insulating films 105, 110, 112, 115 and 118 of the source forming region 107 and the drain forming region 108 are removed, and metal or metal nitride or the like is removed. The source electrode 109 and the drain electrode 210 are formed from the conductive material of the above or a laminated film thereof. At this time, the source electrode 109 and the drain electrode 210 may be in contact with only the AlGaN layer 104 or the GaN layer 103.
If it can be ensured that the current in the overlapping region of the first gate electrode 116 and the charge storage gate electrode 111 is sufficiently small during operation, the step of removing only the region of the charge injection layer without forming the block insulating film 112 The first gate electrode 116 and the charge storage gate electrode 111 may be overlapped with each other only through the tunnel insulating film 115 (which is unnecessary).

In the above manufacturing process, the source electrode 109 and the drain electrode 210 are formed immediately after the formation of the field insulating film 105, and the first insulating film 110 to the first gate electrode 116 and the second gate electrode 117 are formed. It doesn't matter.

By applying a negative voltage to the second gate electrode 117 with respect to the charge storage gate electrode 111, electrons are transmitted to the second gate electrode 117 through the tunnel insulating film 115 between the two in the charge injection region 113. Is injected into the charge storage gate electrode 111. The threshold voltage of this FET seen from the first gate electrode 116 changes depending on the amount of charge of the charge storage gate electrode 111. A so-called normally-off FET is realized by controlling the number of electrons injected from the second gate electrode 117 into the charge storage gate electrode 111 so as to obtain a desired positive voltage.

In the region between the source electrode 109 and the charge storage gate electrode 111 and the drain electrode 210 and the charge storage gate electrode 111, the thickness of the AlGaN layer 104 is about 10 nanometers or more, and a sufficient amount of conductive electrons is used. Is induced in the conductive channel at the AlGaN / GaN interface to reduce the resistance in that region. The AlN mixed crystal ratio of the AlGaN layer 104, that is, _{the value of x when the chemical formula is expressed as Al x} Ga _1-x N is appropriately adjusted so that AlGaN having a lattice constant different from that of GaN does not cause significant lattice relaxation. Usually, x is adjusted between 0.1 and 0.4. The charge storage gate electrode 111 is surrounded by a first insulating film 110, a block insulating film 112, and a tunnel insulating film 115, and is electrically in a floating state. Therefore, when the package is sealed, only the source electrode 109, the drain electrode 210, the first gate electrode 116, and the second gate electrode 117 are connected to the external pins. Alternatively, the second gate electrode 117 may be floated and sealed without being connected to an external pin. There are four or three electrodes connected to the external pins.

As the charge storage gate electrode 111, in addition to the metal layer, impurity-doped polycrystalline silicon can be used. In that case, phosphorus, arsenic, boron or the like is used as the impurity.

The capacitance between each node of the FET shown in FIG. 1 is shown in FIG. When the first gate electrode 116 is formed via the block insulating film 112 and the tunnel insulating film 115, if the area is sufficiently large, the capacity 120 formed by the charge storage gate electrode 111 and the first gate electrode 116 is formed. Is larger than the capacitance 121 formed by the second gate electrode 117 and the charge storage gate electrode 111 and the capacitance 119 formed between the charge storage gate electrode 111 and the source and drain, and is larger than the first gate electrode. The capacitive coupling between the 116 and the charge storage gate electrode 111 can be made relatively strong. At this time, the overlapping portion between the charge storage gate electrode 111 and the first gate electrode 116 may be on the element separation region 114, but by extending from the channel region 106 to the drain side in the active region, the field plate It can also be expected to play the role of.
The case where a channel is formed in the channel region 106 is represented by (a), and the case where the FET is turned off and there are substantially no electrons in the channel region 106 is represented by (b). A capacitance 120 is formed between the first gate electrode 116 and the charge storage gate electrode 111, and a capacitance 121 is formed between the second gate electrode 117 and the charge storage gate electrode 111. On the other hand, the capacitance 119 formed between the charge storage gate electrode 111 and the source and drain has the charge storage gate electrode 111 and the source when the channel is formed in the channel region 106 (FIG. (A)). -Formed between regions 122 where charge is accumulated between drains. On the other hand, when no channel is formed in the channel region 106 (FIG. (B)), the GaN is depleted and a capacitance 123 is formed between the charge storage gate electrode 111 and the source and drain, but the capacitance 123 is extremely small compared to the capacity 119.

By fixing the voltages of the first gate electrode 116, the source electrode 109, and the drain electrode 210 and applying a lower voltage to the second gate electrode 117, the charge storage gate electrode from the second gate electrode 117 A charge is injected into 111. Conditions for operating this FET, for example, from the first gate electrode 116 when the voltage of the source electrode 109 is 0 V, the voltage of the drain electrode 210 is the high voltage to be used, and the voltage of the second gate electrode 117 is 0 V. The seen threshold voltage Vth is determined by the amount of charge Qth in the charge storage gate electrode 111. Normally, Vth is set to a positive voltage. A voltage Vinj lower than that of the first gate electrode 116 and the source electrode 109 is applied to the second gate electrode 117, and a voltage is applied until the total injection amount reaches Qth. At this time, when the source voltage is 0 V, the voltage of the second gate electrode is Vinj, and the charge amount of the charge storage gate electrode 111 is Qth, the charge of the channel region 106 is substantially extinguished so that the charge of the first gate electrode disappears. If a voltage is applied, the capacity 119 in FIG. 2 changes to the capacity 123 when the amount of charge of the charge storage gate electrode 111 reaches Qth, and the capacity between the charge storage gate electrode 111 and the source and drain. Since the coupling is weakened, the absolute value of the voltage between the charge storage gate electrode 111 and the first gate electrode 116 and the second gate electrode 117 becomes extremely small, and the charge injection is substantially stopped.

When operating the FET of the present invention after charging, the first gate electrode 116 is required to reduce the voltage applied to the first gate electrode 116 required to turn on / off the current flowing between the source and drain. It is desirable that the capacity 120 formed by the charge storage gate electrode 111 is sufficiently larger than the other capacities. If possible, the capacitance 120 is the capacitance between the charge storage gate electrode 111 and the region 122 where the charge between the source and drain is accumulated in the capacitance 121 formed by the second gate electrode 117 and the charge storage gate electrode 111. It is desirable that it is larger than the sum of 119. Alternatively, when the second gate electrode is operated at the same potential as the first gate electrode, it is desirable that the sum of the capacitance 120 and the capacitance 121 be larger than the capacitance 119. In these cases, the area where the first gate electrode 116 forming the capacitance 120 and the charge storage gate electrode 111 overwrap is larger than the area where the second gate electrode 117 and the charge storage gate electrode 111 overwrap. This can be achieved by extending the charge storage gate electrode 111 from the channel region 106 to the drain electrode 210 side in the active region, and the block insulating film 112 and the tunnel above it. This can be achieved by forming the first gate electrode 116 via the insulating film 115.

In the FET of the present invention, a second gate electrode 117 is provided via a tunnel insulating film 115 on a portion of the charge storage gate electrode 111 extending above the element separation region 114, and this portion, that is, a charge injection region. In 113, a current is passed between the second gate electrode 117 and the charge storage gate electrode 111 to accumulate charges in the charge storage gate electrode 111, thereby changing the potential of the charge storage gate electrode. Therefore, the influence of the charge injection does not reach the first insulating film 110, and the problems due to the conventional structure such that the first insulating film 110 is damaged at the time of charge injection are solved, and it is practical. A normally-off nitride semiconductor FET can be obtained.

Here, when it is desired to obtain a large drain current, a plurality of structures of FIG. 1 may be arranged side by side, and the first gate electrode 116, the second gate electrode 117, the source electrode 109, and the drain electrode 210 may be connected in parallel. .. At this time, all the second gate electrodes 117 are not connected in parallel, and one pad is pulled out for each transistor, or one pad is drawn out for each transistor, which is less than the total number, so that electron injection can be performed. After adjusting the threshold value, the variation in the threshold value of the transistors connected to the plurality of transistors becomes small. Further, if the process of connecting in parallel is performed by bonding the package instead of the wafer process, a semiconductor device that removes defective chips and allows a large current to flow is obtained.

When connecting in parallel, as shown in FIG. 3, the source electrode 109 and the drain electrode 210 are arranged alternately, and the charge storage gate 111 is arranged between them, and the first gate electrode 116 and the source electrode 109, respectively, are arranged. If the drain electrode 210 is connected, the area is smaller and a larger current can be obtained than the above-mentioned parallel connection of single transistors. At this time, when the first gate electrode 116 is formed via the block insulating film 112 and the tunnel insulating film 115 as in the case of the single unit described above, if the area is sufficiently large, the charge storage gate electrode 111 and The capacity 120 formed by the first gate electrode 116 is based on the capacity 121 formed by the second gate electrode 117 and the charge storage gate electrode 111, or the capacity 119 formed by the charge storage gate electrode 111 and the source or drain. growing. At this time, by extending the charge storage gate electrode 111 and the first gate electrode 116 toward the drain side of the active region, it can be expected to play the role of a field plate.

Further, as shown in FIG. 4, if the overlapping portion between the charge storage gate electrode 111 and the first gate electrode 116 is formed on the element separation region 114, the capacity 120 can be increased. As long as the area of the overlapping portion on the element separation region 114 is sufficiently large, the extension of the charge storage gate electrode 111 and the first gate electrode 116 to the drain side may be shortened or eliminated. Alternatively, the overlapping portion between the charge storage gate electrode 111 and the first gate electrode 116 may be formed only on the element separation region 114. Also in this case, by extending the charge storage gate electrode 111 from the channel region to the drain side in the active region, it can also serve as a field plate. In this embodiment, the case where the charge storage gate electrode 111 in the active region and the charge storage gate electrode 111 formed on the element separation region 114 are simultaneously formed by a common conductive film is shown, but in the active region. The charge storage gate electrode 111 and the charge storage gate electrode 111 formed on the element separation region 114 may be formed of different conductive films and electrically connected to each other.

As shown in FIG. 3, the second gate electrode 117 may be provided one by one for a cell composed of one source / drain and one charge storage gate electrode 111, or one in a plurality. It may be provided. In the case of one place as a whole, it may be outside the cell as shown in FIG. In the case of one in total, the threshold value is adjusted by the above-mentioned charge injection method, but if the cell is divided to form the second gate electrode 117, the charge injection is stopped for each unit, so the threshold value adjustment is high. It will be refined.

In the above-described embodiment, the case where GaN and AlGaN are used as the nitride semiconductor has been described. Since the band gap of AlGaN is larger than the band gap of GaN, a conductive channel is formed on the GaN side of the interface between AlGaN and GaN. This conductive channel is used in the above-described embodiment. In the present invention, a nitride semiconductor other than GaN and AlGaN may be used. For example, a nitride semiconductor containing In such as InN, InGaN, and InAlN may be used. Alternatively, a multilayer structure of nitride semiconductors having different compositions may be used. The material and composition may be selected so that the main part of the lower layer is formed of a nitride semiconductor having a small bandgap and the main part of the upper layer is formed of a nitride semiconductor having a large bandgap.

For the purpose of protecting the surface of the second nitride semiconductor, another nitride semiconductor having a composition different from that of the second nitride semiconductor may be inserted. For example, when the first nitride semiconductor is GaN and the second nitride semiconductor is AlGaN, a thin GaN layer may be inserted directly above AlGaN.

In the channel region 106, the first insulating film 110 may be formed after the AlGaN layer 104 is half-etched. In this case, since the AlGaN layer 104 becomes thin, it exists at the interface between the first insulating film 110 and the AlGaN layer 104 when the positive voltage applied to the first gate electrode is increased to increase the current flowing through the conductive channel. The Fermi level is easily fixed at the trap level, and as a result, the induction of conductive electrons into the conductive channel is hindered, and the characteristics such as on-resistance deteriorate. On the other hand, since the AlGaN layer 104 becomes thin and the amount of shift of the threshold voltage to the negative side due to polarization is reduced, the amount of negative charge injected into the charge storage gate electrode 111 in order to obtain a desired positive threshold voltage is reduced. Can be done. Further, although the initial threshold voltage varies due to the variation in the etching depth, the variation can be compensated by the above-mentioned method of automatically stopping the charge injection into the charge storage gate electrode 111.

In the above examples, the case where the conductive channel in the channel region is composed of the conductive channel formed at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer has been described. On the other hand, in the present invention, the first insulating film is provided directly above the single-layer nitride semiconductor, and the current between the source and drain is transmitted through the conductive channel formed at the interface between the nitride semiconductor and the first insulating film. It can also be applied to flowing nitride semiconductor transistors. An embodiment in this case is shown in FIG. In FIG. 5, in the embodiment shown in FIG. 1, the AlGaN layer 104 in the channel region is removed and dug up to the GaN layer 103 to form the first insulating film 110 directly above the GaN layer 103 for charge storage. The gate electrode 111 is formed. The current between the source and drain during transistor operation flows through the conductive channel formed at the interface between the first insulating film 110 and the GaN layer 103. Other than that, it is the same as the embodiment shown in FIG. The threshold voltage of the transistor may be adjusted in the same manner as the method described with reference to FIGS. 1 and 2. In the nitride semiconductor transistor of this embodiment, the conductive channel is strongly affected by the trap level existing at the interface between the first insulating film 110 and the GaN layer 103, and the electron mobility of the conductive channel is lowered. Since there is a problem that the induction of electrons to the conductive channel by applying a positive voltage to the gate electrode 116 is hindered, the characteristics such as on-resistance are significantly higher than those of the nitride semiconductor transistor according to the embodiment shown in FIG. Inferior. However, since there is no shift of the threshold voltage to the negative side due to the polarization of the AlGaN layer, the amount of negative charge injected into the charge storage gate electrode 111 in order to obtain the positive threshold voltage required for the desired normalization-off operation is significantly increased. Can be reduced. Further, in a transistor composed of a plurality of cells, the threshold between cells can be automatically stopped when the desired threshold voltage is reached, and the charge injection from the second gate electrode 117 to the charge storage gate electrode 111 can be automatically stopped. It is the same as the case of the nitride semiconductor transistor described with reference to FIGS. 1 to 3 in that the effect of reducing the voltage variation can be obtained.

The nitride semiconductor transistor device of the present invention is mainly useful as a power switch used in a power supply circuit or the like. In addition, it is also useful as a high-frequency transistor used in wireless communication, sensors, and the like. When used as a high-frequency transistor, the transistor can be operated only with a positive voltage power supply by adjusting the threshold voltage positively according to the present invention, so that the negative voltage power supply, which has been conventionally required, can be eliminated. Further, even when the transistor is operated with the threshold value kept negative, the threshold voltage variation between the transistors or between the gates in the transistor in the transistor composed of a plurality of gate electrodes is obtained by the threshold voltage adjusting method according to the present invention. The threshold voltage variation can be reduced, and a good transistor with little characteristic variation can be obtained.

101 ... substrate, 102 ... buffer layer, 103 ... GaN layer, 104 ... AlGaN layer, 105 ... field insulating film, 106 ... channel region, 107 ... source forming region, 108 ... Drain forming region, 109 ... Source electrode, 210 ... Drain electrode, 110 ... First insulating film, 111 ... Charge storage gate electrode, 112 ... Block insulating film, 113 ... Charge injection region, 114 ... Element separation region, 115 ... Tunnel insulating film, 116 ... First gate electrode, 117 ... Second gate electrode, 118 ... Insulating film , 119: Capacity between the charge storage gate electrode and the conductive channel directly under the gate, 120: Charge between the charge storage gate electrode and the first gate electrode, 121: Charge storage gate electrode and the second gate Capacity between electrodes, 122 ... Region where charge is accumulated between source and drain, 123 ... Capacity between the gate electrode for charge storage and the floating region where the conductive channel directly under the gate is not formed. 1001 ... Substrate, 1002 ... Buffer layer, 1003 ... GaN layer, 1004 ... AlGaN layer, 1005 ... Insulation film, 1006 ... Recess etching section, 1007 ... Gate electrode, 1008 ... Source electrode, 1009 ... Drain electrode, 1010 ... Conductive channel, 1101 ... Substrate, 1102 ... Buffer layer, 1103 ... GaN layer, 1104 ... AlGaN layer, 1105 ... Insulating film, 1106 ... recess etching part, 1107 ... gate electrode, 1108 ... source electrode, 1109 ... drain electrode, 1110 ... conductive channel, 1111 ... conductive channel, 1201 ... The lower end of the conductive band, 1202 ... Polarization (P) existing in the AlGaN layer, 1203 ... Fermi level (EF), 1204 ... Trap level, 1205 ... Positive gate voltage

Claims (23)

A substrate, an electrically inactive element separation region provided on the substrate, a nitride semiconductor layer provided on the substrate, and a first insulating film provided on the nitride semiconductor layer. , At least a charge storage gate electrode provided on the first insulating film, a second insulating film provided on the charge storage gate electrode, and a second insulating film provided on the second insulating film. A gate electrode of No. 1, a source electrode and a drain electrode provided on the nitride semiconductor layer with the charge storage gate electrode sandwiched in the plane direction, and a third insulation provided on the charge storage gate electrode. A nitride semiconductor transistor apparatus comprising a film and a second gate electrode provided on the third insulating film. The third insulating film is located on the charge storage gate electrode provided on the element separation region, and the second gate electrode is provided on the third insulating film. 1 Nitride semiconductor transistor device. Claim 1 is characterized in that the potential of the charge storage gate electrode is changed by passing a current between the second gate electrode and the charge storage gate electrode and accumulating the charge in the charge storage gate electrode. Or 2 nitride semiconductor transistor device. When a current is passed between the second gate electrode and the charge storage gate electrode to store charge in the charge storage gate electrode, a voltage is applied to the first gate electrode to facilitate control of the charge injection amount. 3. The nitride semiconductor transistor apparatus according to claim 3. One of claims 1 to 4, wherein the electrical capacitance between the first gate electrode and the charge storage gate electrode is larger than the electrical capacitance between the second gate electrode and the charge storage gate electrode. Nitride semiconductor transistor device. The electrical capacitance between the first gate electrode and the charge storage gate electrode is the electrical capacitance between the second gate electrode and the charge storage gate electrode, and the electrical capacitance and drain between the source and the charge storage gate electrode. The nitride semiconductor transistor apparatus according to any one of claims 1 to 4, wherein the sum is larger than the sum of the electric capacitance between the charge storage gate electrodes. By applying a voltage lower than that of the source electrode, the drain electrode, and the first gate electrode to the second gate electrode, a current is passed between the second gate electrode and the charge storage gate electrode, whereby the charge storage gate electrode. The nitride semiconductor transistor apparatus according to any one of claims 1 to 6, wherein the electric charge inside is changed. The nitride semiconductor transistor apparatus according to any one of claims 1 to 7, wherein the transistor is in an off state when the first gate electrode is 0 V or less. The nitride semiconductor transistor apparatus according to any one of claims 1 to 8, wherein the first gate electrode and the second gate electrode are insulated from each other. The feature is that the electrical capacitance formed by the first gate electrode and the charge storage gate electrode is larger than the electrical capacitance formed by the charge storage gate electrode and the nitride semiconductor layer when the transistor is on. The nitride semiconductor transistor apparatus according to any one of claims 1 to 9. The nitride semiconductor transistor apparatus according to claim 10, wherein the area of the first gate electrode is larger than the overlapping area of the charge storage gate electrode and the channel region. The nitride semiconductor transistor apparatus according to any one of claims 1 to 11, wherein the overlapping region of the first gate electrode and the charge storage gate electrode projects from the channel region to the drain electrode side. The nitride semiconductor transistor apparatus according to any one of claims 1 to 12, wherein the second insulating film and the third insulating film are the same insulating film. The nitride semiconductor transistor apparatus according to any one of claims 1 to 13, wherein the third insulating film is a tunnel insulating film. The nitride semiconductor transistor apparatus according to any one of claims 1 to 12, wherein the second insulating film includes a block insulating film. Claim 1 in which a plurality of the transistors are connected in parallel, electrodes other than the second gate electrode are connected in parallel, and one or several transistors are provided with a second gate electrode one by one. A nitride semiconductor transistor apparatus according to any one of 15 to 15. The nitride semiconductor transistor device according to claim 16, which has a finger structure in which sources and drains are alternately arranged and charge storage gate electrodes are arranged between the plurality of transistors. When a current is passed between the second gate electrode and the charge storage gate electrode to control the amount of charge injected when the charge is stored in the charge storage gate electrode by applying a voltage to the first gate electrode. The nitride semiconductor transistor apparatus according to claim 16 or 17, wherein the amount of electric charge is adjusted for each portion having a common second gate electrode. The nitride semiconductor transistor apparatus according to any one of claims 1 to 18, wherein at least the lowermost layer of the first insulating film is made of aluminum oxide. The nitride semiconductor transistor apparatus according to any one of claims 1 to 19, wherein the nitride semiconductor layer is made of GaN. The nitride semiconductor layer is provided on the first nitride semiconductor layer provided on the substrate and the first nitride semiconductor layer, and at least a part of the nitride of the first nitride semiconductor layer is nitrided. The nitride semiconductor transistor apparatus according to any one of claims 1 to 19, further comprising a second nitride semiconductor layer including at least a nitride semiconductor having a bandgap larger than that of the semiconductor. The first nitride semiconductor layer is made of GaN, and the second nitride semiconductor layer is made of Al _x Ga _1-x N (0 <x ≦ 1). Item 21. Nitride semiconductor transistor apparatus. A nitride semiconductor transistor apparatus according to any one of claims 1 to 22 and a package for sealing the transistor apparatus are included, and a first gate electrode, a drain electrode, and a source electrode of the transistor apparatus are included in each of the packages. A nitride semiconductor device characterized in that the second gate electrode of the transistor device is connected to each of the external pins of the transistor device and is not connected to the external pin.

Images