JP2021040404A - Motor driver device and semiconductor apparatus - Google Patents

Abstract

To make a contribution to improvement in operation involved in a windowless driving system.SOLUTION: A driving control unit, of a motor driver device, for drivingly switching a DC motor, detects a zero-cross timing of counter electromotive force generated in a coil in a prescribed phase of the DC motor during a window section for stopping a current flow to the coil in the prescribed phase, and drivingly controls the motor by a first driving system (window driving system) of drivingly controlling the motor on the basis of the detected zero-cross timing of counter electromotive force, or by a second driving system (windowless driving system) of drivingly controlling the motor on the basis of a zero-cross timing of a driving current flowing through the coil in the prescribed phase and a zero-cross timing of a driving voltage applied to the coil in the prescribed phase. The driving control unit is configured to be able to detect a zero-cross timing of counter electromotive force by setting a window section even when drivingly controlling the motor by the second driving system.SELECTED DRAWING: Figure 17

Description

The present invention relates to a motor driver device and a semiconductor device.

In a motor that does not have a commutation mechanism using a brush, such as a brushless DC motor, it is necessary to switch the direction of the current supplied to the coil according to the position of the rotor. As the drive method of the brushless DC motor, the position of the rotor is determined based on the zero cross point of the counter electromotive force (induced voltage) generated in the coil without using the Hall element and the method using the position information of the rotor obtained from the Hall element. The sensorless method of estimation is widely known.

As a control method for the three-phase brushless motor, a 120-degree energization method (rectangular wave drive) and a 180-degree energization method (sine wave drive) are widely used. The 120-degree energization method has the advantage of being relatively easy to control, while the 180-degree energization method has the advantage of being relatively quiet and having good vibration characteristics.

In order to detect the counter electromotive force in the sensorless method, it is necessary to make the current flowing through the coil zero. In the 120-degree energization method, a non-energized section is set for the coil of each phase, so that the counter electromotive force can be easily detected by using the non-energized section. On the other hand, in the 180-degree energization method, since a current always flows through each coil, it is not possible to use the non-energized section as in the 120-degree energization method. Therefore, in the 180-degree energization method, a window section including the time when the zero cross point of the counter electromotive force is likely to occur is set, and the output of the driver is forcibly set to a high impedance state in the window section (hereinafter, window drive). A method (referred to as a method) is used (see, for example, Patent Documents 1 and 2 below). However, the setting of the window section may impair the quietness, which is the original advantage of the 180-degree energization method.

In consideration of this, a method that does not require the output of the driver to be forced into a high impedance state (hereinafter referred to as a windowless drive method) has also been proposed. In the windowless drive system, at least the terminal voltage of the coil is used to detect the polarity reversal timing (timing in which the direction of current flow is reversed) of the current flowing through the coil (see, for example, Patent Documents 3 and 4 below). By periodically detecting (sampling) the polarity of the current, the phase information of the current can be acquired, and a pulse width-modulated drive control signal can be generated based on the acquired phase information. Then, the motor can be driven sensorlessly by supplying a drive voltage having a duty based on the drive control signal to the coils of each phase.

Japanese Unexamined Patent Publication No. 2010-4733 International Publication No. 2009/150794 Japanese Patent No. 6231357 Japanese Unexamined Patent Publication No. 10-341588

In the motor driver device that can drive and control the motor by the window drive system or the windowless drive system, there is room for improvement in the operation related to the windowless drive system. As an example, there was room for improvement in response to a request for a smooth transition from the windowless drive system to the window drive system. As another example, there was room for improvement in optimizing drive control in the windowless drive system.

The present invention contributes to the improvement of the operation related to the windowless drive system (for example, contributes to the smooth transition from the windowless drive system to the window drive system, or contributes to the optimization of the drive control in the windowless drive system. It is an object of the present invention to provide a motor driver device and a semiconductor device.

The motor driver device according to the present invention is a motor driver device that switches and drives a DC motor, and has a zero cross of countercurrent force generated in the predetermined phase coil in a window section for stopping energization of the predetermined phase coil of the DC motor. The first drive method that detects the timing and controls the drive of the motor based on the detection zero-cross timing of the countercurrent force, or the zero-cross timing of the drive current flowing through the coil of the predetermined phase and the application to the coil of the predetermined phase. In the second drive system that controls the drive of the motor based on the zero cross timing of the drive voltage, the drive control unit that controls the drive of the motor is provided, and the drive control unit is the second drive system. This is a configuration (first configuration) in which the window section is set so that the zero cross timing of the countercurrent force can be detected even when the drive control of the motor is being performed.

In the motor driver device according to the first configuration, the drive control unit switches the drive system of the motor from the first drive system to the second drive system, and then sets the drive system of the motor to the second drive system. Upon receiving a transition instruction signal indicating that the system should be switched to the first drive system, the window section is set while maintaining the drive system of the motor in the second drive system, and the counter electromotive force is detected at zero cross timing. The motor drive system may be changed from the second drive system to the first drive system after the adjustment operation is completed (second configuration).

In the motor driver device according to the second configuration, the drive control unit includes a back electromotive force zero cross detection unit that derives the back electromotive force detection zero cross timing based on the voltage between both terminals of the coil in the window section. The counter electromotive force zero cross estimation unit that derives the estimated zero cross timing of the counter electromotive force by estimating the zero cross timing of the counter electromotive force based on the zero cross timing of the drive current and the zero cross timing of the drive voltage, and the first When the drive control of the motor is performed by the drive method, the estimated zero cross timing of the counter electromotive force is obtained when the drive control of the motor is performed by the second drive method based on the detection zero cross timing of the counter electromotive force. Based on this, a signal processing unit that generates a drive control signal for the coil of each phase of the motor and also generates a drive voltage zero-cross signal indicating the zero-cross timing of the drive voltage is provided, and is generated by the signal processing unit. The drive voltage zero cross signal is fed back to the counter electromotive force zero cross estimation unit and used for estimating the counter electromotive force zero cross timing, and the signal processing unit uses the counter electromotive force detection zero cross timing in the adjustment operation. A configuration (third configuration) that reduces the phase error of the counter electromotive force from the estimated zero cross timing may be used.

In the motor driver device according to the third configuration, the signal processing unit adjusts the advance angle, which is the phase difference between the estimated zero cross timing of the counter electromotive force and the zero cross timing of the drive voltage, in the adjustment operation. Therefore, the configuration may be such that the phase error is reduced (fourth configuration).

In the motor driver device according to the fourth configuration, in the signal processing unit, the adjustment operation may be completed when the magnitude of the phase error is equal to or less than a predetermined threshold value (fifth configuration).

In the motor driver device according to the first configuration, the drive control unit drives the motor when a predetermined open condition is satisfied when the drive control of the motor is performed by the second drive method. The second drive system may be maintained, the window section may be set, and a predetermined operation may be performed using the counter electromotive force detection zero cross timing (sixth configuration).

In the motor driver device according to the sixth configuration, the drive control unit includes a back electromotive force zero cross detection unit that derives the back electromotive force detection zero cross timing based on the voltage between both terminals of the coil in the window section. The counter electromotive force zero cross estimation unit that derives the estimated zero cross timing of the counter electromotive force by estimating the zero cross timing of the counter electromotive force based on the zero cross timing of the drive current and the zero cross timing of the drive voltage, and the first When the drive control of the motor is performed by the drive method, the estimated zero cross timing of the counter electromotive force is obtained when the drive control of the motor is performed by the second drive method based on the detection zero cross timing of the counter electromotive force. Based on this, a signal processing unit that generates a drive control signal for the coil of each phase of the motor and also generates a drive voltage zero-cross signal indicating the zero-cross timing of the drive voltage is provided, and is generated by the signal processing unit. The drive voltage zero cross signal is fed back to the counter electromotive force zero cross estimation unit and used for estimating the counter electromotive force zero cross timing, and the signal processing unit uses the counter electromotive force detection zero cross timing in the predetermined operation. A configuration (seventh configuration) that reduces the phase error of the counter electromotive force from the estimated zero cross timing may be used.

In the motor driver device according to the seventh configuration, the drive control unit completes the predetermined operation when the magnitude of the phase error becomes equal to or less than a predetermined threshold value, and drives the motor by the second drive method. It may be a configuration (eighth configuration) that controls and returns to the state in which the window section is not set.

In the motor driver device according to the seventh or eighth configuration, the signal processing unit sets an advance angle which is a phase difference between the estimated zero cross timing of the counter electromotive force and the zero cross timing of the drive voltage in the predetermined operation. The configuration may be such that the phase error is reduced by adjusting (the ninth configuration).

In the motor driver device according to the sixth configuration, the drive control unit includes a back electromotive force zero cross detection unit that derives the back electromotive force detection zero cross timing based on the voltage between both terminals of the coil in the window section. The counter electromotive force zero cross estimation unit that derives the estimated zero cross timing of the counter electromotive force by estimating the zero cross timing of the counter electromotive force based on the zero cross timing of the drive current and the zero cross timing of the drive voltage, and the first When the drive control of the motor is performed by the drive method, the estimated zero cross timing of the counter electromotive force is obtained when the drive control of the motor is performed by the second drive method based on the detection zero cross timing of the counter electromotive force. Based on this, a signal processing unit that generates a drive control signal for the coil of each phase of the motor and also generates a drive voltage zero-cross signal indicating the zero-cross timing of the drive voltage is provided, and is generated by the signal processing unit. The drive voltage zero cross signal is fed back to the counter electromotive force zero cross estimation unit and used for estimating the counter electromotive force zero cross timing, and the drive control unit uses the counter electromotive force detection zero cross timing in the predetermined operation. A configuration in which a phase error with the estimated zero cross timing of the counter electromotive force is derived, and when the magnitude of the phase error is equal to or greater than a predetermined value, the drive method of the motor is switched from the second drive method to the first drive method. (10th configuration) may be used.

In the motor driver device according to any one of the first to tenth configurations, the drive control unit determines the difference phase between the zero cross timing of the drive current and the zero cross timing of the drive voltage in the second drive system. The configuration may be such that the drive control of the motor is performed so as to match the target phase of (11th configuration).

In the motor driver device according to any one of the first to eleventh configurations, the spindle motor for rotating the magnetic disk of the magnetic disk device is switched and driven as the DC motor (12th configuration).

The semiconductor device according to the present invention is a semiconductor device that forms the motor driver device according to any one of the first to twelfth configurations, and the motor driver device is formed by using an integrated circuit (13th). Configuration).

According to the present invention, it contributes to the improvement of the operation related to the windowless drive system (for example, contributes to the smooth transition from the windowless drive system to the window drive system, or the optimization of the drive control in the windowless drive system. It becomes possible to provide a motor driver device and a semiconductor device (which contributes to).

It is a schematic block diagram which concerns on the mechanism of the hard disk apparatus which concerns on 1st Embodiment of this invention. It is an electric schematic block diagram of the hard disk apparatus which concerns on 1st Embodiment of this invention. It is external perspective view of the driver IC mounted on the hard disk apparatus which concerns on 1st Embodiment of this invention. It is a block diagram of the SPM and the SPM driver which concerns on 1st Embodiment of this invention. FIG. 5 is a diagram showing a waveform of a counter electromotive force generated in a U-phase coil in SPM and a signal waveform related thereto according to the first embodiment of the present invention. It is a figure which shows the appearance that a plurality of frames are arranged in a time series according to the 1st Embodiment of this invention. It is an internal block diagram of the drive control part which concerns on 1st Embodiment of this invention. FIG. 5 is a configuration diagram relating to the generation of a drive current zero cross signal according to the first embodiment of the present invention. FIG. 7 is a selection state diagram of two selectors shown in FIG. 7 according to the first embodiment of the present invention. It is a figure which shows the example of the method of generating a window signal which concerns on 1st Embodiment of this invention. It is a figure which shows the WLE generation part which concerns on 1st Embodiment of this invention. It is a figure which shows the basic operation of the window drive system which concerns on 1st Embodiment of this invention. It is a figure which shows one configuration example of the phase control part shown in FIG. 7. It is a figure which shows the basic operation of the windowless drive system which concerns on 1st Embodiment of this invention. It is a figure which shows the transition sequence from the window drive system to the windowless drive system which concerns on 1st Embodiment of this invention. It is a figure which shows the phase error control part which concerns on 1st Embodiment of this invention. It is a figure which shows the transition sequence from the windowless drive system to the window drive system which concerns on 1st Embodiment of this invention. It is explanatory drawing of the phase error which concerns on 1st Embodiment of this invention. It is explanatory drawing of the advance angle which concerns on 1st Embodiment of this invention. It is a flowchart of the adjustment operation which concerns on 1st Embodiment of this invention. It is a figure which shows the transition sequence from the windowless drive system to the window drive system which concerns on a reference method. It is a figure (a) which shows the input / output signal of a selector, the selection state diagram (b) of a selector, and a sequence diagram (c) which concerns on the setting of a window section, according to the 2nd Embodiment of this invention.

Hereinafter, examples of embodiments of the present invention will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are designated by the same reference numerals, and duplicate explanations regarding the same parts will be omitted in principle. In this specification, for the sake of simplification of description, by describing a symbol or a code that refers to an information, a signal, a physical quantity, an element or a part, etc., the information, a signal, a physical quantity, an element or a part corresponding to the symbol or the code is described. Etc. may be omitted or abbreviated. For example, the measured BEMF zero-cross signal referred to by “BZX1” described below (see FIG. 7) may be referred to as the measured BEMF zero-cross signal BZX1 or may be abbreviated as signal BZX1, but they may be abbreviated. All refer to the same thing.

First, some terms used in the description of the embodiments of the present invention will be described.
IC is an abbreviation for Integrated Circuit. The ground refers to a conductive portion having a reference potential of 0 V (zero volt) or the potential of 0 V itself. The potential of 0V may be referred to as a grant potential. In the embodiment of the present invention, the voltage shown without any particular reference represents the potential seen from the ground.
Level refers to the level of potential, where a high level has a higher potential than a low level for any signal or voltage. For any signal or voltage, a signal or voltage at a high level means that the signal or voltage level is at a high level, and a signal or voltage at a low level means that the signal or voltage level is at a low level. Means that it is in.
For any signal or voltage, switching from low level to high level is called up edge, and timing of switching from low level to high level is called up edge timing. Similarly, for any signal or voltage, switching from high level to low level is referred to as down edge, and timing of switching from high level to low level is referred to as down edge timing.
For any transistor configured as a FET (Field Effect Transistor) including a MOSFET, the on state means that the drain and source of the transistor are in a conductive state, and the off state means the drain of the transistor. And it means that there is a non-conduction state (interruption state) between the sources. The same applies to transistors that are not classified as FETs. Unless otherwise specified, the MOSFET may be understood as an enhancement type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". For any transistor, the on-state and off-state may be simply expressed as on and off.
For any signal having a high level or low level signal level, a section in which the level of the signal is high level is referred to as a high level section, and a section in which the level of the signal is low level is referred to as a low level section. The same is true for any voltage that has a high or low level voltage level.

<< First Embodiment >>
The first embodiment of the present invention will be described. FIG. 1 is a schematic configuration diagram relating to the mechanism of a hard disk device (hereinafter referred to as an HDD device) 1 as a magnetic disk device according to the first embodiment of the present invention.

The HDD device 1 uses a magnetic disk 10 as a recording medium, a magnetic head 11 (hereinafter, also referred to as a head 11) for writing and reading information to and from the magnetic disk 10, and a magnetic head 11 having a radius of the magnetic disk 10. An arm 12 that supports the magnetic disk 10 so as to be movable in a direction, a spindle motor 13 that supports and rotates the magnetic disk 10 (hereinafter, also referred to as SPM 13), and a magnetic disk 11 that is driven and positioned to rotate the arm 12. A voice coil motor 14 (hereinafter, also referred to as VCM 14) that moves and positions in the radial direction of 10 is provided.

The HDD device 1 further includes a pair of piezoelectric elements 15, a load beam 16, and a lamp unit 17 that holds the magnetic head 11 in a predetermined retracted position away from the magnetic disk 10. The load beam 16 is attached to the tip of the arm 12, and the magnetic head 11 is attached to the tip of the load beam 16. A pair of piezoelectric elements 15 are arranged near the attachment portion of the load beam 16 at the tip end portion of the arm 12. By applying voltages of opposite phases to the pair of piezoelectric elements 15, the pair of piezoelectric elements 15 expand and contract in opposite phases, and the magnetic head 11 at the tip of the load beam 16 is displaced in the radial direction of the magnetic disk 10. be able to.

As described above, the HDD device 1 employs a so-called two-stage actuator system. The VCM 14 functions as a coarse acting actuator that roughly positions the magnetic head 11 on the magnetic disk 10 (positioning with a relatively rough resolution) by driving the arm 12, and the pair of piezoelectric elements 15 are located at the position of the arm 12. By adjusting the position of the magnetic head 11 with reference to, the magnetic head 11 functions as a fine movement actuator that precisely positions the magnetic head 11 on the magnetic disk 10 (positions with a finer resolution than the VCM 14). In the following, an actuator composed of a pair of piezoelectric elements 15 will be referred to as MA15 by using the abbreviation "MA" of the microactuator.

The magnetic disk 10, the magnetic head 11, the arm 12 to which the MA15 and the load beam 16 are attached, the SPM 13, the VCM 14, and the lamp unit 17 are housed in the housing of the HDD device 1. Regarding the movement and displacement of the magnetic head 11 by the VCM 14 or MA15, the movement and displacement of the magnetic disk 10 in the radial direction means the movement and displacement in the direction connecting the outer periphery and the center of the disk-shaped magnetic disk 10. However, the movement and displacement of the magnetic head 11 by the VCM 14 or MA15 causes the movement and displacement of the magnetic disk 10 in the radial direction as well as the components of the movement and displacement in other directions (for example, the tangential direction of the outer periphery of the magnetic disk 10). May include.

FIG. 2 is an electrical schematic block diagram of the HDD device 1. The HDD device 1 is provided with a driver IC 30, a signal processing circuit 21, an MPU (micro-processing unit) 22, and a power supply circuit 23 as electrical components. The power supply circuit 23 supplies the driver IC 30, the signal processing circuit 21, and the power supply voltage for driving the MPU 22 to them. The MPU 22 is connected to each of the signal processing circuit 21 and the driver IC 30 in a form capable of bidirectional communication.

When writing information to the magnetic disk 10, the signal processing circuit 21 outputs a recording signal for writing the information to the magnetic head 11, and when reading information from the magnetic disk 10, the signal read from the magnetic disk 10 Is subjected to necessary signal processing, and the signal obtained by this is sent to the MPU 22. The MPU 22 controls the information writing operation and reading operation by the magnetic head 11 through the control of the signal processing circuit 21.

The driver IC 30 is an electronic component (driver device) formed by enclosing a semiconductor integrated circuit as shown in FIG. 3 in a housing (package) made of resin. The number of pins (number of external terminals) of the driver IC 30 shown in FIG. 3 is merely an example. The driver IC 30 is provided with an SPM driver 33 for driving and controlling the SPM 13, a VCM driver 34 for driving and controlling the VCM 14, and an MA driver 35 for driving and controlling the MA 15, and bidirectionally between the MPU 22 and the driver IC 30. An IF circuit (interface circuit) 32 for enabling communication, a control circuit 31 for controlling the operation of the drivers 33 to 35 based on the control data received from the MPU 22 through the IF circuit 32, and the like are provided.

The MPU 22 controls the rotation of the magnetic disk 10 through the drive control of the SPM 13 by controlling the SPM driver 33 of the driver IC 30, and controls the VCM driver 34 and the MA driver 35 of the driver IC 30 through the drive control of the VCM 14 and MA 15. The movement control and positioning of the magnetic head 11 are performed. Position information indicating each position on the magnetic disk 10 is recorded at each location of the magnetic disk 10, and when the magnetic head 11 is located on the magnetic disk 10, this position information is read by the magnetic head 11. Is transmitted to the MPU 22 through the signal processing circuit 21. The MPU 22 can control the VCM driver 34 and the MA driver 35 based on the position information, and through this control, the VCM driver 34 supplies the drive current required for the VCM 14 to realize the first stage positioning of the magnetic head 11. Moreover, the MA driver 35 supplies the voltage required for the MA 15 to realize the second stage positioning of the magnetic head 11. The fact that the magnetic head 11 is located on the magnetic disk 10 means that the magnetic head 11 is located above the magnetic disk 10 with a minute space in between.

In a state where the position information is not read by the magnetic head 11, such as when the magnetic head 11 is located outside the outer periphery of the magnetic disk 10, the MPU 22 does not rely on the position information, and the VCM driver 34 and MA The driver 35 can be controlled. For example, when the magnetic head 11 is moved from the retracted position in the lamp unit 17 onto the magnetic disk 10, the MPU 22 outputs a signal to the driver IC 30 instructing the VCM 14 to supply a predetermined drive current suitable for the movement. As a result, the VCM driver 34 supplies the VCM 14 with a predetermined drive current based on the signal. Since precise position control of the magnetic head 11 is not required when the position information is not read by the magnetic head 11, the supply voltage to the pair of piezoelectric elements 15 may be zero or a fixed voltage. good.

FIG. 4 shows the internal configurations of the SPM 13 and the SPM driver 33 and their connection relationships. External terminals provided in the driver IC 30 include terminals OUTu, OUTv, OUTw and TM _CT . The SPM 13 is a three-phase brushless DC motor including a star-connected U-phase coil 13u, a V-phase coil 13v, and a W-phase coil 13w. The SPM 13 has a stator and a rotor with a permanent magnet, and the stator is provided with coils 13u, 13v and 13w. One end of the coil 13u, one end of the coil 13v, and one end of the coil 13w are connected to the external terminals OUTu, OUTv, and OUTw, respectively, and the other ends of the coils 13u, 13v, and 13w are commonly connected at the neutral point 13n. There is. The neutral point 13n is connected to the _{external terminal TM CT.} The external terminals OUTu, OUTv, and OUTw can also be referred to as output terminals. In the following description, when the term "rotor" is used, it means the rotor of SPM13. Further, the rotation of the SPM 13 means the rotation of the rotors constituting the SPM 13.

The SPM driver 33 includes a U-phase half-bridge circuit 50u, a V-phase half-bridge circuit 50v, a W-phase half-bridge circuit 50w, a pre-driver circuit 51, a BEMF comparator section 52, and a drive control section 100. The SPM 13 is sensorlessly driven by a window drive system or a windowless drive system. At this time, the SPM driver 33 may drive the SPM 13 by a 180-degree energization method (sine wave drive). BEMF is an abbreviation for "back electromotive force".

Each of the half-bridge circuits 50u, 50v and 50w consists of a high-side transistor TrH and a low-side transistor TrL connected in series between the line to which the power supply voltage VPWR is applied and the ground. The transistors TrH and TrL are configured as N-channel MOSFETs. The power supply voltage VPWR is a predetermined positive DC voltage, and here, it is assumed to be 12 V (volt) as an example.

More specifically, in each of the half-bridge circuits 50u, 50v and 50w, the drain of the transistor TrH is connected to the first power supply terminal to which the power supply voltage VPWR is applied to receive the power supply voltage VPWR, and the transistor TrH receives the power supply voltage VPWR. The source and the drain of the transistor TrL are commonly connected at the node ND, and the source of the transistor TrL is connected to the ground functioning as a second power supply terminal. The node NDs in the half-bridge circuits 50u, 50v, and 50w are connected to the output terminals OUTu, OUTv, and OUTw, respectively. Therefore, the node NDs in the half-bridge circuits 50u, 50v, 50w are connected to one end of the coils 13u, 13v, 13w via the output terminals OUTu, OUTv, OUTw, respectively. The voltages applied to the output terminals OUTu, OUTv, and OUTw, which correspond to the voltages at one ends of the coils 13u, 13v, and 13w, are represented by Vu, Vv, and Vw, respectively. The pre-driver circuit 51 and the half-bridge circuits 50u, 50v and 50w apply the voltages Vu, Vv and Vw to the output terminals OUTu, OUTv and OUTw, respectively. Further, representative of the voltage applied to the neutral point 13n in _{V CT.}

The currents flowing through the coils 13u, 13v, and 13w through the output terminals OUTu, OUTv, and OUTw are referred to as drive currents or coil currents, and are referred to by Iu, Iv, and Iw, respectively. Regarding the drive current Iu, the polarity of the drive current Iu flowing from the node ND of the half-bridge circuit 50u toward the coil 13u via the output terminal OUTu is defined as positive, and the opposite polarity is defined as negative. Polarities are similarly defined for the drive currents Iv and Iw.

The BEMF comparator unit 52 generates a comparison result signal CMPOUT by comparing at least one of the voltages Vu, Vv and Vw with the voltage V _CT, and outputs the comparison result signal to the drive control unit 100. The comparison result signal CMPOUT is one of the _{signal CMPOUTu indicating the magnitude relationship between the voltages Vu and V CT} , the signal CMPOUTv indicating the magnitude relationship between the voltages Vv and V _CT , and the signal CMPOUTw indicating the magnitude relationship between the voltages Vw and V _CT. Including the above signals. Here, it is assumed that at least the signal CMPOUTu is included in the comparison result signal CMPOUT. The terminal _{TM CT} is not essential, in the case where the terminal _{TM CT} is not present, the voltage Vu, the voltage obtained by synthesizing the Vv and Vw (voltage imitating the voltage _{V CT)} as a voltage _{V CT} It may be used to generate a comparison result signal CMPOUT.

In addition to the comparison result signal CMPOUT, the drive control unit 100 is supplied with a signal representing the voltages Vu, Vv and Vw or a signal corresponding to the voltages Vu, Vv and Vw, and further, the gate of each transistor in each half-bridge circuit. A signal corresponding to the voltage between the sources (expressed in Vgs in FIG. 4) is supplied. Based on these signals, the drive control unit 100 generates and outputs a drive control signal DRVu for the half-bridge circuit 50u, a drive control signal DRVv for the half-bridge circuit 50v, and a drive control signal DRVw for the half-bridge circuit 50w. ^{Further, a torque command signal Trq *} that specifies the torque to be generated in the SPM 13 is given from the MPU 22 to the drive control unit 100 via the IF circuit 32 (see FIG. 2), and the drive control unit 100 gives a torque command. Drive control signals DRVu, DRVv and DRVw are generated so that the torque specified by the signal Trq ^{* is generated in SPM13.} At this time, the drive control signals DRVu, DRVv and DRVw may be generated so that the sinusoidal current flows through the coils 13u, 13v and 13w with reference to the predetermined waveform data. Each of the drive control signals DRVu, DRVv, and DRVw is a binary signal having a variable pulse width, and has a high level or a low level.

The pre-driver circuit 51 controls the state of each half-bridge circuit by controlling the gate potential of each transistor in the half-bridge circuits 50u, 50v and 50w according to the drive control signals DRVu, DRVv and DRVw. As a result, the voltage obtained by switching the power supply voltage VPWR according to the drive control signals DRVu, DRVv and DRVw is added to the output terminals OUTu, OUTv and OUTw as the voltages Vu, Vv and Vw, and the SPM 13 is switched and driven. The gate signals of the transistors TrH and TrL of the half-bridge circuit 50u (voltage signals applied to the gate) are referred to by the symbols "GHu" and "GLu", respectively, and the gate signals of the transistors TrH and TrL of the half-bridge circuit 50v are referred to, respectively. References are made to the symbols "GHv" and "GLv", and the gate signals of the transistors TrH and TrL of the half-bridge circuit 50w are referred to by the symbols "GHw" and "GLw", respectively.

In the target half-bridge circuit, which is any one of the half-bridge circuits 50u, 50v, and 50w, the state in which the transistor TrH is on and the transistor TrL is off is referred to as an output high state, and the transistor TrH is The state in which the transistor TrL is off and the transistor TrL is on is referred to as an output low state. Assuming that the on-resistance of the transistors TrH and TrL is zero, for example, in the half-bridge circuit 50u, if the output is high, the power supply voltage VPWR is applied to the output terminal OUTu via the high side transistor TrH, and the output is low. For example, the ground potential is applied to the output terminal OUTu via the low-side transistor TrL (however, the transient state is ignored). The same applies to the half bridge circuits 50v and 50w.

The target half-bridge circuit may be in a high impedance state. The high impedance state in the target half-bridge circuit is a state in which both the transistors TrH and TrL of the target half-bridge circuit are turned off, whereby the current supply to the corresponding coil by the target half-bridge circuit is stopped. For example, when the half-bridge circuit 50u is put into a high impedance state, both the transistors TrH and TrL of the half-bridge circuit 50u are turned off, so that the energization of the coil 13u by the half-bridge circuit 50u is stopped. The same applies to the half bridge circuits 50v and 50w.

The drive control unit 100, the signal _{S BEMF} related back electromotive force generated in the coil of any one phase of the SPM 13 (e.g., the counter electromotive force of the zero-cross timing signal specifying a generated in the coil 13u) an IF circuit 32 ( It is output to the MPU 22 via (see FIG. 2). MPU22 is (can adjust the torque to be generated in other words SPM 13) which can be adjusted torque command signal Trq ^* on the basis of the signal _{S BEMF.} Signal _{S BEMF} is because it contains information of the rotational speed of the SPM 13 (details will be described later), by the drive control unit 100 and the MPU 22, so that the rotational speed control loop of the SPM 13 is formed.

The SPM driver 33 pays attention to a predetermined phase among the U phase, V phase, and W phase of the SPM 13, and can perform drive control of the SPM 13 by a window drive method based on the counter electromotive force generated in the coil of the predetermined phase. The drive control of the SPM 13 can be performed by a windowless drive method based on the drive current flowing through the coil of the predetermined phase and the drive voltage applied to the coil of the predetermined phase. In the following, performing drive control of the SPM 13 in the window drive system may be referred to as window drive, and performing drive control of the SPM 13 in the windowless drive system may be referred to as windowless drive. The predetermined phase may be any one phase among the U phase, V phase and W phase, or any two phases. All of the U phase, the V phase and the W phase may be predetermined phases. However, in the following, it is assumed that the predetermined phase is the U phase for the purpose of embodying the explanation.

FIG. 5 shows a waveform (smoothing waveform) of the back electromotive force BEMFu generated in the U-phase coil 13u due to the rotation of the rotor (the signals BZX1 and BZX2 shown in FIG. 5 will be described later). The counter electromotive force is sometimes referred to as the induced voltage. By putting the half-bridge circuit 50u in a high impedance state, the difference voltage (Vu-V _CT ) is observed as the back electromotive force BEMFu. The back electromotive force BEMFu is a sinusoidal voltage whose voltage value changes periodically, and the period of the back electromotive force BEMFu coincides with the rotation period at the electric angle of the rotor. Here, the counter electromotive force BEMFu becomes zero when the phases at the electrical angle of the rotor position are 0 ° and 180 °, and the counter electromotive force BEMFu has a negative extreme value when the phase is 90 °. Moreover, it is assumed that the counter electromotive force BEMFu takes a positive extreme value when the phase is 270 °.

In addition, the term "frame" will be introduced for the purpose of embodying the explanation. One frame is a section that starts when the rotor phase is 0 ° and ends just before the rotor phase reaches 360 ° (even if it is understood that it ends when the phase reaches 360 °). good). Then, a plurality of frames are arranged in succession in a time series, and each frame has the same length as the rotation period at the electric angle of the rotor. As shown in FIG. 6, the nth frame may be represented by "FL [n]" starting from an arbitrary and predetermined timing at which the rotor is rotating. n is an arbitrary natural number.

Although not particularly shown, the back electromotive force BEMFv generated in the coil 13v and the back electromotive force BEMFw generated in the coil 13w due to the rotation of the rotor also have the same period as the back electromotive force BEMFu and have a sinusoidal shape similar to the back electromotive force BEMFu. It becomes a voltage. However, the phases of the back electromotive forces BEMFv and BEMFw are delayed by 120 ° and 240 °, respectively, with respect to the back electromotive force BEMFu.

FIG. 7 shows the internal configuration of the drive control unit 100. The drive control unit 100 includes a window drive unit 110, a windowless drive unit 120, a signal processing unit 130, and a selector 140.

The window drive unit 110 is a functional block mainly for realizing window drive, and includes a counter electromotive force zero cross detection unit 111. In the window drive system, the first drive that detects the zero cross timing of the counter electromotive force BEMFu generated in the coil 13u in the window section in which the energization of the coil 13u is stopped and controls the drive of the SPM 13 based on the detected zero cross timing of the counter electromotive force BEM Fu. Corresponds to the method.

The comparison result signal CMPOUTu from the BEMF comparator unit 52 and the window signal WDW from the selector 133, which will be described later, are input to the counter electromotive force zero cross detection unit 111. The window signal WDW is a binary signal that takes a high level or a low level. The high-level section of the window signal WDW corresponds to the window section, and the low-level section of the window signal WDW does not belong to the window section (that is, outside the window section). In the window section, the half-bridge circuit 50u is in a high impedance state. Comparison result signal CMPOUTu as described above is a binary signal representative of the magnitude relationship between the voltage Vu and _{V CT.} Here, the signal CMPOUTu when _{"Vu> V CT"} goes high, the signal CMPOUTu when "Vu _{<V CT"} shall become a low level.

The counter electromotive force zero cross detection unit 111 detects the zero cross timing of the counter electromotive force BEMFu based on the comparison result signal CMPOUTu and the window signal WDW, and outputs the actually measured BEMF zero cross signal BZX1 representing the detected zero cross timing. The counter electromotive force zero cross detection unit 111 maintains the level of the signal BZX1 at a low level in principle, and sets the signal BZX1 to a high level for a short time each time it detects the zero cross timing of the counter electromotive force BEMFu (that is, a pulse to the signal BZX1). To generate). The zero cross timing of the counter electromotive force BEMFu to be detected may be the timing at which the counter electromotive force BEMFu switches from positive to negative, or the timing at which the counter electromotive force BEMFu switches from negative to positive. Then, the former timing is represented by the signal BZX1, and hereinafter, the zero cross timing of the counter electromotive force BEMFu refers to the timing at which the counter electromotive force BEMFu switches from positive to negative unless otherwise specified. Therefore, the counter electromotive force zero cross detection unit 111 performs only a minute time at the timing when the signal CMPOUTu switches from the high level to the low level in the window section (that is, the timing when the signal CMPOUTu switches from "Vu> V _CT " to "Vu <V _CT"). The signal BZX1 is set to a high level, and the level of the signal BZX1 is maintained at a low level except outside the window section (see FIG. 5).

The windowless drive unit 120 is a functional block mainly for realizing windowless drive, and includes a drive current zero cross detection unit 121, a phase control unit 122, and a signal generation unit 123. The windowless drive system corresponds to a second drive system that controls the drive of the SPM 13 based on the zero cross timing of the drive current Iu flowing through the coil 13u and the zero cross timing of the drive voltage Vu _{DRV applied to the coil 13u.} The drive voltage Vu _DRV is a voltage applied between both terminals of the coil 13u by the SPM driver 30 outside the window section, and corresponds to _{a difference voltage (Vu-V CT) outside the window section.} The zero cross timing of the drive voltage Vu _DRV is represented by the drive voltage zero cross signal DZX described later.

The drive current zero-cross detection unit 121 determines the zero-cross timing of the drive current Iu based on the voltage Vu at the output terminal OUTu and the gate-source voltage of the transistors TrH and TrL of the half-bridge circuit 50u (expressed by Vgsu in FIG. 7). It detects and generates and outputs a drive current zero cross signal CZX that represents the detection result.

FIG. 8 shows a configuration example for generating the drive current zero cross signal CZX. In the half-bridge circuit 50u, a parasitic diode whose forward direction is from the source to the drain is added to each of the transistors TrH and TrL (the same applies to the half-bridge circuits 50v and 50w). The SPM driver 33 is provided with sensors 61 to 63 as sensors for the half-bridge circuit 50u. The high-side off sensor 61 detects whether or not the transistor TrH is in the off state based on the level of the gate signal GHu of the transistor TrH and outputs a signal Sigma 61 indicating the detection result, and the low-side off sensor 62 is the transistor TrL. Based on the level of the gate signal GLu, it detects whether or not the transistor TrL is in the off state and outputs a signal Sigma 62 indicating the detection result, and the output sensor 63 compares the voltage Vu at the output terminal OUTu with a predetermined voltage and compares it. The signal Sigma 63 indicating the result is output. The drive current zero cross detection unit 121 of FIG. 8 determines the polarity of the drive current Iu based on the signals Sigma 61 to Sigma 63, detects the zero cross timing of the drive current Iu from the polarity reversal timing, and represents the detected zero cross timing. Output the signal CZX.

The drive current zero cross detection unit 121 maintains the level of the signal CZX at a low level in principle, and sets the signal CZX to a high level for a short time each time it detects the zero cross timing of the back electromotive force BEMFu (that is, a pulse is sent to the signal CZX). generate). The zero cross timing of the drive current Iu to be detected may be the timing at which the drive current Iu switches from positive to negative, or the timing at which the drive current Iu switches from negative to positive. It is assumed that the timing is represented by the signal CZX, and hereinafter, the zero cross timing of the drive current Iu refers to the timing at which the drive current Iu switches from positive to negative unless otherwise specified. Therefore, the drive current zero cross detection unit 121 keeps the signal CZX at a high level for a short time at the timing when the drive current Iu switches from positive to negative, and maintains the level of the signal CZX at a low level otherwise.

Many methods have been proposed as a method for determining the polarity of the drive current Iu, and any method may be used to determine the polarity of the drive current Iu. For example, as shown in Japanese Patent Application Laid-Open No. 10-341588, the polarity of the drive current Iu and the polarity reversal timing can be detected based on the voltage Vu when both the transistors TrH and TrL of the half-bridge circuit 50u are in the off state. You may do it. Alternatively, for example, the method shown in Japanese Patent No. 6231357 may be used.

The phase control unit 122 adjusts the drive frequency f when windowless drive is performed by determining (deriving) the drive state time DST based on the drive current zero cross signal CZX and the drive voltage zero cross signal DZX. The drive frequency f is the frequency of the voltage Vu, Vv or Vw, and represents the frequency of the _{voltage Vu (and thus the frequency of the drive voltage Vu DRV) if attention is paid to the coil 13u.} The drive frequency f corresponds to the reciprocal of the length of one frame. In windowless drive, the drive state time DST defines the length of the next frame. That is, when the windowless drive is being performed, the phase control unit 122 derives the drive state time DST based on the signals CZX and DZX obtained in the frame FL [i-1], and the derived drive is derived. The state time DST is set to the length of the next frame FL [i] (i is an integer). A windowless enable signal WLE is also input to the phase control unit 122. Details of the phase control unit 122 will be described later.

The signal generation unit 123 generates and outputs the estimated BEMF zero cross signal BZX2 based on the drive state time DST derived by the phase control unit 122. The estimated BEMF zero-cross signal BZX2 estimates the zero-cross timing of the counter electromotive force BEMFu based on the drive current zero-cross signal CZX and the drive voltage zero-cross signal DZX (that is, based on _{the respective zero-cross timings of the drive current Iu and the drive voltage Vu DRV).} Corresponds to. In windowless drive, in principle, the window section is not set, so the zero cross timing of the back electromotive force BEMFu is not actually measured (with exceptions), but since the back electromotive force BEMFu is synchronized with the _{drive current Iu and the drive voltage Vu DRV,} The zero cross timing of the back electromotive force BEMFu can be estimated based on each zero cross timing of the drive current Iu and the drive voltage Vu _DRV.

The signal generation unit 123 sets the signal BZX2 at a high level for a short time at the timing when the zero cross timing of the back electromotive force BEMFu is estimated to occur, and maintains the level of the signal BZX2 at a low level at other times (FIG. 5 shows an estimation error). It is assumed that there is no). It is assumed that the zero cross timing represented by the signal BZX2 estimates the timing at which the counter electromotive force BEMFu switches from positive to negative so as to be consistent with the signal BZX1. However, a modification is also possible so that the timing at which the counter electromotive force BEMFu switches from negative to positive can be estimated.

The selector 140 selects either the measured BEMF zero-cross signal BZX1 or the estimated BEMF zero-cross signal BZX2 based on the windowless enable signal WLE and the adjustment completion signal ADJ _{CMP , and sets the selected signal as the signal BZX SEL} in the signal processing unit 130. Send to. As shown in FIG. 9A, if the signal WLE is at a high level, the signal BZX2 is selected as the _{signal BZX SEL} regardless of the level of the _{signal ADJ CMP.} If both the signal WLE and the ADJ _CMP are low level, the signal BZX2 is selected as the _{signal BZX SEL.} If the signal WLE is low level and the signal ADJ _CMP is high level, the signal BZX1 is selected as the _{signal BZX SEL.} The initial level of the signal ADJ _{CMP is high.} The role of the signal ADJ _CMP will be described later. When the signal BZX1 is selected by the selector 140, the SPM13 is driven and controlled by the window drive method, and when the signal BZX2 is selected by the selector 140, the SPM13 is driven and controlled by the windowless drive method.

The signal processing unit 130 is a functional block that generates a drive clock signal DRVCLK, a window signal WDW, and the like based on the _{signal BZX SEL supplied from the selector 140.} By the function of the selector 140, a drive clock signal DRVCLK or the like is generated based on the signal BZX1 when the SPM13 is drive-controlled by the window drive method, and based on the signal BZX2 when the SPM13 is drive-controlled by the windowless drive method. The drive clock signal DRVCLK and the like will be generated. The signal processing unit 130 includes a drive clock signal generation unit 131, a window signal generation unit 132, a selector 133, a drive control signal generation unit 134, and a drive voltage zero cross detection unit 135.

The drive clock signal generation unit 131 generates the drive clock signal DRVCLK by multiplying the _{signal BZX SEL by m.} Here, it is assumed that m = 6. However, the value of m is not limited to 6.

The window signal generation unit 132 generates a window signal WDW'for setting a window section in synchronization with the drive clock signal DRVCLK. In each frame, the window signal WDW'is switched from low level to high level before the zero cross timing of the back electromotive force BEMFu arrives, and when the zero cross timing of the back electromotive force BEMFu is detected or estimated (ie, signal BZX). _It is returned to the low level (when an up edge occurs in the SEL). Therefore, the signal BZX _SEL may be referred to by the window signal generation unit 132. For example, the window signal generator 132, as shown in FIG. 10, based on the interval _{t INT} of the up-edge timing of the past signal _{BZX SEL,} estimates the zero-cross timing of the next back EMF BEMFu, from the estimated timing _{T EST} The window signal WDW'is switched from the low level to the high level at the timing before the predetermined time (k × t _INT). After that, when an up edge occurs in the signal BZX _SEL , the window signal WDW'is returned to the low level. k is a positive predetermined value less than 1 (eg 0.02).

The selector 133 receives the windowless enable signal WLE, outputs the window signal WDW'from the window signal generation unit 132 as it is as the window signal WDW so that the window section is actually set if the signal WLE is low level, and outputs the signal as it is. If the WLE is at a high level, the window signal WDW is fixed at a low level (see FIG. 9B). The high-level windowless enable signal WLE serves as a signal that permits or directs the execution of windowless drive. The low-level windowless enable signal WLE serves as a signal that prohibits the execution of windowless drive. Therefore, it can be said that the switching from the high level to the low level of the signal WLE functions as a first transition instruction signal indicating that the driving system of the SPM 13 should be switched from the windowless driving system to the window driving system. On the contrary, the switching from the low level to the high level of the signal WLE can be said to function as a second transition instruction signal indicating that the drive system of the SPM 13 should be switched from the window drive system to the windowless drive system.

With reference to FIG. 11, the SPM driver 33 is provided with a WLE generation unit 55 that generates and outputs a signal WLE. It may be understood that the WLE generation unit 55 is included in the components of the drive control unit 100. The initial level of the signal WLE is low level. For example, the WLE generator 55 may be able to determine the level of the signal WLE based on the signal from the MPU 22. Alternatively, for example, the WLE generation unit 55 may determine the level of the signal WLE based on the signal generated in the drive control unit 100. More specifically, for example, in the process in which the SPM 13 starts rotating under the instruction of the MPU 22 and the rotation speed of the SPM 13 rises toward a predetermined rotation speed, the signal WLE is set to a low level (initial level) and the rotation of the SPM 13 is performed. When the stable state in which the speed is stabilized at a constant speed is reached, the drive system of the SPM 13 is switched from the window drive system to the windowless drive system by switching the signal WLE from the low level to the high level. After that, for example, when a predetermined rotation stop instruction signal instructing the rotation stop of the SPM 13 from the MPU 22 is received by the SPM driver 33, the signal WLE is switched from the high level to the low level to return to the window drive system and window drive. The rotation speed of the SPM 13 is reduced toward zero by the method.

With reference to FIG. 7 again, the drive control signal generation unit 134 outputs to supply the sinusoidal drive currents Iu, Iv, Iw to the coils 13u, 13v and 13w based on the drive clock signal DRVCLK and predetermined waveform data. The drive control signals DRVu, DRVv, are obtained by obtaining the U-phase, V-phase, and W-phase target voltages to be applied to the terminals OUTu, OUTv, and OUTw, and pulse-width-modulating the signals indicating the U-phase, V-phase, and W-phase target voltages. Generate DRVw. At this time, the drive control signal generation unit 134 determines the amplitudes of the U-phase, V-phase, and W-phase target voltages based on ^{the torque command signal Trq *.} As a result, the U-phase, V-phase, and W-phase switching voltages, which are pulses width-modulated U-phase, V-phase, and W-phase target voltages, are added to the output terminals OUTu, OUTv, and OUTw through the pre-driver circuit 51, and the SPM13 The desired drive is achieved.

However, the window signal WDW from the selector 133 is input to the predriver circuit 51, and in the high level section (that is, the window section) of the window signal WDW, the half bridge circuit 50u is set to the high impedance state regardless of the drive control signal DRVu. The window. Alternatively, the window signal WDW may be input to the drive control signal generation unit 134 instead of the pre-driver circuit 51 so that the same operation as this is realized.

The drive voltage zero-cross detection unit 135 detects the zero-cross timing of the _{drive voltage Vu DRV} based on the drive clock signal DRVCLK, and generates a drive voltage zero-cross signal DZX representing the zero-cross timing of the _{drive voltage Vu DRV.} Zero-cross timing of the driving voltage Vu _DRV to be detected, to the driving voltage Vu _DRV may be a timing of switching from positive to negative, the driving voltage Vu _DRV may be positively switched timing from negative here in assumed the former timing is represented by the signal DZX, hereinafter, the zero-cross timing of the driving voltage Vu _DRV, unless specifically stated, is intended to refer to the timing of driving voltage Vu _DRV is switched from positive to negative. The drive voltage zero cross detection unit 135 sets the _{signal DZX at a high level for a short time at the timing when the drive voltage Vu DRV} switches from positive to negative, and maintains the level of the signal DZX at a low level otherwise.

In the signal processing unit 130, the U-phase, V-phase, and W-phase target voltages to be applied to the output terminals OUTu, OUTv, and OUTw are determined based on the drive clock signal DRVCLK. Therefore, naturally, the drive clock signal DRVCLK is used. The zero cross timing of the drive voltage Vu _{DRV can be obtained.} For example, by deriving the timing at which the duty of the drive control signal DRVu (the ratio of the high level section of the signal DRVu occupying one cycle of the signal DRVu) takes the median value of the variable range of the duty, the drive voltage Vu _DRV Zero cross timing may be specified. In this case, it may be understood that the detection unit 135 detects the zero cross timing of the _{drive voltage Vu DRV} based on the drive control signal DRVu.

In the drive control unit 100 according to the present embodiment, the window drive unit 110 and the windowless drive unit 120 always operate. That is, the operation of generating the signal BZX1 by the window drive unit 110 is executed not only when the window drive is performed but also when the windowless drive is performed (however, the window signal WDW is fixed at a low level). The signal BZX1 when it is being used does not have significant information). The operation of generating the signal BZX2 by the windowless drive unit 120 is executed not only when the windowless drive is performed but also when the window drive is performed.

[Window drive method]
FIG. 12 is a diagram showing the basic operation of the window drive system. In FIG. 12, waveforms of drive currents Iu, Iv and Iw, signals BZX _SEL , DRVCLK, WDW, GHu, GHv, GHw, GLu, GLv and GLw are shown in order from the top (FIGS. 4 and 7 are also shown as appropriate). reference). In window drive, "BZX _SEL = BZX1". In order to facilitate understanding of this figure, the vertical axis and the horizontal axis are appropriately enlarged or reduced, and each waveform is also appropriately simplified.

In the example of FIG. 12, the SPM 13 is driven by using the sinusoidal waveform data SIN so that the drive currents Iu, Iv, and Iw become sinusoidal currents shifted by 120 degrees from each other. In FIG. 12, Tp1 is _{the interval between adjacent up edges in the signal BZX SEL} and corresponds to the interval between adjacent zero cross timings in the back electromotive force BEMFu.

The drive clock signal DRVCLK is _{generated by multiplying the signal BZX SEL} by m (here, “m = 6”), and in the example of FIG. 12, the drive clock signal DRVCLK is pulsed (up) with a cycle of “Tp2 = Tp1 / m”. Edge) is occurring. Further, the above-mentioned waveform data SIN is generated in synchronization with the drive clock signal DRVCLK. Therefore, the drive currents Iu, Iv and Iw are controlled in synchronization with the _{signal BZX SEL.} As shown in the figure, the drive clock signal DRVCLK may be given a predetermined delay Td with respect _{to the signal BZX SEL.} By adjusting this delay Td, it is possible to optimize the drive of the SPM 13.

The gate signals GHu, GHv, GHw, GLu, GLv and GLw are generated in synchronization with the drive clock signal DRVCLK. In the half-bridge circuit 50u, if the gate signal GHu is high level and low level, the transistor TrH is in the on state and off state, respectively, and if the gate signal GLu is high level and low level, the transistor TrL is in the on state, respectively. It goes off. The same applies to the half bridge circuits 50v and 50w. Although not explicitly shown in FIG. 12, in the half-bridge circuits 50u, 50v, 50w, the actual gate signals of the transistors TrH and TrL are pulse width modulated so that the drive currents Iu, Iv and Iw are sinusoidal.

The window signal WDW is set to a high level before the zero cross timing of the back electromotive force BEMFu arrives. During the high level period of the window signal WDW (corresponding to the hatched region of FIG. 12), both the gate signals GHu and GLu are set to low levels by the drive control signal generation unit 134 or the predriver circuit 51, and the U-phase half bridge circuit 50u Is the output high impedance state. As a result, it becomes possible to observe the back electromotive force BEMFu. When the zero cross timing of the back electromotive force BEMFu arrives and an _{up edge occurs in the signal BZX SEL} , the window signal WDW is returned to the low level.

The window drive system cannot be used when the rotor is completely stopped. Therefore, when the SPM 13 is started, it is sufficient to first apply a certain amount of rotational force to the rotor by a known forced commutation method and then shift to the window drive method.

[Windowless drive system]
FIG. 13 is a diagram showing a configuration example of the phase control unit 122 included in the windowless drive unit 120. The phase control unit 122 of FIG. 13 includes an adder 122a, a subtractor 122b, a PI control unit 122c, and a target phase setting unit 122d.

The drive voltage zero cross signal DZX and the target phase TP_CD are input to the adder 122a. Since the driving voltage zero cross signal DZX represent zero-cross timing of the driving voltage _{Vu DRV,} it contains phase information of the drive voltage _{Vu DRV. The adder 122a adds the target phase TP_CD to the phase of the drive voltage Vu DRV} represented by the signal DZX, and outputs the phase of the addition result to the subtractor 122b.

In addition to the output of the adder 122a, a drive current zero cross signal CZX is input to the subtractor 122b. Since the drive current zero-cross signal CZX represents the zero-cross timing of the drive current Iu, it includes the phase information of the drive current Iu. The subtractor 122b derives the differential phase ERR_CD by subtracting the phase of the addition result output from the adder 122a from the phase of the drive current Iu.

The PI control unit 122c receives the input of the difference phase ERR_CD and derives the above-mentioned drive state time DST by performing proportional integral control to direct the difference phase ERR_CD to zero. However, this proportional integral control works effectively only when the windowless drive is performed. The proportional coefficient and the integral coefficient in the proportional integral control may be arbitrarily set based on the signal from the MPU 22.

The target phase setting unit 122d is a functional block for setting the target phase TP_CD input to the adder 122a, and includes a latch unit 122d_1, a fixed phase storage unit 122d_2, and a selector 122d_3.

The latch portion 122d_1 receives the input of the differential phase ERR_CD and the windowless enable signal WLE, and immediately before the transition at the transition from the window drive system to the windowless drive system, that is, at the timing when the signal WLE switches from the low level to the high level. Incorporates and retains the differential phase ERR_CD in. The initial holding phase of the latch portion 122d_1 may be zero. The significance of introducing the latch portion 122d_1 will be described later.

The fixed phase storage unit 122d_2 stores a fixed phase (for example, 0). The fixed phase may be arbitrarily set based on the signal from the MPU 22.

The selector 122d_3 selects either the phase held in the latch portion 122d_1 or the fixed phase stored in the fixed phase storage unit 122d_1 according to the target phase selection signal TSEL, and outputs the selected phase as the target phase TP_CD. .. Here, the selector 122d_3 selects and outputs the phase (ERR_CD) held in the latch portion 122d_1 when the signal TSEL is high level, and is fixed stored in the fixed phase storage unit 122d_2 when the signal TSEL is low level. The phase shall be selected and output. The level of the target phase selection signal TSEL may be determined based on the signal from the MPU 22.

As described above, since the target phase setting unit 122d includes the fixed value storage unit 122d_2 and the selector 122d_3 in addition to the latch unit 122d_1, it is possible to select the fixed phase as the target phase TP_CD.

FIG. 14 is a diagram showing the basic operation of the windowless drive system. On the left side of FIG. 14, the relationship between the rotational speed RPM of the SPM 13 and the differential phase ERR_CD is shown on the assumption that ^{the torque command signal Trq * is fixed.} On the right side of FIG. 14, under the assumption that the target phase TP_CD is zero, the countercurrent power BEMFu in each of the case of "ERR_CD>0", the case of "ERR_CD = 0", and the case of "ERR_CD <0" The waveforms (smooth waveforms) of the drive current Iu (corresponding to the dashed line waveform), the drive voltage Vu _{DRV (corresponding to the alternate long and short dash line waveform) are shown.}

Assuming that the target phase TP_CD is zero
When the zero cross timing of the drive current Iu is earlier than the zero _{cross timing of the drive voltage Vu DRV} (that is, when the phase of the drive current Iu is advanced when viewed from the phase of the _{drive voltage Vu DRV), “ERR_CD> 0” is obtained.}
When the zero cross timing of the drive current Iu is later than the zero _{cross timing of the drive voltage Vu DRV} (that is, when the phase of the drive current Iu is delayed when viewed from the phase of the _{drive voltage Vu DRV), "ERR_CD <0" is obtained.}
When the zero cross timing of the drive current Iu _{matches the zero cross timing of the drive voltage Vu DRV} (that is, when _{the phase of the drive voltage Vu DRV} matches the phase of the drive current Iu), “ERR_CD = 0”. ..

In the windowless drive system, when "ERR_CD> 0", the rotation speed RPM of the SPM 13 is lowered by lowering the drive frequency f (that is, by increasing the drive state time DST), and conversely, "ERR_CD <0". When ", the rotation speed RPM of the SPM 13 is increased by increasing the drive frequency f (that is, by decreasing the drive state time DST).

As described above, in the windowless drive system, the differential phase ERR_CD is driven to be zero, that is, the differential phase between the zero cross timing of the drive current Iu and the zero cross timing of the drive voltage Vu _DRV is driven to match the target phase TP_CD. The frequency f is adjusted, thereby optimizing the rotational speed RPM of the SPM 13. If the rotation speed RPM is too high, step-out of the SPM 13 is likely to occur, and if the rotation speed RPM is too low, the driving efficiency of the SPM 13 decreases. The difference phase between the zero-cross timing of the drive current Iu and the zero-cross timing of the drive voltage Vu _DRV is a quantity expressing the time difference between the two zero-cross timings in phase units, in other words, the phase of the drive current Iu. a differential phase between the drive voltage _{Vu DRV} phase, where is the phase of the drive current Iu seen from the phase of the drive voltage _{Vu DRV.}

In the windowless drive system, the estimated BEMF zero-cross signal BZX2 is generated after adjusting the drive frequency f as described above. Therefore, the phase control unit 122 and the signal generation unit 123 have the zero-cross timing of the drive current Iu and the drive voltage Vu _DRV. Under the assumption that the difference phase from the zero cross timing of the above matches the target phase TP_CD, the zero cross timing of the counter electromotive force BEMFu is estimated based on the zero _{cross timing of the drive current Iu and the zero cross timing of the drive voltage Vu DRV, and the estimation result is obtained.} Can be said to be generated and output as the signal BZX2.

[Transition from window drive system to windowless drive system]
FIG. 15 is a diagram showing a transition sequence from the window drive system to the windowless drive system. At timing T _A1 Previously, and the signal ADJ _CMP signal WLE is not set to low level is a high level which is an initial level. Therefore, at the timing _{T A1} Previously, the selector 140 signal BZX1 is selected (see FIG. 7 and FIG. 9 (a)), the window rotational speed RPM by the drive control of SPM13 is performed by the drive system is desired target value Is maintained at. Further, at a predetermined timing before the timing T _A1, the target phase selection signal TSEL is switched from the low level to the high level. In the following description, unless otherwise specified, the signal TSEL is assumed to be fixed at a high level.

Even while the SPM 13 is driven and controlled by the window drive method, the difference phase ERR_CD (the phase corresponding to 10 μsec in the example of FIG. 15) is sequentially derived in the windowless drive unit 120. However, when the SPM 13 is driven and controlled by the window drive method, the SPM 13 is not actually driven and controlled based on the difference phase ERR_CD, so that the proportional integration control for directing the difference phase ERR_CD to zero does not function effectively.

At timing _{T A1,} up edge occurs in windowless enable signal WLE. As a result, a boundary timing _{T A1,} selects and outputs signal _{BZX SEL} of the selector 140 will be is switched from the signal BZX1 the signal BZX2, the driving method of SPM13 is switched to a window-less drive system from the window driving system. It is assumed that the phase error control unit 150 (see FIG. 16), which will be described later _{, switches the signal ADJ CMP} from the high level to the low level in synchronization with the up edge of the signal WLE. It is desirable that the signal WLE is switched to a high level after the rotation speed RPM of the SPM 13 is stabilized by the window drive method.

By performing the transition from the window drive system to the windowless drive system in this way, stable operation is ensured immediately after the SPM 13 is started (advantage of the window drive system), and noise reduction and vibration suppression (windowless drive) during steady operation are performed. It is possible to achieve both of the advantages of the method).

By the way, in general, the difference phase ERR_CD immediately before the transition from the window drive system to the windowless drive system fluctuates due to various factors (driving state of SPM13, manufacturing variation, etc.). Therefore, when the target phase TP_CD is a fixed value (fixed phase), the drive control of the SPM 13 by the windowless drive method is started from the state where the difference phase ERR_CD and the target phase TP_CD are largely deviated from each other. There is a risk of unintended fluctuations in the rotational speed RPM.

On the other hand, in the present embodiment, when the target phase selection signal TSEL is at a high level, the differential phase ERR_CD (10 μ in the example of FIG. 15) derived immediately before the transition when transitioning from the window drive system to the windowless drive system is performed. The phase corresponding to seconds) is taken in by the latch portion 122d_1 and set as the target phase TP_CD.

Therefore, the drive control of the SPM 13 by the windowless drive system can be started from the state where the difference phase ERR_CD and the target phase TP_CD completely match, so that the transition from the window drive system to the windowless drive system can be smoothly performed. It becomes possible.

Focusing on the rotation speed RPM of the SPM 13, when the target phase TP_CD is a fixed value (fixed phase), as shown by the broken line 611 or 612 in FIG. 15, the window drive system is changed to the windowless drive system. With the transition, the rotation speed RPM deviates from the target speed. On the other hand, when the differential phase ERR_CD derived immediately before the transition is set as the target phase TP_CD, the rotation speed RPM is targeted even at the time of transition from the window drive method to the windowless drive method as shown by the solid line 610. It is possible to maintain the speed. The broken line 611 ^{corresponds to the situation where the torque command signal Trq *} is variably controlled, and the broken line 612 corresponds to the situation where the torque command signal Trq ^* is fixed.

[Transition from windowless drive system to window drive system]
FIG. 16 shows a phase error control unit 150 that functions effectively when transitioning from the windowless drive system to the window drive system. The phase error control unit 150 is provided in the drive control unit 100. It may be understood that the phase error control unit 150 is provided in the signal processing unit 130. The phase error control unit 150 includes a measured BEMF zero-cross signal BZX1 from the counter electromotive force zero-cross detection unit 111, an estimated BEMF zero-cross signal BZX2 from the signal generation unit 123 (see FIG. 7), and a windowless enable from the WLE generation unit 55. The signal WLE (FIG. 11) and is input. _{The adjustment completion signal ADJ CMP} is output from the phase error control unit 150. As described above, the initial level of the windowless enable signal WLE is low and the initial level of the adjustment completion signal ADJ _CMP is high.

FIG. 17 is a diagram showing a transition sequence from the windowless drive system to the window drive system. Timing _{T A2} shown in FIG. 17 is a timing later than the timing _{T A1} of FIG. 15, the timing _{T A3} is a timing after further than the timing _{T A2.} After the up-edge occurs in the signal WLE at the timing _{T A1} of FIG. 15, the signal WLE just before reaching the timing _{T A2} of FIG. 17 is maintained at a high level, a down edge signal WLE at a timing _{T A2} occurs To do. When a down edge occurs in the signal WLE, the phase error control unit 150 performs a predetermined adjustment operation BB based on the signals BZX1 and BZX2. The phase error control unit 150 _{maintains the signal ADJ CMP} at a low level until the adjustment operation BB is completed, and _{switches the signal ADJ CMP} to a high level when the adjustment operation BB is completed. In the example of FIG. 17, the adjustment operation BB is completed at _{the timing TA3.}

The timing _{T A1} of FIG. 15 to the timing _{T A2} in FIG. 17, the signal WLE is SPM13 is driven and controlled by windowless drive system because it is a high level. In between time T _A2 and T _A3 corresponds to the execution interval of adjustment operation BB, although the signal WLE is at a low level, the transition to the window driving system because the signal ADJ _CMP is at a low level is waiting, windowless drive The SPM 13 is driven and controlled by the method (see also FIG. 9A as appropriate). However, between the time _{T A2} and _{T A3, "WDW = WDW '} " becomes because the signal WLE is at low level, the SPM13 windowless drive system despite being controlled drive, window section in each frame Is set, and the counter electromotive force zero cross detection unit 111 detects the zero cross timing of the counter electromotive force BEMFu. Since the timing _{T A3,} since the signal WLE is low level and the signal _{ADJ CMP} becomes high level, SPM 13 at the window driving system is driven and controlled (see FIG. 9 (a) as appropriate).

The phase error control unit 150 of FIG. 16 derives the phase error ERR_BB based on the signals BZX1 and BZX2 in the above-mentioned adjustment operation BB, and operates so as to reduce the phase error ERR_BB. The phase error ERR_BB is a quantity having polarity as described later. Therefore, the reduction of the phase error ERR_BB means the reduction of the magnitude of the phase error ERR_BB. In fact, after the start of the adjusting operation BB, continuously perform the adjustment operation BB to the size of the phase error ERR_BB is less than or equal to a predetermined threshold value _{TH BB,} the magnitude of the phase error ERR_BB is less than or equal to a predetermined threshold value _{TH BB} The adjustment operation BB is completed to generate an up edge in the _{signal ADJ CMP.} The threshold value TH _BB may be variably set based on the signal from the MPU 22 (however, TH _BB > 0).

The signal BZX1 represents the zero cross timing of the counter electromotive force BEMFu detected by the window drive unit 110 (hereinafter, may also be referred to as the detection zero cross timing of the counter electromotive force BEMFu), while the signal BZX2 represents the windowless drive unit. It represents the zero cross timing of the back electromotive force BEMFu estimated by 120 (hereinafter, may be referred to as the estimated zero cross timing of the back electromotive force BEMFu). Therefore, both the signal BZX1 and the signal BZX2 include the phase information of the back electromotive force BEMFu. However, while the phase of the counter electromotive force BEMFu represented by the signal BZX1 is based on the actual measurement, the phase of the counter electromotive force BEMFu represented by the signal BZX2 is based on the estimation. Can cause errors.

The phase error ERR_BB is the phase error between the detection zero cross timing of the counter electromotive force BEMFu and the estimated zero cross timing of the counter electromotive force BEMFu, and the phase of the counter electromotive force BEMFu whose zero cross timing is defined by the signal BZX1 and the zero cross timing by the signal BZX2. Corresponds to the difference from the phase of the back electromotive force BEMFu specified. Here, as shown in FIGS. 18A and 18B, the back electromotive force BEMFu whose zero cross timing is defined by the signal BZX1 and the back electromotive force BEMFu whose zero cross timing is defined by the signal BZX2 are BEMFu1 and BEMFu2, respectively. See at. Further, the phase of the back electromotive force BEMFu1 and the phase of the back electromotive force BEMFu2 are referred to by P1 and P2, respectively. FIGS. 18A and 18B show waveforms (smooth waveforms) of the back electromotive forces BEMFu1 and BEMFu2 when “P1 ≠ P2”.

The phase error ERR_BB is represented by "(P1-P2)" or "(P2-P1)", but here, it is assumed that "ERR_BB = P2-P1". Therefore,
As shown in FIG. 18A, when the zero cross timing of the counter electromotive force BEMFu2 indicated by the signal BZX2 is earlier than the zero cross timing of the counter electromotive force BEMFu1 indicated by the signal BZX1 (that is, from the phase of the counter electromotive force BEMFu1). (When the phase of the counter electromotive force BEMFu2 is advanced), "ERR_BB>0", and
As shown in FIG. 18B, when the zero cross timing of the counter electromotive force BEMFu2 indicated by the signal BZX2 is later than the zero cross timing of the counter electromotive force BEMFu1 indicated by the signal BZX1 (that is, from the phase of the counter electromotive force BEMFu1). When the phase of the counter electromotive force BEMFu2 is delayed), it is assumed that "ERR_BB <0".

The phase error ERR_BB is determined by the rotation speed RPM of the SPM 13 and the time difference between the detected zero cross timing and the estimated zero cross timing of the counter electromotive force BEMFu. Therefore, in particular, for example, in the case where the rotation speed RPM when the adjustment operation BB is performed can be regarded as substantially constant, the phase error ERR_BB may be expressed in units of time. In this case, the phase error ERR_BB corresponds to the time difference between the detection zero cross timing of the counter electromotive force BEMFu and the estimated zero cross timing of the counter electromotive force BEMFu, and the above-mentioned threshold value TH _BB is also a value in units of time (for example, 1). Microseconds).

The reduction of the phase error ERR_BB in the adjustment operation BB is realized by adjusting the advance angle ADV. With reference to FIG. 19, the advance angle ADV represents the phase difference between the zero cross timing (estimated zero cross timing) of the back electromotive force BEMFu2 indicated by the signal BZX2 and the zero cross timing of the drive voltage Vu _{DRV indicated by the signal DZX.} .. The phase difference between the zero cross timing (estimated zero cross timing) of the back electromotive force BEMFu2 indicated by the signal BZX2 and the zero cross timing of the drive voltage Vu _DRV indicated by the signal DZX is the phase difference between the two zero cross timings. In other words, it is the difference phase between the phase of the back electromotive force BEMFu2 and the phase of the drive voltage Vu _DRV. Here, it is assumed that the advance angle ADV is the phase of the drive voltage Vu _DRV viewed from the phase of the counter electromotive force BEMFu2 (however, it can be modified to be the phase of the counter electromotive force BEMFu2 viewed from the phase of the _{drive voltage Vu DRV.} Is).

FIG. 20 shows a flowchart of the adjustment operation BB. In the adjustment operation BB, the phase error control unit 150 first refers to the signals BZX1 and BZX2 in step S21, and the latest phase based on the latest zero cross timing of the back electromotive force BEMFu1 and the latest zero cross timing of the back electromotive force BEMFu2. The error ERR_BB is derived. In the following step S22, the phase error control unit 150 compares the magnitude of the phase error ERR_BB derived in step S21 with the predetermined threshold value TH _BB, and if the magnitude of the phase error ERR_BB is equal to or less than the _{threshold value TH BB, performs processing.} The process proceeds to step S16, while the process proceeds to step S13 otherwise. In step S13, the polarity of the phase error ERR_BB is determined, and if "ERR_BB>0", the process proceeds to step S14, and if "ERR_BB <0", the process proceeds to step S15.

In step S14, the phase error control unit 150 reduces the advance angle ADV by a predetermined adjustment amount ΔADV (ΔADV> 0). That is, if the advance angle ADV in the frame FL [i-1] is "ADV [i-1]", the advance angle ADV in the frame FL [i] becomes "ADV [i-1] -ΔADV". As described above, _{the timing relationship (in other words, the phase relationship) between the signal BZX SEL} (signal BZX2 during the execution of the adjustment operation BB) and the drive clock signal DRVCLK is adjusted.

In step S15, the phase error control unit 150 increases the advance angle ADV by a predetermined adjustment amount ΔADV (here, “ΔADV> 0”). That is, if the advance angle ADV in the frame FL [i-1] is "ADV [i-1]", the advance angle ADV in the frame FL [i] becomes "ADV [i-1] + ΔADV". In addition, the timing relationship (in other words, the phase relationship) between the signal BZX _SEL (signal BZX2 during the execution of the adjustment operation BB) and the drive clock signal DRVCLK is adjusted.

The adjustment in steps S14 and S15 corresponds to adjusting the magnitude of the delay Td, paying attention to the delay Td as shown in FIG. After step S14 and after step S15, the process returns to step S11, and the processes after step S11 are repeated until step S16.

In step S16, the phase error control unit 150 _{switches the level of the adjustment completion signal ADJ CMP} from the low level to the high level to complete the adjustment operation BB.

An appropriate value is set for the adjustment amount ΔADV so that the back and forth between steps S14 and S15 does not occur in one adjustment operation BB (for example, “TH _BB >ΔADV> 0” or “ TH _BB >>ΔADV> 0 ").

The significance of the adjustment operation BB will be described with reference to FIG. FIG. 21 shows a transition sequence from the windowless drive system to the window drive system according to the reference method. In the reference method, when a down edge occurs in the windowless enable signal WLE, the transition from the windowless drive system to the window drive system is performed immediately without performing the adjustment operation BB. In FIG. 21, it is assumed that "WDW = WDW'" is always set and the zero cross timing of the counter electromotive force BEMFu is actually measured.

Now, it is assumed that the SPM 13 is rotating at a desired constant rotation speed RPM (= 1 / tp) in the windowless drive system, and a non-zero phase error ERR_BB exists. Then, when a down edge occurs in the signal WLE in the reference method and the windowless drive method is changed to the window drive method, _{the period of the up edge of the signal BZX SEL} changes sharply before and after the transition (change from tp to tp'). Corresponds to) Glitch occurs. Due to such a glitch, the rotation speed RPM may be controlled so as to actually temporarily fluctuate from the desired speed, or the required torque may not be obtained by the SPM 13. Further, sends the signal BZX1 itself or the signal driver controller 100 a signal as a signal _{S BEMF} based on BZX1 the MPU22 when performing window drive, a signal based on the signal BZX2 itself or signals BZX2 when doing a windowless drive The signal S _BEMF can be sent from the drive control unit 100 to the MPU 22 as a signal S BEMF (see FIG. 4), but in the reference method, since the signal S _BEMF including the glitch is transmitted to the MPU 22, the MPU 22 and the drive motion control unit The rotational speed control loop formed at 100 can become unstable.

On the other hand, in the configuration of the present embodiment, since the phase error ERR_BB is reduced as much as necessary before the transition to the window drive method is performed, the glitch as described above does not occur and the windowless drive method is used. It is possible to smoothly transition from to the window drive system.

In the configuration of the present embodiment, the difference phase ERR_CD immediately before the transition is set to the target phase TP_CD at the time of transition from the window drive system to the windowless drive system. Therefore, if it is assumed that all the conditions including the surrounding environment of the SPM 13 do not change after that, the subsequent phase error ERR_BB is expected to be maintained at zero, and the adjustment operation BB becomes unnecessary. However, in reality, a phase error ERR_BB often occurs during execution of the windowless drive due to a change in the ambient temperature of the SPM 13 or a change in the load of the SPM 13, and therefore, the above-mentioned adjustment operation BB functions beneficially. Of course, the above-mentioned adjustment operation BB is feasible and useful even in a configuration in which an operation such as setting the difference phase ERR_CD immediately before the transition to the target phase TP_CD is not performed at the time of transition from the window drive system to the windowless drive system. Works for.

The above-mentioned adjustment operation BB will be completed as long as the difference between the zero cross timing of the counter electromotive force BEMFu1 indicated by the signal BZX1 and the zero cross timing of the counter electromotive force BEMFu2 indicated by the signal BZX2 becomes small. At that time, in the actual SPM 13, it is uncertain whether the zero cross timing of the actual counter electromotive force BEMFu and the zero cross timing of the actual drive current Iu match or are close to each other. Therefore, after the adjustment operation BB is completed and the system shifts to the window drive method, the following adjustment operation BC may be performed following the adjustment operation BB. It may be understood that the adjustment operation BC is executed by the phase adjustment unit (not shown) provided in the signal processing unit 130 immediately after the transition of the window drive system.

In the adjustment operation BC, the phase error ERR_BC is derived based on the signals BZX1 and CZX, and the phase error ERR_BC is reduced toward zero. Like the phase error ERR_BB, the phase error ERR_BC has polarity. Therefore, the reduction of the phase error ERR_BC means the reduction of the magnitude (absolute value) of the phase error ERR_BC. In fact, after the start of the adjusting operation BC, continue executing the adjustment operation BC until the magnitude of the phase error ERR_BC is less than or equal to a predetermined threshold value _{TH BC,} the magnitude of the phase error ERR_BC is less than or equal to a predetermined threshold value _{TH BC} The adjustment operation BC is completed. The threshold value TH _BC may be variably set based on the signal from the MPU 22 (however, TH _BC > 0).

The phase error ERR_BC is the phase error between the zero cross timing of the counter electromotive force BEMFu indicated by the signal BZX1 and the zero cross timing of the drive current Iu indicated by the signal CZX, and the counter electromotive force whose zero cross timing is defined by the signal BZX1. It corresponds to the difference between the phase of BEMFu and the phase of the drive current Iu whose zero cross timing is defined by the signal CZX.

The reduction of the phase error ERR_BC by the adjustment operation BC is realized by adjusting the advance angle ADV in the same manner as the method of reducing the phase error ERR_BB by the adjustment operation BB. That is, in the adjustment operation BC, the magnitude of the phase error ERR_BC is equal greater the in than the predetermined threshold value _{TH BC,} until the magnitude of the phase error ERR_BC is less than or equal to a predetermined threshold value _{TH BC,} the phase error ERR_BC is reduced The advance angle ADV may be increased or decreased by a predetermined adjustment amount in the direction.

<< Second Embodiment >>
A second embodiment of the present invention will be described. The second embodiment and the third embodiment described later are the embodiments based on the first embodiment, and the matters not particularly described in the second and third embodiments are the first embodiment unless there is a contradiction. The description also applies to the second and third embodiments. In interpreting the description of the second embodiment, the description of the second embodiment may be prioritized for matters that conflict between the first and second embodiments (the same applies to the third embodiment described later). As long as there is no contradiction, any plurality of embodiments may be combined among the first to third embodiments.

In the second embodiment, the selector 133 shown in FIG. 7 performs a selection operation based on the windowless enable signal WLE and the window open signal OPEN as shown in FIG. 22 (a). The windowless enable signal WLE is generated by the WLE generation unit 55 also shown in FIG. The window open signal OPEN is generated by the OPEN generation unit 56. The OPEN generation unit 56 is provided in the drive control unit 100. Each of the signals WLE and OPEN is a binary signal with a low level or a high level.

As shown in FIGS. 22 (b) and 22 (c), the selector 133 according to the second embodiment is
When the signal WLE is low level, the window signal WDW'from the window signal generation unit 132 is output as it is as the window signal WDW regardless of the level of the signal OPEN.
When the signal WLE is high level and the signal OPEN is low level, the window signal WDW is fixed at low level.
When the signal WLE is at a high level and the signal OPEN is at a high level, the window signal WDW'from the window signal generation unit 132 is output as it is as the window signal WDW.
That is, even if the execution of the windowless drive is permitted or instructed by the high-level signal WLE and the windowless drive is actually being performed, the window section is set in the high-level section of the signal OPEN. Therefore, the zero cross timing of the counter electromotive force BEMFu is detected by the counter electromotive force zero cross detection unit 111.

The OPEN generation unit 56 sequentially determines the success or failure of a predetermined open condition in the high level section of the signal WLE, that is, in the execution section of the windowless drive, and when the open condition is satisfied, the signal OPEN is changed from the low level to the high level. Switching (see FIG. 22 (c)). The signal OPEN is maintained at a low level until the open condition is satisfied. After the open condition is satisfied, when the predetermined close condition is satisfied, the OPEN generation unit 56 switches the signal OPEN from the high level to the low level.

Therefore, in the drive control unit 100 according to the second embodiment, when the SPM 13 is driven and controlled by the windowless drive system, the drive system of the SPM 13 is changed to the windowless drive system when a predetermined open condition is satisfied. The window section will be set while being maintained. The same can be said for the first embodiment, and in the first embodiment, the occurrence of the down edge of the signal WLE corresponds to the establishment of the open condition. Then, between the time when the open condition is satisfied and the time when the close condition is satisfied, the drive control unit 100 according to the second embodiment uses the zero cross timing of the back electromotive force BEMFu detected by the back electromotive force zero cross detection unit 111. , The predetermined operation J can be performed (see FIG. 22 (c)).

The second embodiment includes the following Examples EX2_1 and EX2_2. The above description in the second embodiment applies to Examples EX2_1 and EX2_2 as long as there is no contradiction.

[Example EX2_1]
Example EX2_1 will be described. The predetermined operation J according to the embodiment EX2_1 is the adjustment operation BB described in the first embodiment. In Example EX2_1, it is assumed that the signal WLE is maintained at a high level during and before and after the adjustment operation BB as the predetermined operation J is executed.

Therefore, the phase error control unit 150 (see FIG. 16) according to the embodiment EX2_1 starts the above-mentioned adjustment operation BB in synchronization with the up edge of the signal OPEN regardless of the level of the signal WLE, thereby the above-mentioned adjustment operation BB. The phase error ERR_BB of is reduced. The content of the adjustment operation BB is as shown in the first embodiment, and the phase error ERR_BB may be reduced by adjusting the advance angle ADV. When the magnitude of the phase error ERR_BB _{becomes equal to or less than the predetermined threshold value TH BB} , the phase error control unit 150 completes the adjustment operation BB as the predetermined operation J. In Example EX2_1, the closing condition is satisfied when the magnitude of the phase error ERR_BB is equal to or less than the _{predetermined threshold value TH BB.} That is, the closing condition is satisfied when the adjustment operation BB as the predetermined operation J is completed. Therefore, when the adjustment operation BB as the predetermined operation J is completed, the SPM 13 is driven and controlled by the windowless drive method, and the window section is not set.

When the adjustment operation BB is executed as the predetermined operation J, _{a pulse in which the adjustment completion signal ADJ CMP} is set to a high level for a short time is generated when the adjustment operation BB is completed, and the pulse is generated by the OPEN generation unit. By transmitting to 56, the establishment of the closing condition is recognized by the OPEN generation unit 56.

By setting the differential phase ERR_CD immediately before the transition to the target phase TP_CD when transitioning from the window drive system to the windowless drive system, even if the transition to the windowless drive system is performed in an appropriate state, the ambient temperature after that The phase error ERR_BB may deviate from zero due to a change or a change in the load of the SPM 13. This can be a factor that causes a decrease in efficiency and step-out. According to the method of Example EX2_1, even when the windowless drive is continuously executed, the window section can be temporarily set to detect and reduce the phase error ERR_BB, and the SPM13 is appropriate. The drive will be maintained.

The open condition may be satisfied periodically at regular intervals when the windowless drive is performed. In this case, for example, a timer may be provided in the OPEN generation unit 56, and a trigger pulse indicating that the open condition is satisfied may be generated from the timer at regular intervals.

The open condition may be determined to be successful or unsuccessful based on the output of the sensor built in the driver IC 100 or externally connected.

The sensor here may be a temperature sensor that measures the temperature of the driver IC 100 or the temperature of the SPM 13, and in this case, the OPEN generation unit 56 can determine the success or failure of the open condition based on the temperature measurement value of the temperature sensor. More specifically, for example, when the drive system of the SPM 13 transitions from the window drive system to the windowless drive system, the OPEN generation unit 56 holds the temperature measurement value of the temperature sensor immediately after the transition as a reference value. After that, during the windowless drive, the latest temperature measurement value by the temperature sensor is compared with the reference value, and the difference between the latest temperature measurement value and the reference value is a predetermined judgment value (for example, 10 ° C.). When the above is reached, it may be determined that the open condition has been satisfied. In addition, after determining that the open condition is satisfied, it is advisable to update the reference value with the latest temperature measurement value. As a result, the open condition is satisfied each time a temperature change corresponding to a predetermined determination value occurs, and the phase error ERR_BB is reduced each time.

[Example EX2_2]
Example EX2_2 will be described. In the predetermined operation J, although the phase error ERR_BB is derived and checked, the phase error ERR_BB may not be reduced. This will be described. In the EX2_2 example, the signal WLE is maintained at a high level except for the case where the drive system of the SPM 13 is switched from the windowless drive system to the window drive system based on the phase error ERR_BB as described later. ..

In Example EX2_2, the phase error control unit 150 of FIG. 16 derives the phase error ERR_BB by the method shown in the first embodiment in response to the up edge of the signal OPEN regardless of the level of the signal WLE. .. The phase error ERR_BB derived here is particularly referred to as a determination phase error ERR_BB. The determination phase error ERR_BB is the phase error ERR_BB first derived in response to the up edge of the signal OPEN, and is the phase error ERR_BB in a state where the function of the phase error control unit 150 has not been reduced. When the determination phase error ERR_BB is derived, the signal WLE is at a high level and is being windowlessly driven.

The phase error control unit 150 compares the magnitude of the determination phase error ERR_BB with the predetermined value TH _LIM (0 <TH _BB <TH _LIM ).

The subsequent operation when the magnitude of the determination phase error ERR_BB is _{less than the predetermined value TH LIM} is the same as that of Example EX2_1. That is, if the magnitude of the determination phase error ERR_BB _{is less than the predetermined value TH LIM} , the phase error ERR_BB is reduced by adjusting the advance angle ADV, and the magnitude of the phase error ERR_BB is a predetermined threshold value, as in the case of the EX2_1 embodiment. When _{it becomes TH BB} or less, the adjustment operation BB as the predetermined operation J is completed. In this case, when the magnitude of the phase error ERR_BB is _{equal to or less than the predetermined threshold value TH BB} (that is, when the adjustment operation BB as the predetermined operation J is completed), the closing condition is satisfied, and the SPM 13 is operated by the windowless drive method. It returns to the state where the drive is controlled and the window section is not set.

On the other hand, when the magnitude of the determination phase error ERR_BB is equal to _{or larger than the predetermined value TH LIM} , the phase error control unit 150 does not reduce the phase error ERR_BB by the adjustment operation BB in the predetermined operation J without performing the adjustment operation BB. A predetermined phase error excessive signal is sent to the WLE generation unit 55 and the OPEN generation unit 56. When the OPEN generation unit 56 receives the phase error excessive signal, the closing condition is satisfied. On the other hand, when the WLE generation unit 55 receives the phase error excessive signal, the signal WLE is switched from the high level to the low level, so that the drive system of the SPM 13 is switched from the windowless drive system to the window drive system.

That is, the drive control unit 100 according to the embodiment EX2_2 derives the phase error ERR_BB between the detection zero cross timing of the counter electromotive force BEMFu and the estimated zero cross timing of the counter electromotive force BEMFu as the determination phase error ERR_BB in the predetermined operation J. Then, when the magnitude of the determination phase error ERR_BB is equal to _{or larger than the predetermined value TH LIM} , the drive method of the SPM 13 is switched from the windowless drive method to the window drive method. At this time, as shown in the first embodiment, the adjustment operation BB may be performed before switching to the window drive system. In Example EX2_2, the predetermined operation J may be understood to include a derivation operation of the determination phase error ERR_BB and an operation of switching from the windowless drive system to the window drive system that can be executed based on the determination phase error ERR_BB. However, it may be understood that only the derivation operation of the determination phase error ERR_BB is included.

When the magnitude of the determination phase error ERR_BB is equal to _{or larger than the predetermined value TH LIM} , it is presumed that the environmental change is large, and the drive in the windowless drive system may not be appropriate. Therefore, as described above, the window drive system is returned to give priority to the advantage of stable drive by the window drive system.

In Example EX2_2, the method of determining the success or failure of the open condition may be the same as in Example EX2_1.

<< Third Embodiment >>
A third embodiment of the present invention will be described.

In the first embodiment, the MPU 22 may be able to specify in advance to the drive control unit 100 whether or not to perform the adjustment operation BB when transitioning from the windowless drive system to the window drive system. The same applies to the adjustment operation BC. In the first embodiment, it is assumed that the adjustment operation BB should be specified in advance.

Regarding the configuration in which the drive control of the SPM 13 is performed using the counter electromotive force, the drive current, and the zero cross timing of the drive voltage of the predetermined phase, the U phase was focused on as the predetermined phase in the above description, but the predetermined phase is the V phase or the W phase. It may be a predetermined phase, or two or more of the U phase, the V phase and the W phase may be predetermined phases.

The drive control signal generation unit 134 (see FIG. 7) is designed to generate drive control signals (DRVu, DRVv, DRVw) with reference to the ^{torque command signal Trq *, but the torque to be generated by the SPM 13 is} In a predetermined case, the torque command signal Trq ^* may be unnecessary.

Although the example in which the SPM 13 is composed of the coils for three phases has been described above, the SPM 13 may be composed of coils for a plurality of phases different from the three phases.

Each component of the driver IC 30 is formed in the form of a semiconductor integrated circuit, and the semiconductor device is configured by enclosing the semiconductor integrated circuit in a housing (package) made of resin. However, a circuit equivalent to the circuit in the driver IC 30 may be configured by using a plurality of discrete components. Further, the semiconductor device may be configured by forming the SPM driver 33 alone in the form of a semiconductor integrated circuit and enclosing the semiconductor integrated circuit in a housing (package) made of resin.

In the above-described embodiment, an example of applying the present invention to the motor driver device (driver IC30) for the SPM 13 of the HDD device 1 is given, but any motor for sensorless driving a motor (particularly, a DC motor or a brushless DC motor) is given. The present invention can be widely applied to a driver device, for example, the present invention may be applied to a motor driver device for driving a fan motor for air cooling.

With respect to any signal or voltage indicating a logical value, the relationship between the high level and the low level may be reversed in a manner that does not impair the above-mentioned purpose (that is, whether the high level is assigned to the logical value “1” or the low level is assigned. Is optional).

Each half-bridge circuit may be modified so that the transistor TrH is composed of a P-channel MOSFET. It is also possible to make the transistor TrL a P-channel MOSFET.

Each of the above-mentioned transistors may be any kind of transistor. For example, the transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor in a manner that does not impair the above-mentioned purpose. Any transistor has a first electrode, a second electrode and a control electrode. In the FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In the IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is the base.

[Considerations relating to the present invention]
The present invention embodied in each of the above embodiments will be considered.

The motor driver device according to one aspect of the present invention is a motor driver device (for example, PM driver 33 or driver IC30) that switches and drives a DC motor (for example, SPM13), and stops energization of a coil of a predetermined phase of the DC motor. A first drive method (window) in which the zero cross timing (corresponding to BZX1) of the counter electromotive force generated in the coil of the predetermined phase is detected in the window section to be operated, and the drive control of the motor is performed based on the detection zero cross timing of the counter electromotive force. The motor is based on the zero cross timing of the drive current flowing through the coil of the predetermined phase (corresponding to CZX) and the zero cross timing of the drive voltage applied to the coil of the predetermined phase (corresponding to DZX). The second drive system (corresponding to the windowless drive system) that controls the drive of the motor is provided with a drive control unit (for example, 100) that controls the drive of the motor, and the drive control unit is the second drive system. Even when the drive control of the motor is being performed, the window section is set so that the zero cross timing of the countercurrent force can be detected.

Focusing on the technology of the first embodiment of the motor driver device (particularly, see FIG. 17), the drive control unit switches the drive system of the motor from the first drive system to the second drive system. After that, when a transition instruction signal (corresponding to switching from high level to low level of the signal WLE) indicating that the drive system of the motor should be switched from the second drive system to the first drive system is received, the motor is driven. While maintaining the method as the second drive method, the window section is set, a predetermined adjustment operation (corresponding to the adjustment operation BB) using the detection zero cross timing of the counter electromotive force is performed, and after the adjustment operation is completed, the adjustment operation is performed. It is preferable to shift the drive system of the motor from the second drive system to the first drive system.

Regarding the motor driver device (particularly, see FIG. 7), the drive control unit derives the back electromotive force detection zero cross timing (corresponding to BZX1) based on the voltage between both terminals of the coil in the window section. The reverse of the above by estimating the zero cross timing of the counter electromotive force based on the power zero cross detection unit (for example, 111), the zero cross timing of the drive current (corresponding to CZX), and the zero cross timing of the drive voltage (corresponding to DZX). The counter electromotive force zero cross estimation unit that derives the estimated electromotive force zero cross timing (corresponding to BZX2) and the counter electromotive force detection zero cross timing (corresponding to BZX1) when the motor drive control is performed by the first drive method. ), When the drive control of the motor is performed by the second drive method, the drive control signal (corresponding to BZX2) for the coils of each phase of the motor is based on the estimated zero cross timing of the counter electromotive force (corresponding to BZX2). The signal processing unit includes a signal processing unit (for example, 130) that generates a drive voltage zero-cross signal (corresponding to DZX) indicating the zero-cross timing of the drive voltage while generating DRVu, DRVu, and DRVw). The generated drive voltage zero cross signal is fed back to the counter electromotive force zero cross estimation unit and used for estimating the zero cross timing of the counter electromotive force.

Then, paying attention to the technique of the first embodiment (particularly, see FIGS. 16 and 20), the signal processing unit detects the counter electromotive force in the adjustment operation (corresponding to the adjustment operation BB) and zero cross timing (BZX1). The phase error (corresponding to ERR_BB) between the estimated zero cross timing of the counter electromotive force (corresponding to BZX2) can be reduced.

Regarding the configuration of FIG. 7, it can be considered that the above-mentioned counter electromotive force zero cross estimation unit is configured by the phase control unit 122 and the signal generation unit 123.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present invention, and the meanings of the terms of the present invention and the constituent requirements are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

1 HDD device 13 SPM (spindle motor)
13u, 13v, 13w coil 22 MPU
33 SPM driver 50u, 50v, 50w Half bridge circuit 51 Pre-driver circuit 52 BEMF comparator 100 Drive control unit 110 Window drive unit 120 Windowless drive unit 130 Signal processing unit

Claims (13)

A motor driver device that switches and drives a DC motor.
The zero cross timing of the counter electromotive force generated in the coil of the predetermined phase is detected in the window section for stopping the energization of the coil of the predetermined phase of the DC motor, and the drive control of the motor is performed based on the detection zero cross timing of the counter electromotive force. The first drive method to be performed, or the second drive method to control the drive of the motor based on the zero cross timing of the drive current flowing through the coil of the predetermined phase and the zero cross timing of the drive voltage applied to the coil of the predetermined phase. A drive control unit that controls the drive of the motor is provided.
The drive control unit is configured to be able to detect the zero cross timing of the counter electromotive force by setting the window section even when the drive control of the motor is performed by the second drive method. A featured motor driver device. The drive control unit should switch the drive system of the motor from the first drive system to the second drive system, and then switch the drive system of the motor from the second drive system to the first drive system. Upon receiving the indicated transition instruction signal, the window section is set while maintaining the drive system of the motor in the second drive system, and a predetermined adjustment operation using the detection zero cross timing of the counter electromotive force is performed to perform the adjustment. The motor driver device according to claim 1, wherein the drive system of the motor is changed from the second drive system to the first drive system after the operation is completed. The drive control unit
A counter electromotive force zero cross detection unit that derives the counter electromotive force detection zero cross timing based on the voltage between both terminals of the coil in the window section, and a counter electromotive force zero cross detection unit.
A counter electromotive force zero cross estimation unit that derives an estimated counter electromotive force zero cross timing by estimating the counter electromotive force zero cross timing based on the drive current zero cross timing and the drive voltage zero cross timing.
When the drive control of the motor is performed by the first drive method, the back electromotive force is estimated based on the detection zero cross timing of the counter electromotive force when the drive control of the motor is performed by the second drive method. A signal processing unit that generates a drive control signal for the coil of each phase of the motor based on the zero-cross timing and a drive voltage zero-cross signal indicating the zero-cross timing of the drive voltage is provided.
The drive voltage zero cross signal generated by the signal processing unit is fed back to the counter electromotive force zero cross estimation unit and used for estimating the zero cross timing of the counter electromotive force.
The motor driver device according to claim 2, wherein the signal processing unit reduces a phase error between the detection zero cross timing of the counter electromotive force and the estimated zero cross timing of the counter electromotive force in the adjustment operation. The signal processing unit is characterized in that the phase error is reduced by adjusting an advance angle which is a phase difference between the estimated zero cross timing of the counter electromotive force and the zero cross timing of the drive voltage in the adjustment operation. The motor driver device according to claim 3. The motor driver device according to claim 4, wherein in the signal processing unit, the adjustment operation is completed when the magnitude of the phase error becomes equal to or less than a predetermined threshold value. When a predetermined open condition is satisfied when the drive control unit is performing drive control of the motor by the second drive system, the drive control unit maintains the drive system of the motor in the second drive system. The motor driver device according to claim 1, wherein a window section is set to perform a predetermined operation using the detection zero cross timing of the counter electromotive force. The drive control unit
A counter electromotive force zero cross detection unit that derives the counter electromotive force detection zero cross timing based on the voltage between both terminals of the coil in the window section, and a counter electromotive force zero cross detection unit.
A counter electromotive force zero cross estimation unit that derives an estimated counter electromotive force zero cross timing by estimating the counter electromotive force zero cross timing based on the drive current zero cross timing and the drive voltage zero cross timing.
When the drive control of the motor is performed by the first drive method, the back electromotive force is estimated based on the detection zero cross timing of the counter electromotive force when the drive control of the motor is performed by the second drive method. A signal processing unit that generates a drive control signal for the coil of each phase of the motor based on the zero-cross timing and a drive voltage zero-cross signal indicating the zero-cross timing of the drive voltage is provided.
The drive voltage zero cross signal generated by the signal processing unit is fed back to the counter electromotive force zero cross estimation unit and used for estimating the zero cross timing of the counter electromotive force.
The motor driver device according to claim 6, wherein the signal processing unit reduces a phase error between the detection zero cross timing of the counter electromotive force and the estimated zero cross timing of the counter electromotive force in the predetermined operation. When the magnitude of the phase error becomes equal to or less than a predetermined threshold value, the drive control unit completes the predetermined operation, drives and controls the motor by the second drive method, and does not set the window section. The motor driver device according to claim 7, wherein the motor driver device returns to. The signal processing unit is characterized in that the phase error is reduced by adjusting an advance angle which is a phase difference between the estimated zero cross timing of the counter electromotive force and the zero cross timing of the drive voltage in the predetermined operation. The motor driver device according to claim 7 or 8. The drive control unit
A counter electromotive force zero cross detection unit that derives the counter electromotive force detection zero cross timing based on the voltage between both terminals of the coil in the window section, and a counter electromotive force zero cross detection unit.
A counter electromotive force zero cross estimation unit that derives an estimated counter electromotive force zero cross timing by estimating the counter electromotive force zero cross timing based on the drive current zero cross timing and the drive voltage zero cross timing.
When the drive control of the motor is performed by the first drive method, the back electromotive force is estimated based on the detection zero cross timing of the counter electromotive force when the drive control of the motor is performed by the second drive method. A signal processing unit that generates a drive control signal for the coil of each phase of the motor based on the zero-cross timing and a drive voltage zero-cross signal indicating the zero-cross timing of the drive voltage is provided.
The drive voltage zero cross signal generated by the signal processing unit is fed back to the counter electromotive force zero cross estimation unit and used for estimating the zero cross timing of the counter electromotive force.
The drive control unit derives a phase error between the detected zero cross timing of the counter electromotive force and the estimated zero cross timing of the counter electromotive force in the predetermined operation, and when the magnitude of the phase error is equal to or greater than a predetermined value, The motor driver device according to claim 6, wherein the drive system of the motor is switched from the second drive system to the first drive system. In the second drive system, the drive control unit performs drive control of the motor so that the difference phase between the zero cross timing of the drive current and the zero cross timing of the drive voltage matches a predetermined target phase. The motor driver device according to any one of claims 1 to 10. The motor driver device according to any one of claims 1 to 11, wherein the spindle motor for rotating the magnetic disk of the magnetic disk device is switched and driven as the DC motor. A semiconductor device that forms the motor driver device according to any one of claims 1 to 12.
The motor driver device is a semiconductor device characterized by being formed by using an integrated circuit.

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