JP2020129622A - Method for manufacturing semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a semiconductor device capable of reducing a chip defect rate.SOLUTION: An insulating film 12 is formed from a front surface of a semiconductor wafer 1 to an inner wall of a trench 11. Next, a polysilicon layer 20 is deposited on the insulating film 12 to fill the inside of the trench 11 with the polysilicon layer 20. Next, the polysilicon layer 20 is selectively removed so that a first gate portion 21 of the polysilicon layer 20 which will be a gate electrode 13 forming a trench gate structure is left inside the trench 11. At this time, the position of the upper end of the first gate portion 21 is set to be lower than an upper corner portion 11a of the trench 11 so that the upper corner portion 11a of the trench 11 is not covered with the polysilicon layer 20. In this state, a predetermined voltage is applied to the insulating film 12 via the first gate portion 21 to screen the insulating film 12. After that, remaining portions such as an interlayer insulating film, a front surface electrode and a back surface electrode are formed.SELECTED DRAWING: Figure 9

Description

The present invention relates to a method of manufacturing a semiconductor device.

Conventionally, a trench gate in which a MOS gate (insulated gate having a three-layer structure of metal-oxide film-semiconductor) is embedded in a trench (hereinafter referred to as a gate trench) formed in a semiconductor substrate (semiconductor chip) is provided. In the trench gate type semiconductor device, the reliability of the gate insulating film is evaluated by applying a predetermined voltage to the gate insulating film formed along the inner wall of the gate trench and observing the time-dependent breakdown phenomenon of the gate insulating film. It is known to perform a pressure resistance test (screening).

A conventional method of manufacturing a trench gate type semiconductor device will be described. FIG. 16 is a plan view showing a state in the middle of manufacturing a conventional semiconductor device. FIG. 17 is a cross-sectional view showing a cross-sectional structure taken along the section line AA-AA′ in FIG. 16. FIG. 16 shows a layout of the conventional trench gate type semiconductor device in the process of forming the trench gate 110 as seen from the front surface side of the semiconductor wafer 101. The trench gate 110 has a structure in which a gate electrode 113 is provided inside a gate trench 111 with a gate insulating film 112 interposed therebetween.

First, a predetermined semiconductor region (not shown) forming the element structure is formed on the front surface side of the semiconductor wafer 101. Next, the gate trench 111 having a predetermined depth is formed from the front surface of the semiconductor wafer 101. Next, the gate insulating film 112 is formed along the inner wall of the gate trench 111 and the front surface of the semiconductor wafer 101. Next, a polysilicon layer 120 to be the gate electrode 113 is deposited on the gate insulating film 112 so as to fill the inside of the gate trench 111. The polysilicon layer 120 is also deposited on the front surface of the semiconductor wafer 101.

Next, the polysilicon layer 120 is selectively removed by photolithography and etching to leave the portions of the polysilicon layer 120 to be the chip portion 121, the pad portion 122, and the connecting portion 123. The chip portion 121 of the polysilicon layer 120 is a portion of the polysilicon layer 120 that covers the entire surface of a region (hereinafter, referred to as a chip region) 102 that becomes a semiconductor chip after dicing (cutting) the semiconductor wafer 101. There are as many chip areas 102 as there are wafers 101.

The pad portion 122 of the polysilicon layer 120 is a portion of the polysilicon layer 120 that is used as an electrode pad (hereinafter referred to as a test pad) 103 for screening the gate insulating film 112. The pad portion 122 of the polysilicon layer 120 is provided for each chip region 102 and is arranged near the paired chip regions 102. The connecting portion 123 of the polysilicon layer 120 is a portion of the polysilicon layer 120 that connects the pair of chip portions 121 and the pad portion 122. The state up to this point is shown in FIGS.

Next, a probe is applied to the test pad 103, and a predetermined voltage is applied from the probe to the gate insulating film 112 between the chip portion 121 of the polysilicon layer 120 and the semiconductor wafer 101 via the test pad 103. .. Thus, the gate insulating films 112 on the inner walls of all the gate trenches 111 formed in the same chip region 102 of the polysilicon layer 120 covered by the chip portion 121 are simultaneously screened. The screening of the gate insulating film 112 is performed on all the chip regions 102 of the semiconductor wafer 101.

Next, the polysilicon layer 120 is etched back to remove the portion of the polysilicon layer 120 on the front surface of the semiconductor wafer 101. As a result, the polysilicon layer 120 to be the gate electrode 113 remains only inside the gate trench 111. Next, a front surface electrode and a back surface electrode are formed on both surfaces of the semiconductor wafer 101, respectively. After that, the semiconductor wafer 101 is diced (cut) along the scribe line 104 to complete the conventional trench gate type semiconductor device.

Further, as another method of manufacturing a conventional trench gate type semiconductor device, a gate electrode (hereinafter, referred to as a dummy gate electrode) connected to a potential other than the gate potential is an insulating film (hereinafter, referred to as a dummy gate insulating film). A method of manufacturing a trench gate type semiconductor device comprising a dummy trench gate embedded inside a trench (hereinafter, referred to as a dummy trench) via a gate insulating film screening, a dummy gate insulating film screening, There has been proposed a method of simultaneously performing (see, for example, Patent Documents 1 and 2 below).

JP, 2005-207736, A International Publication No. 2016/147529

However, in the above-described conventional method for manufacturing a semiconductor device (see FIGS. 16 and 17), the gate insulating film 112 is screened while the entire chip region 102 of the semiconductor wafer 101 is covered with the polysilicon layer 120. When the breakdown voltage of the portion of the gate insulating film 112 that covers the upper corner portion 111a of the gate trench 111 is low, the breakdown of the trench gate 110 near the upper corner portion 111a of the gate trench 111 (hereinafter , Gate breakdown) has occurred (see FIG. 15).

When the gate breakdown occurs in this manner, fragments of the polysilicon layer 120 and the gate insulating film 112 scatter around and adhere to a wide area within the front surface of the semiconductor wafer 101 to become a foreign substance. Therefore, not only the chip region 102 in which the gate breakdown has occurred, but also the other chip regions 102 of the same semiconductor wafer 101 may become defective due to the foreign matter. Further, fragments scattered from the semiconductor wafer 101 in which the gate is broken may adhere to another semiconductor wafer 101 via the manufacturing apparatus, and the chip defect rate may increase in the other semiconductor wafer 101 (contamination).

In the screening of the gate insulating film 112, when the gate current flowing from the semiconductor wafer 101 side toward the chip portion 121 (gate electrode 113) of the polysilicon layer 120 exceeds the reference value. The chip region 102 having the gate insulating film 112 is determined to be defective. However, if the chip region 102 originally determined to be defective in the screening is in an electrically open state (open state) in which no gate current flows, there is a problem that it is erroneously determined to be a good product. ..

In Patent Document 1, after forming all the element structures on the front surface side of the semiconductor wafer, screening is performed by applying a predetermined voltage to each of the gate insulating film and the dummy gate insulating film via different electrode pads and different gate runners. It is carried out. Therefore, the timing of evaluating the gate insulating film and the dummy gate insulating film is determined by the CR (capacitance/resistance) component difference generated between the electrode pad and the gate insulating film and between the electrode pad and the dummy gate insulating film. Therefore, there is a risk that the reliability of screening will be reduced.

In Patent Document 2, as in the above-described conventional method of manufacturing a semiconductor device (see FIGS. 16 and 17), during the manufacture of the element structure on the front surface side of the semiconductor wafer, the entire chip region of the semiconductor wafer is In a state of being covered with the polysilicon layer, a predetermined voltage is simultaneously applied to each insulating film between a portion of the polysilicon layer to be a gate electrode and a portion of the dummy gate electrode and the semiconductor wafer to screen the insulating film. It is carried out. Therefore, the same problem as in the conventional semiconductor device manufacturing method may occur during the screening of the insulating film.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing a chip defect rate in order to solve the above-mentioned problems of the conventional technique.

In order to solve the problems described above and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a trench gate structure, and has the following features. A first step of forming a predetermined semiconductor region forming the trench gate structure on the first main surface side of the semiconductor wafer is performed. A second step of forming a trench having a predetermined depth from the first main surface of the semiconductor wafer is performed. A third step of forming an insulating film from the first main surface of the semiconductor wafer to the inner wall of the trench is performed. A fourth step of depositing a conductor layer on the insulating film and filling the inside of the trench with the conductor layer is performed. A fifth step is performed in which the conductor layer is selectively removed, and a portion of the conductor layer that will be a gate electrode forming the trench gate structure is left inside the trench. A sixth step of performing a withstand voltage test by applying a predetermined voltage to the insulating film through the gate electrode is performed. After the sixth step, a seventh step of forming a first electrode electrically connected to the semiconductor region on the first main surface of the semiconductor wafer is performed. After the sixth step, an eighth step of forming a second electrode on the second main surface of the semiconductor wafer is performed. In the fifth step, the upper end of the gate electrode is located at a position lower than the upper corner of the trench.

Further, in the semiconductor device manufacturing method according to the present invention, in the above-described invention, the plurality of trenches are formed in the second step. In the fifth step, a portion of the conductor layer, which will be an electrode pad electrically connected to the gate electrode inside all the trenches, is left on a scribe line of the semiconductor wafer. In the sixth step, the predetermined voltage is applied to the insulating film through the electrode pad and the gate electrode.

In the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the trench gate structure includes a first trench gate structure that contributes to control of an element, and a second trench gate structure that does not contribute to control of the element. Have. After the sixth step and before the seventh step, a ninth step of selectively removing the remaining portion of the conductor layer is further performed. In the ninth step, the gate electrode is divided into a first gate electrode forming the first trench gate structure and a second gate electrode forming the second trench gate structure.

Further, in the semiconductor device manufacturing method according to the present invention, in the above-described invention, the plurality of trenches are formed in the second step. In the fifth step, a portion of the conductor layer, which will be a gate wiring layer connected to the gate electrodes inside all the trenches, is left. In the sixth step, the predetermined voltage is applied to the insulating film via the gate wiring layer and the gate electrode. In the ninth step, the connecting portion between the second gate electrode and the gate wiring layer is removed.

Also, in the method for manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, in the fifth step, a portion of the conductor layer that becomes an electrode pad connected to the gate wiring layer is formed into the gate wiring layer. And leave it on the scribe line of the semiconductor wafer. In the sixth step, the predetermined voltage is applied to the insulating film via the electrode pad, the gate wiring layer, and the gate electrode.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, in the fifth step, a position of an upper end of the gate electrode is set to a position lower than a curvature portion of a corner portion above the trench. Is characterized by.

In addition, in the method for manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, in the fifth step, the position of the upper end of the gate electrode is 0.1 μm or more and 0.5 μm or less from the first main surface of the semiconductor wafer. It is characterized by making the depth as low as possible.

According to the above-mentioned invention, since the upper corner portion of the trench is not covered with the polysilicon layer at the time of screening the insulating film, the upper corner portion of the trench of the insulating film is covered at the time of screening the insulating film (sixth step). No voltage is applied to the upper part. As a result, it is possible to suppress the scattering of foreign matter to the chip area other than the chip area where the gate breakdown has occurred, and to reduce the generation of foreign matter within the surface of the semiconductor wafer.

The method of manufacturing a semiconductor device according to the present invention has the effect of reducing the chip defect rate.

3 is a flowchart showing an outline of a method for manufacturing a semiconductor device according to the first embodiment. 3 is a plan view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 1; FIG. FIG. 3 is a sectional view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 1; FIG. 3 is a sectional view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 1; FIG. 3 is a sectional view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 1; 3 is a plan view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 1; FIG. 3 is a plan view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 1; FIG. 3 is a plan view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 1; FIG. FIG. 3 is a sectional view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 1; 3 is a plan view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 1; FIG. FIG. 9 is a plan view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 2; FIG. 12 is a cross-sectional view showing a cross-sectional structure taken along the section line D-D′ of FIG. 11. FIG. 9 is a plan view showing a condition partway through the manufacture of the semiconductor device according to Embodiment 2; It is a top view which shows the state in the middle of manufacture of an Example. It is a top view which shows the state in the middle of manufacture of a prior art example. It is a top view showing the state in the middle of manufacture of the conventional semiconductor device. FIG. 17 is a cross-sectional view showing a cross-sectional structure taken along the section line AA-AA′ in FIG. 16.

Hereinafter, preferred embodiments of a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, electrons or holes are the majority carriers in the layers or regions prefixed with n or p. Further, + and − attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region not attached thereto, respectively. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment 1)
A method of manufacturing a semiconductor device according to the first embodiment will be described by taking a trench gate type semiconductor device including a trench gate and a dummy trench gate as an example. FIG. 1 is a flowchart showing an outline of the method for manufacturing a semiconductor device according to the first embodiment. 2, 6 to 8 and 10 are plan views showing a state in which the semiconductor device according to the first embodiment is being manufactured. 3 to 5 and 9 are cross-sectional views showing a state in which the semiconductor device according to the first embodiment is being manufactured.

2 and 6 show layouts of the semiconductor wafer 1 viewed from the front surface (first main surface) side. In FIG. 6, the patterns of the first to third gate portions 21 to 23 and the second connecting portion 26 of the polysilicon layer 20 arranged in the same chip region 2 are not shown and are shown by one rectangular hatching. In FIG. 6, the pad portion 24 and the first connecting portion 25 of the polysilicon layer 20 are omitted from the drawing. 5 to 10, the polysilicon layer 20 is hatched (the same applies to FIGS. 11 to 15).

FIGS. 7, 8 and 10 show a state in which the trench gate 10 and the dummy trench gate 10 ′ (see FIG. 9) of the semiconductor device according to the first embodiment are in the process of being viewed from the front surface side of the semiconductor wafer 1. The layout is shown. FIG. 7 shows an enlarged view of the inside of the rectangular frame A of FIG. 8 and 10, the inside of the rectangular frame B of FIG. 7 is enlarged. 3 to 5 and 9 show the same portion of the semiconductor wafer 1 (a part of the chip region 2). FIG. 9 shows a cross-sectional structure taken along the section line C-C′ of FIG. 8.

The trench gate 10 has a structure in which a gate electrode 33a having a gate potential is provided inside the gate trench 31a via a gate insulating film 32a. The dummy trench gate 10' has a structure in which a dummy gate electrode 33b having a potential other than the gate potential (for example, an emitter potential) is provided inside the dummy trench 31b via a dummy gate insulating film 32b. The dummy trench gate 10 ′ may have the same size as the trench gate 10.

First, a predetermined semiconductor region (not shown) forming an element structure is formed on the front surface side of the semiconductor wafer 1 by a general method (step S1: first step). The predetermined semiconductor region is a plurality of p-type or n-type semiconductor regions arranged between trenches 11 (mesa regions) described later. A plurality of semiconductor regions arranged in these mesa regions form a trench gate structure having a channel (inversion layer) along the sidewall of the trench 11.

Specifically, for example, a semiconductor device is n-channel type IGBT according to the first embodiment: the case of (Insulated Gate Bipolar Transistor insulated gate bipolar transistor), the semiconductor wafer 1 the n ^- is the type, n ^- -type drift region Make up. The plurality of semiconductor regions forming the device structure are a p-type base region, an n ⁺ -type emitter region, and a p ⁺ -type contact region.

Predetermined semiconductor regions forming this element structure are formed in active regions of regions (chip regions) 2 that will become semiconductor chips after the dicing (cutting) of the semiconductor wafer 1. The chip area 2 of the semiconductor wafer 1 has, for example, a substantially rectangular planar shape, and is arranged in a matrix. The periphery of the chip region 2 is surrounded by the scribe line 4 (FIG. 2). The active region is a region in which the main current flows when the device is in the ON state.

Inside the chip region 2, the periphery of the active region is surrounded by the edge termination region. The edge termination region is a region between the active region and the end of the chip region 2 (end of the semiconductor chip), and is a region that relaxes the electric field on the front surface side of the semiconductor chip to maintain the breakdown voltage. .. In the edge termination region, for example, a pressure resistant structure such as a field limiting ring (FLR) or a field plate is arranged.

Next, as shown in FIG. 3, a plurality of trenches 11 having a predetermined depth from the front surface of the semiconductor wafer 1 are formed in the chip region 2 of the semiconductor wafer 1 by photolithography and etching (step S2: first). 2 steps). In step S2, the upper corner portion 11a of the trench 11 is rounded into an arc shape having a predetermined curvature. The upper corner portion 11 a of the trench 11 is a boundary between the front surface of the semiconductor wafer 1 and the sidewall of the trench 11.

The plurality of trenches 11 are, for example, arranged in a stripe shape extending in a direction (hereinafter, referred to as a first direction) X parallel to the front surface of the semiconductor wafer 1. One or more of the plurality of trenches 11 are gate trenches 31a, and the remaining trenches 11 are dummy trenches 31b (see FIG. 8). The gate trench 31a extends in the first direction X in the same chip region 2 and reaches the edge termination region from the active region.

The gate trench 31a extends to the outside (the end portion side of the chip region 2) beyond the end portion of the dummy trench 31b. That is, the dummy trenches 31b terminate in the active region within the same chip region 2. The gate trenches 31a and the dummy trenches 31b are alternately and repeatedly arranged in a direction parallel to the front surface of the semiconductor wafer 1 and in a direction (hereinafter, referred to as a second direction) Y orthogonal to the first direction X. Good.

Next, as shown in FIG. 4, the inner wall of the trench 11 and the front surface of the semiconductor wafer 1 are, for example, thermally oxidized to form the insulating film 12 along the inner wall of the trench 11 and the front surface of the semiconductor wafer 1. It forms (step S3: 3rd process). The portion of the insulating film 12 formed along the inner wall of the gate trench 31a is the gate insulating film 32a, and the portion formed along the inner wall of the dummy trench 31b is the dummy gate insulating film 32b (see FIG. 8). ).

Next, as shown in FIG. 5, a polysilicon (poly-Si) layer 20 is deposited as a conductor layer to be the gate electrode 13 on the insulating film 12 so as to fill the inside of the trench 11 (step S4: Fourth step). This polysilicon layer 20 is also deposited on the front surface of the semiconductor wafer 1. Next, as shown in FIGS. 6 to 9, the polysilicon layer 20 is selectively removed by photolithography and etching and left only in a predetermined portion (step S5: fifth step).

The predetermined portions of the polysilicon layer 20 remaining in the process of step S5 are the first to third gate portions 21 to 23, the pad portion 24, and the first and second connecting portions 25 and 26. One set of the first to third gate portions 21 to 23 and the second connecting portion 26 is arranged in each chip region 2 of the semiconductor wafer 1 (FIG. 6). The first gate portion 21 of the polysilicon layer 20 is a portion of the polysilicon layer 20 inside the trench 11 and remains in the same pattern as the trench 11 (FIG. 7).

Further, the upper end of the first gate portion 21 of the polysilicon layer 20 is located below the curved portion of the upper corner portion 11a of the trench 11 (FIG. 9). The upper end of the first gate portion 21 of the polysilicon layer 20 is a portion that protrudes most upward along the sidewall of the trench 11. The depth d from the front surface of the semiconductor wafer 1 to the upper end of the first gate portion 21 of the polysilicon layer 20 is preferably in the range of 0.1 μm or more and 0.5 μm or less.

The depth d from the front surface of the semiconductor wafer 1 to the upper end of the first gate portion 21 of the polysilicon layer 20 is different in the surface of the semiconductor wafer 1, and becomes deeper toward the outer peripheral portion of the semiconductor wafer 1. ing. A portion of the first gate portion 21 of the polysilicon layer 20 in the gate trench 31a constitutes a gate electrode 33a, and a portion in the dummy trench 31b constitutes a dummy gate electrode 33b.

That is, in the process of step S5, the trench gate 10 in which the gate electrode 33a is embedded inside the gate trench 31a via the gate insulating film 32a is formed. A dummy trench gate 10' in which a dummy gate electrode 33b is embedded is formed inside the dummy trench 31b via a dummy gate insulating film 32b. In FIG. 9, the gate electrodes functioning as the gate electrode 33a or the dummy gate electrode 33b are collectively denoted by reference numeral 13.

The second gate portion 22 of the polysilicon layer 20 is a portion of the polysilicon layer 20, which is disposed in the edge termination region and surrounds the periphery of the active region (FIG. 7). The second gate portion 22 of the polysilicon layer 20 is provided on the front surface of the semiconductor wafer 1 via a field oxide film (not shown) and constitutes a gate runner (gate wiring layer). All the first gate portions 21 in the same chip region 2 are connected to the second gate portion 22 of the polysilicon layer 20.

The second gate portion 22 of the polysilicon layer 20 faces the end portion of the gate trench 31a (end portion of the trench 11) in the depth direction Z and is connected to the first gate portion 21 in the gate trench 31a. .. Since the second gate portion 22 does not face the end portion of the dummy trench 31b (end portion of the trench 11), the second gate portion 22 is connected to the first gate portion 21 in the dummy trench 31b by the second connecting portion 26. (FIG. 8). In FIG. 8, a fine broken line shows an end portion of the trench 11 extending below the second gate portion 22 (the same applies to FIG. 10).

The third gate portion 23 of the polysilicon layer 20 is, for example, a linear portion of the polysilicon layer 20 that passes through the center of the chip region 2 (FIG. 7). The third gate portion 23 of the polysilicon layer 20 is provided on the front surface of the semiconductor wafer 1 via a field oxide film (not shown) and constitutes a gate finger (gate wiring layer). Similar to the second gate portion 22, all the first gate portions 21 in the same chip region 2 are connected to the third gate portion 23 of the polysilicon layer 20.

That is, the third gate part 23 is connected to the end of the first gate part 21 inside the gate trench 31a in the depth direction Z, which is the other end of the first gate part 21 connected to the second gate part 22. ing. Although not shown, the third gate portion 23 is an end portion of the first gate portion 21 in the dummy trench 31b that is the other end of the first gate portion 21 connected to the second gate portion 22 by the second connecting portion 26. Is connected with.

The pad portion 24 of the polysilicon layer 20 is a portion of the polysilicon layer 20 that is used as an electrode pad (hereinafter referred to as a test pad) 3 for screening the insulating film 12 described later (FIG. 7). The pad portion 24 of the polysilicon layer 20 is provided for each chip region 2 and is arranged near the paired chip region 2. The pad portion 24 of the polysilicon layer 20 is arranged on the scribe line 4.

The pad portion 24 of the polysilicon layer 20 is preferably arranged apart from the first to third gate portions 21 to 23 of the polysilicon layer 20 arranged along the outer periphery of the chip region 2. The reason is that when the probe is applied to the test pad 3 (the pad portion 24 of the polysilicon layer 20) in the process of step S6 described later, the first to third gate portions 21 to 21 of the polysilicon layer 20 of the chip region 2 are applied. This is because it is possible to prevent the probe 23 from being accidentally applied.

The pad portion 24 of the polysilicon layer 20 is located between the adjacent chip regions 2. Therefore, it is preferable that the distances from the adjacent chip regions 2 to the pad portions 24 are equal. The reason is the following two points. The first reason is that even if the pattern shift of the polysilicon layer 20 occurs during the process of step S5, the pad portion 24 comes into contact with the second gate portions 22 arranged in the adjacent chip regions 2, respectively. This is because it can be suppressed.

The second reason is that when the pad portion 24 of the polysilicon layer 20 is removed in the process of step S7 to be described later, even if a pattern shift of the etching mask occurs, it is arranged in each of the adjacent chip regions 2. This is because it is possible to prevent the width of the second gate portion 22 of the polysilicon layer 20 from being narrowed. Thereby, the gate runner constituted by the second gate portion 22 of the polysilicon layer 20 can be formed with high dimensional accuracy.

The first connection part 25 of the polysilicon layer 20 is a part of the polysilicon layer 20 that connects the pad part 24 and the second gate part 22 arranged in the chip region 2 paired with the pad part 24. And is located on the scribe line 4. The second connection portion 26 of the polysilicon layer 20 extends, for example, in a straight line from the end of the dummy trench 31b to the second gate portion 22 side, and the second gate portion 22 and the first gate portion 21 in the dummy trench 31b. And are connected.

Next, for each chip region 2 of the semiconductor wafer 1, a predetermined voltage is applied to the insulating film 12 to observe the time-dependent breakdown phenomenon of the insulating film 12 to confirm the leak current of the insulating film 12 and confirm the leakage current of the insulating film 12. A withstand voltage test (screening) for evaluating reliability is performed (step S6: sixth step). Specifically, a probe (not shown) is applied to the test pad 3, and a predetermined voltage is applied from the probe to the insulating film 12 between the polysilicon layer 20 and the semiconductor wafer 1 via the test pad 3. To do.

The test pad 3 (pad portion 24 of the polysilicon layer 20) is formed in the same chip region 2 via the first connecting portion 25 and the second and third gate portions 22 and 23 of the polysilicon layer 20. The first gate portions 21 of the polysilicon layer 20 in all the trenches 11 are connected. Therefore, in the process of step S6, it is possible to simultaneously screen the insulating films 12 on the inner walls of all the trenches 11 formed in the same chip region 2.

That is, in the process of step S6, the gate insulating film 32a formed of the insulating film 12 in the gate trench 31a and the dummy trench 31b are formed in the same chip region 2 with the same polysilicon layer 20 interposed therebetween. A predetermined voltage can be applied simultaneously to the dummy gate insulating film 32b composed of the insulating film 12. Therefore, the gate insulating film 32a and the dummy gate insulating film 32b can be evaluated at the same timing.

In addition, since the upper corner portion 11a of the trench 11 is not covered with the polysilicon layer 20 during the process of step S6, no voltage is applied to the portion of the insulating film 12 that covers the upper corner portion 11a of the trench 11. .. Therefore, during the processing of step S6, the trench gate 10 and the dummy trench gate 10' are not destroyed (gate destruction) in the upper corner portion 11a of the trench 11.

In the process of step S6, the upper corner portions 11a of the trench 11 are covered with the second and third gate portions 22 and 23 of the polysilicon layer 20 or the second connecting portion 26 at both ends of the trench 11 ( In portions other than both ends of the trench 11 (enclosed by a rough broken line in FIG. 8), the upper corner portion 11a of the trench 11 is not covered with the polysilicon layer 20 as described above.

Therefore, as compared with the conventional method (see FIGS. 16 and 17), the area of the portion where the upper corner portion 11a of the trench 11 is covered with the polysilicon layer 20 is extremely small with respect to the entire area of the chip region 2. You can Since the probability of occurrence of gate breakdown at the location where the upper corner portion 11a of the trench 11 is covered with the polysilicon layer 20 is equal in the plane of the chip region 2, the upper corner portion 11a of the trench 11 is covered with the polysilicon layer 20. By reducing the number of exposed portions, the probability of occurrence of gate breakdown with respect to the entire area of the chip region 2 can be reduced to, for example, about 1/10,000 as compared with the conventional method.

The result of the process of step S6 is held as electronic information, for example. For example, the screening result of the insulating film 12 of each chip area 2 in the surface of the semiconductor wafer 1 is used as the unique identification number of the semiconductor wafer 1 and the site information in which the position of each chip area 2 in the semiconductor wafer 1 is addressed. Based on this, it may be stored as electronic information in a storage unit (not shown) of the evaluation device for screening or an external storage unit (not shown).

Next, the second connection portion 26 of the polysilicon layer 20 is removed by photolithography and etching (step S7: ninth step). In the process of step S7, the second connecting portion 26 is formed so that the first gate portion 21 in the dummy trench 31b and the second and third gate portions 22 and 23 in the polysilicon layer 20 are separated. It can be cut. Therefore, at least part of the second connecting portion 26 may be removed in the process of step S7 (FIG. 10). In FIG. 10, the second connecting portion 26' after the process of step S7 is surrounded by a broken line.

In the process of step S7, by removing the second connecting portion 26 of the polysilicon layer 20, the first to third gate portions 21 to 23 of the polysilicon layer 20 can be left with high dimensional accuracy. By the process of step S7, the first gate portion 21 that becomes the gate electrode 33a in the gate trench 31a and the first gate portion 21 that becomes the dummy gate electrode 33b in the dummy trench 31b are separated. In the process of step S7, the pad portion 24 and the first connecting portion 25 of the polysilicon layer 20 may be further removed.

Next, an interlayer insulating film (not shown) is formed on the front surface of the semiconductor wafer 1 so as to cover the gate electrode 13 (step S8). Next, the interlayer insulating film is selectively removed to form a contact hole, and a predetermined semiconductor region (n ⁺ type emitter region and p ⁺ type contact region) is exposed in the contact hole. Next, a front surface electrode (first electrode) is formed on the front surface of the semiconductor wafer 1 so as to be embedded in the contact hole (step S9: seventh step).

In the process of step S9, a front surface electrode is formed for each chip region 2 of the semiconductor wafer 1 by forming and patterning a metal layer on the entire front surface of the semiconductor wafer 1. In the process of step S9, the dummy gate electrode 33b is electrically connected to a potential other than the gate potential in the same chip region 2 by electrically connecting the front surface electrode and all the dummy gate electrodes 33b, for example. Fixed to.

For example, the dummy gate electrode 33b may be connected to the front surface electrode by forming a contact hole exposing the end of the dummy gate electrode 33b and burying the front surface electrode in the contact hole. Further, a gate runner to which all the dummy gate electrodes 33b in the same chip region 2 are electrically connected is formed at a predetermined timing, and the dummy gate electrode 33b is connected to the front surface electrode via the gate runner. You may.

For example, when the semiconductor device according to the first embodiment is an n-channel IGBT, the front surface electrode is an emitter electrode. The front surface electrode may be, for example, an electrode containing aluminum (Al), may have a laminated structure of a barrier metal and an electrode containing aluminum, or may have a plating film on the outermost surface. You may have. The front surface electrode may have a structure in which a tungsten (W) plug is embedded in a contact hole, for example.

Next, a front surface protective film (not shown) is formed on the front surface of the semiconductor wafer 1 (step S10). Next, after forming a predetermined semiconductor region on the back surface (second main surface) side of the semiconductor wafer 1, a back surface electrode (second electrode) is formed (step S11: eighth step). For example, when the semiconductor device according to the first embodiment is an n-channel IGBT, the predetermined semiconductor region formed in the process of step S11 is a p ⁺ -type collector region or an n-type field stop region, and the back electrode is the collector electrode. Is.

Next, a general wafer inspection other than screening is performed on the semiconductor wafer 1 (step S12). In the process of step S12, as a wafer inspection, for example, a WAT (Wafer Acceptance Test) for evaluating whether or not the device normally operates by applying electricity is performed. Specifically, in the wafer inspection, the threshold voltage, the presence/absence of leakage current, the ON voltage, etc. may be evaluated.

In the process of step S12, after the wafer inspection, based on the electronic information stored in the storage unit in the screening of step S6 and the wafer inspection result, the chip region 2 determined to be non-defective and the chip region 2 determined to be defective. The chip area 2 is marked so that it can be distinguished from the chip area 2. For example, a predetermined mark such as a pattern, a character, or a bar code may be marked (added) on all the chip areas 2 determined to be defective.

Next, the semiconductor wafer 1 is diced (cut) along the scribe lines 4 to divide each chip region 2 into individual chips (step S13). In the process of step S13, the semiconductor chip including the chip region 2 (semiconductor device according to the first embodiment) is completed. At this time, the semiconductor chip formed of the chip region 2 determined to be defective in the screening in step S6 and the wafer inspection in step S12 is removed.

Specifically, for example, after dicing the semiconductor wafer 1, a semiconductor chip including a chip region 2 which is determined to be defective and has a predetermined mark is left as it is on a stage (stage on which the semiconductor wafer 1 is mounted during dicing). By picking up (removing) only a semiconductor chip (semiconductor chip not having a predetermined mark) formed of the chip area 2 which is determined to be a non-defective product, and carrying it to an assembly process for mounting the semiconductor chip in a package. Good.

Next, a general assembly process for mounting the semiconductor chip on the package is performed. Specifically, the back surface of the semiconductor chip is soldered (mounted) to an insulating substrate (not shown) such as a DCB (Direct Copper Bonding) substrate. As described above, since only the semiconductor chips determined to be non-defective are picked up, the semiconductor chips determined to be defective are not mounted on the DCB substrate.

After that, a wiring process is performed by connecting the front surface electrode and the emitter pad and connecting the emitter pad and the gate pad to predetermined electrode leads (not shown) by wire bonding or wireless bonding. At this time, since it is not necessary to perform the wiring process except for the semiconductor chip determined to be defective, the assembling process can be simplified. As described above, the package in which the semiconductor device according to the first embodiment is mounted is completed.

As described above, according to the first embodiment, after the polysilicon layer is buried inside the trench via the insulating film, the polysilicon layer on the upper corner portion of the trench is removed, and Then, the insulating film is screened. In the upper corner portion of the trench, the breakdown withstand voltage tends to be low due to the influence of a slight shape difference due to the curvature of the upper corner portion of the trench, but according to the first embodiment, during the screening of the insulating film. The upper corners of the trench are almost not covered with the polysilicon layer.

At the location where the upper corner of the trench is not covered with the polysilicon layer, no voltage is applied to the portion of the insulating film above the upper corner of the trench during the screening of the insulating film, so even if gate breakdown occurs. Therefore, it is possible to suppress the scattering of foreign matter to the chip area other than the chip area where the gate breakdown occurs. As a result, it is possible to reduce the generation of foreign matter within the surface of the semiconductor wafer, and thus it is possible to reduce the chip defect rate.

Further, according to the first embodiment, since the generation of foreign matter is reduced, the electrically defective chip region is prevented from being erroneously determined as a good product by screening. Further, in the trench gate type semiconductor device including the dummy trench gate, the dummy trench gate is electrically at the same potential as the emitter when the product is completed. For this reason, since it is not possible to apply a voltage to the dummy gate insulating film in the screening after the completion of the manufacturing process, the chip defect rate can be further reduced by performing the screening during the manufacturing as in the first embodiment. be able to.

Further, according to the first embodiment, since the polysilicon layer on the upper corner portion of the trench is a portion that does not contribute to the element operation, the element performance can be maintained even if it is removed. Further, according to the first embodiment, the test pad used when screening the insulating film is arranged on the scribe line of the semiconductor wafer. Therefore, the chip size does not increase. Further, it is possible to prevent the probe from being accidentally applied to the chip area when the probe is applied to the test pad.

Further, in Patent Document 1, the dummy gate electrode is set to the emitter potential by short-circuiting the test pad and the emitter pad with a bonding wire. Therefore, the dummy gate electrode does not have the same potential as the emitter potential due to the potential difference due to the resistance component between the test pad and the emitter pad, which adversely affects the product operation. In addition, the wire bonding process for short-circuiting the test pad and the emitter pad increases.

On the other hand, according to the first embodiment, after the dummy gate insulating film is screened, the emitter electrode can be brought into direct contact with the dummy gate electrode by a general emitter electrode (front surface electrode) forming process. The gate electrode can be completely set to the same potential as the emitter potential. Further, since no bonding wire is used to short-circuit the dummy gate electrode and the emitter electrode, no new bonding wire process is required.

Further, in Patent Document 1, the timing of evaluating the gate insulating film and the dummy gate insulating film is determined by the CR component differences generated between the electrode pad and the gate insulating film and between the electrode pad and the dummy gate insulating film. There is a risk that the reliability of the screening may be reduced due to the deviation of the screen. On the other hand, according to the first embodiment, it is possible to simultaneously apply a voltage to the gate insulating film and the dummy gate insulating film through the same polysilicon layer at the time of screening. Therefore, there is no difference in the evaluation timing of the gate insulating film and the dummy gate insulating film.

Further, in Patent Document 1, since the trenches of the gate electrode and the dummy gate electrode are completely filled, there is a possibility that the same problem as in the conventional method of manufacturing a semiconductor device (see FIGS. 16 and 17) may occur. On the other hand, according to the first embodiment, as described above, the insulating film is screened in a state where the upper corner portion of the trench is not covered with the polysilicon layer, which causes a problem in the conventional method for manufacturing a semiconductor device. Does not happen.

(Embodiment 2)
Next, the semiconductor device according to the second embodiment will be described. 11 and 13 are plan views showing a state in which the semiconductor device according to the second embodiment is being manufactured. FIG. 12 is a cross-sectional view showing the cross-sectional structure along the cutting line DD′ of FIG. 11. In the method of manufacturing a semiconductor device according to the second embodiment, the layout of the semiconductor wafer 1 in the process of manufacturing seen from the front surface side is the same as that of the first embodiment except that the layout of the trenches 11 is different (FIG. 2, FIG. 6, 7). 11 and 13 show the inside of the rectangular frame B in FIG. 7 in an enlarged manner. Reference numeral 29 is a field oxide film.

The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in the following two points. The first difference is that adjacent gate trenches 31a are arranged in a U-shape or an annular shape in which end portions are connected to each other. The second difference is that the dummy trenches 31b adjacent to each other are arranged in a U-shape or an annular shape with their ends connected to each other. In the semiconductor device according to the second embodiment, only one of the above two differences may be applied.

In the method of manufacturing the semiconductor device according to the second embodiment, the pattern of the etching mask used in steps S2, S5 and S7 in the method of manufacturing the semiconductor device according to the first embodiment (see FIG. 1) may be changed. In the etching process of step S2, the trench 11 to be the gate trench 31a is formed in a U shape or an annular shape in which end portions are connected. The trench 11 to be the dummy trench 31b is formed in a U shape or an annular shape in which the ends are connected to each other.

For example, the U-shaped or annular trench 11 serving as the gate trench 31a may be arranged so as to surround the U-shaped or annular trench 11 serving as the dummy trench 31b. The connecting portion between the end portions of the trench 11 serving as the gate trench 31a is located in the edge termination region in the depth direction Z so as to face a gate runner formed later. The connecting portion between the end portions of the trench 11 serving as the dummy trench 31b is located in the active region.

In the etching process of step S5, the first to third gate parts 21 to 23, the pad part 24 and the first to third connecting parts 25, 28 and 27 of the polysilicon layer 20 are left (FIGS. 7, 11 and 12). In the second embodiment, the first gate portion 21 of the polysilicon layer 20 remains in the same U-shaped or annular pattern as the trench 11. The arrangement of the second and third gate portions 22 and 23, the pad portion 24 and the first connecting portion 25 of the polysilicon layer 20 is the same as that of the first embodiment.

The second gate portion 22 of the polysilicon layer 20 is in contact with the first gate portion 21 at the connecting portion between the end portions of the gate trench 31a. The second and third connecting portions 28 and 27 of the polysilicon layer 20 are provided on the front surface of the semiconductor wafer 1 with the insulating film 12 interposed therebetween. The third connection portion 27 faces the connection portion between the end portions of the dummy trench 31b in the depth direction Z and is in contact with the first gate portion 21 in the dummy trench 31b. The second connecting portion 28 connects the first gate portion 21 and the second gate portion 22 in the dummy trench 31b via the third connecting portion 27.

In the etching process of step S7, the second connection portion 28 of the polysilicon layer 20 is removed. In the process of step S7, in the polysilicon layer 20, the second connecting portion 28 is formed so that the first gate portion 21 and the second and third gate portions 22 and 23 in the dummy trench 31b are separated. It suffices if at least a part is removed (FIG. 13). In FIG. 13, the second connecting portion 28' after the process of step S7 is surrounded by a broken line.

As described above, according to the second embodiment, even when the trench pattern is changed, the upper corner portion of the trench is reduced in the number of portions covered with the polysilicon layer, and thus the first embodiment is described. The same effect as can be obtained.

(Example)
Next, the state of the semiconductor wafer 1 when the gate breakdown occurs in the screening of the insulating film 12 will be described. FIG. 14 is a plan view showing a state in the middle of manufacturing the embodiment. FIG. 15 is a plan view showing a state in which the conventional example is being manufactured. 14 and 15 show regions having the same area on the front surface of the semiconductor wafer 1. The processes of steps S1 to S6 (see FIG. 1) were performed according to the method for manufacturing a semiconductor device according to the first embodiment described above (hereinafter, referred to as an example). FIG. 14 shows a state in which the gate breakdown has occurred in the embodiment as viewed from the front surface side of the semiconductor wafer 1.

The insulating film was screened according to the above-described conventional method for manufacturing a semiconductor device (see FIG. 16.17) (hereinafter, referred to as a conventional example). FIG. 15 shows a state in which a gate breakdown occurs in the conventional example as viewed from the front surface side of the semiconductor wafer 101. In the conventional example, the conditions were the same as those in the example except that the screening of the gate insulating film 112 and the dummy gate insulating film was performed with the entire surface of the chip region 102 of the semiconductor wafer 101 covered with the polysilicon layer 120.

From the results shown in FIG. 15, it was confirmed that when the gate breakdown occurred in the conventional example, the fragments of the polysilicon layer 120 and the gate insulating film 112 were scattered and attached to the surroundings to become foreign matters (indicated by reference numeral 42). Location). Although only a part of the chip area 102 of the semiconductor wafer 101 is shown in FIG. 15, it has been confirmed by the inventor that foreign matter scattered by the gate destruction adheres to a wide area within the front surface of the semiconductor wafer 101. .. Further, in the conventional example, the defective chip area 102 to which the foreign matter is attached may be electrically judged to be a good product at the time of screening.

On the other hand, as shown in FIG. 14, in the example, the part where the gate was destroyed was slightly scorched (the part shown by reference numeral 41), and it was confirmed that the damage due to the gate damage did not reach other chip regions 2. It was In addition, in the example, it was confirmed by screening that the defective chip area 2 to which a foreign substance had adhered was electrically determined to be defective.

In the above, the present invention is not limited to the above-described embodiments, but can be variously modified without departing from the spirit of the present invention. For example, each of the above-described embodiments can be applied to the case of manufacturing (manufacturing) a trench gate type semiconductor device having no dummy trench gate. Further, it may be applied to a trench gate type semiconductor device having no gate runner or gate finger. In this case, all the upper corner portions of the trench are not covered with the polysilicon layer during the process of step S6, so that the effect of the present invention can be further enhanced. Further, the present invention is similarly applicable even when the conductivity type (n type, p type) is reversed.

As described above, the method for manufacturing a semiconductor device according to the present invention is useful for a trench gate type semiconductor device used for a power converter, a power supply device for various industrial machines and the like.

1 semiconductor wafer 2 chip area of semiconductor wafer 3 electrode pad for screening (test pad)
4 semiconductor wafer scribe line 10 trench gate 10' dummy trench gate 11 trench 11a upper corner portion of trench 12 insulating film 13 gate electrode 20 polysilicon layer 21 first gate portion of polysilicon layer (gate electrode)
22 Polysilicon layer second gate (gate runner)
23 Third gate part (gate finger) of polysilicon layer
24 Polysilicon layer pad (test pad)
25 1st connection part 26, 26', 28, 28' of polysilicon layer 2nd connection part of polysilicon layer 27 3rd connection part of polysilicon layer 31a Gate trench 31b Dummy trench 32a Gate insulating film 32b Dummy gate insulating film 33a Gate electrode 33b Dummy gate electrode d Depth from front surface of semiconductor wafer to upper end of first gate portion of polysilicon layer X Direction parallel to front surface of semiconductor wafer (first direction)
Y A direction parallel to the front surface of the semiconductor wafer and orthogonal to the first direction (second direction)
Z depth direction

Claims (7)

A method of manufacturing a semiconductor device having a trench gate structure, comprising:
A first step of forming a predetermined semiconductor region forming the trench gate structure on the first main surface side of the semiconductor wafer;
A second step of forming a trench having a predetermined depth from the first main surface of the semiconductor wafer;
A third step of forming an insulating film from the first main surface of the semiconductor wafer to the inner wall of the trench;
A fourth step of depositing a conductor layer on the insulating film and filling the inside of the trench with the conductor layer;
A fifth step of selectively removing the conductor layer to leave a portion of the conductor layer, which will be a gate electrode forming the trench gate structure, inside the trench;
A sixth step of applying a predetermined voltage to the insulating film via the gate electrode to perform a withstand voltage test;
A seventh step of forming a first electrode electrically connected to the semiconductor region on the first main surface of the semiconductor wafer after the sixth step;
An eighth step of forming a second electrode on the second main surface of the semiconductor wafer after the sixth step,
Including,
In the fifth step, the position of the upper end of the gate electrode is lower than the upper corner portion of the trench. In the second step, a plurality of the trenches are formed,
In the fifth step, of the conductor layer, a portion to be an electrode pad electrically connected to the gate electrode inside all the trenches is left in a scribe line of the semiconductor wafer,
The method of manufacturing a semiconductor device according to claim 1, wherein in the sixth step, the predetermined voltage is applied to the insulating film via the electrode pad and the gate electrode. The trench gate structure is
A first trench gate structure that contributes to device control;
A second trench gate structure that does not contribute to control of the device,
After the sixth step and before the seventh step, the method further includes a ninth step of selectively removing the remaining portion of the conductor layer,
In the ninth step, the gate electrode is divided into a first gate electrode forming the first trench gate structure and a second gate electrode forming the second trench gate structure. Item 2. A method of manufacturing a semiconductor device according to item 1. In the second step, a plurality of the trenches are formed,
In the fifth step, of the conductor layer, a portion to be a gate wiring layer connected to the gate electrodes inside all the trenches is left,
In the sixth step, the predetermined voltage is applied to the insulating film via the gate wiring layer and the gate electrode,
4. The method of manufacturing a semiconductor device according to claim 3, wherein in the ninth step, the connecting portion between the second gate electrode and the gate wiring layer is removed. In the fifth step, a portion of the conductor layer, which will be an electrode pad connected to the gate wiring layer, is separated from the gate wiring layer and left on a scribe line of the semiconductor wafer,
The method of manufacturing a semiconductor device according to claim 4, wherein in the sixth step, the predetermined voltage is applied to the insulating film via the electrode pad, the gate wiring layer, and the gate electrode. 6. The semiconductor according to claim 1, wherein in the fifth step, a position of an upper end of the gate electrode is set to a position lower than a curvature portion of a corner portion above the trench. Device manufacturing method. 7. In the fifth step, the position of the upper end of the gate electrode is set to a depth lower than the first main surface of the semiconductor wafer by 0.1 μm or more and 0.5 μm or less. A method of manufacturing a semiconductor device according to any one of the above.

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