JP2020124078A - Charge pump circuit, semiconductor device, semiconductor memory device, and electric device - Google Patents

Abstract

To reduce the probability of occurrence of defects due to excessive voltage application.SOLUTION: In a charge pump circuit (10) including a plurality of rectifying elements (D[1] to D[n]) inserted in series between a voltage input terminal (151) and a voltage output terminal (152), and a plurality of capacitors (C[1] to C[n]) whose first end is connected between adjacent rectifying elements and which receives a clock signal in phase with or opposite to the reference clock signal (PCLK) at the second end, an amplitude reducing unit (MA, MB) is provided that makes the amplitude of the clock signal that is supplied to the target capacitors (C[n-1], C[n]) that are parts of the plurality of capacitors smaller than the amplitude of the clock signal supplied to non-target capacitors (C[1] to C[n-2]) different from the target capacitor.SELECTED DRAWING: Figure 3

Description

The present invention relates to a charge pump circuit, and a semiconductor device, a semiconductor memory device, and an electric device using the charge pump circuit.

FIG. 14 shows a Dickson type charge pump circuit 900 as an example of the charge pump circuit. The charge pump circuit 900 is incorporated in a semiconductor memory device such as an EEPROM (Electrically Erasable Programmable Read-Only Memory).

The charge pump circuit 900 includes a plurality of rectifying elements (here, diode-connected MOSFETs) inserted in series between a voltage input terminal 951 to which an input voltage Vi is applied and a voltage output terminal 952 to which an output voltage Vo is applied. A plurality of capacitors, one end of which is connected between the rectifying elements adjacent to each other and the other end of which is connected to one of the clock lines 961 and 962, and the clock signal CLK1 having the same phase as the reference clock signal. And a voltage driver circuit 910 for outputting a clock signal CLK2 having a phase opposite to that of the reference clock signal to the clock line 962, and a voltage detection circuit for generating an enable signal EN according to the level relationship between the output voltage Vo and a predetermined reference voltage. And 920.

When the output voltage Vo becomes equal to or higher than the reference voltage which is the target voltage of the output voltage Vo, the voltage detection circuit 920 outputs the enable signal EN having a logical value of “0” to the clock driver 910, and in response to this, the clock signal CLK1. And the output of CLK2 is stopped. After that, when the output voltage Vo falls below the reference voltage due to the power consumption of the load connected to the voltage output terminal 952, the output of the clock signals CLK1 and CLK2 is restarted through the generation of the enable signal EN having the logical value of "1". To be done. By repeating these operations, the output voltage Vo is stabilized near the reference voltage. The clock signals CLK1 and CLK2 have amplitudes corresponding to the magnitude of the power supply voltage supplied to the charge pump circuit 900, and the higher the power supply voltage, the shorter the output voltage Vo reaches the reference voltage.

FIG. 15 shows a schematic waveform of the output voltage Vo in the process of stabilizing the output voltage Vo in the vicinity of the reference voltage from the start of the boosting operation using the clock signals CLK1 and CLK2. In FIG. 15, a solid line waveform 971 represents a schematic waveform of the output voltage Vo when the power supply voltage of the charge pump circuit 900 is relatively low, and a broken line waveform 972 represents an output voltage Vo when the power supply voltage of the charge pump circuit 900 is relatively high. Shows a schematic waveform of. After the output voltage Vo reaches the reference voltage, the output voltage Vo is maintained near the reference voltage without depending on the power supply voltage. However, since the amplitudes of the clock signals CLK1 and CLK2 correspond to the power supply voltage, the peak value of the output voltage Vo increases as the power supply voltage increases. Not only the output voltage Vo, but the peak of the voltage applied to each rectifying element and each capacitor is formed at the rising edge of the clock signal.

JP, 2017-131069, A

As described above, when the clock signal rises, a relatively large voltage is momentarily applied to the corresponding elements (rectifying element and capacitor), but its peak value increases as the power supply voltage increases. On the other hand, if an excessive voltage is applied to the element, the element is likely to be defective (destructed or deteriorated). As a result, in the charge pump circuit 900 of FIG. 14, there is a possibility that the probability of occurrence of a defect increases when the power supply voltage is relatively high.

It is an object of the present invention to provide a charge pump circuit that contributes to reducing the probability of occurrence of defects, and a semiconductor device, a semiconductor memory device, and an electric device that use the charge pump circuit.

A charge pump circuit according to the present invention has a plurality of rectifying elements inserted in series between a voltage input terminal and a voltage output terminal, and a first terminal at a connection node between adjacent rectifying elements in the plurality of rectifying elements. A plurality of capacitors connected to each other and receiving a clock signal having the same phase or an opposite phase as the reference clock signal at the second end, and generating an output voltage higher than the voltage at the voltage input terminal at the voltage output terminal. In the charge pump circuit, the amplitude of the clock signal supplied to the target capacitor that is a part of the plurality of capacitors is set to the clock supplied to a non-target capacitor different from the target capacitor among the plurality of capacitors. It is characterized in that an amplitude reducing unit for reducing the amplitude of the signal is provided.

Specifically, for example, in the charge pump circuit, the plurality of rectifying elements are composed of a first rectifying element to an nth rectifying element (n is an integer of 4 or more), and are directed from the voltage input terminal to the voltage output terminal. The plurality of rectifying elements are directly connected in the order of first, second,..., (n−1)th, nth rectifying element, and among the plurality of capacitors, the (n−1)th rectifying element and the a capacitor having a first end connected to a connection node between the n rectifying elements, and a capacitor having a first end connected to a connection node between the (n-2)th rectifying element and the (n-1)th rectifying element. The target capacitors may be included as a first target capacitor and a second target capacitor.

At this time, for example, in the charge pump circuit, a first clock line to which a first clock signal having a constant reference amplitude is applied and a second clock signal having the reference amplitude and having a phase opposite to that of the first clock signal are provided. An additional second clock line is further provided, and a second end of the asymmetric capacitor is connected to the first clock line or the second clock line to supply the first clock signal or the second clock signal. The amplitude reduction unit is provided between the first target capacitor and the second target capacitor and the first clock line and the second clock line, and the amplitude reduction unit is in phase with the first clock signal. A clock signal having an amplitude smaller than the reference amplitude is supplied to the second end of one of the first target capacitor and the second target capacitor, and is in phase with the second clock signal. And a clock signal having an amplitude smaller than the reference amplitude may be supplied to the second end of the other one of the first target capacitor and the second target capacitor.

More specifically, for example, in the charge pump circuit, the amplitude reduction unit is provided between one of the first clock line and the second clock line and a second end of the first target capacitor. A first depletion type MOSFET inserted in the second depletion type MOSFET and a second depletion type MOSFET inserted between the other clock line of the first clock line and the second clock line and the second end of the second target capacitor. And a MOSFET.

Further, for example, in the charge pump circuit, the plurality of rectifying elements include a first rectifying element to an nth rectifying element (n is an integer of 3 or more), and the first rectifying element extends from the voltage input terminal toward the voltage output terminal. The plurality of rectifying elements are directly connected in the order of second,..., (n−1)th, nth rectifying element, and among the plurality of capacitors, the (n−1)th rectifying element and the nth rectifying element The target capacitor may include a capacitor having a first end connected to a connection node between them or a connection node between the (n-2)th rectifying element and the (n-1)th rectifying element.

At this time, for example, in the charge pump circuit, a first clock line to which the first clock signal having a predetermined reference amplitude is applied and a second clock signal having the reference amplitude and having a phase opposite to that of the first clock signal. Is further provided, and a second end of the asymmetric capacitor is connected to the first clock line or the second clock line to supply the first clock signal or the second clock signal. The amplitude reduction unit is provided between the target capacitor and one of the first clock line and the second clock line, and the amplitude reduction unit includes the first clock signal or the second clock signal. A clock signal in phase with the signal and having an amplitude smaller than the reference amplitude may be provided to the second end of the subject capacitor.

More specifically, for example, in the charge pump circuit, the amplitude reduction unit is inserted between one of the first clock line and the second clock line and a second end of the target capacitor. It is preferable to have a depletion type MOSFET that is set.

Further, for example, in the charge pump circuit, each rectifying element may be composed of a diode-connected MOSFET, or may be composed of a diode.

A semiconductor device according to the present invention includes a semiconductor integrated circuit including the charge pump circuit.

A semiconductor memory device according to the present invention includes the charge pump circuit and a memory unit capable of storing data, and writes data to the memory unit using an output voltage of the charge pump circuit. And

An electric device according to the present invention includes the semiconductor memory device, and a signal processing device that is connected to the semiconductor memory device and outputs a command for instructing the semiconductor memory device to write or read data. Is characterized by.

According to the present invention, it is possible to provide a charge pump circuit that contributes to a reduction in the probability of occurrence of defects, and a semiconductor device, a semiconductor memory device, and an electric device using the charge pump circuit.

It is a figure which shows the schematic whole structure of EEPROM which concerns on 1st Embodiment of this invention with MPU. FIG. 3 is an external perspective view of the semiconductor device according to the first embodiment of the present invention. It is an internal block diagram of the charge pump circuit which concerns on 1st Embodiment of this invention. FIG. 4 is a diagram illustrating an internal configuration example of the clock driver of FIG. 3 according to the first embodiment of the present invention. FIG. 4 is a diagram showing an internal configuration example of the voltage detection circuit of FIG. 3 according to the first embodiment of the present invention. FIG. 4 is a diagram showing an internal configuration example of the voltage input circuit of FIG. 3 according to the first embodiment of the present invention. FIG. 3 is a diagram showing a relationship between a plurality of clock signals according to the first embodiment of the present invention. FIG. 3 is a diagram for explaining a voltage relationship around a depletion type MOSFET according to the first embodiment of the present invention. FIG. 9 is a first modified internal configuration diagram of the charge pump circuit according to the first embodiment of the present invention. FIG. 9 is a second modified internal configuration diagram of the charge pump circuit according to the first embodiment of the present invention. It is a figure which shows the structure of the characteristic part which concerns on 2nd Embodiment of this invention. It is an external view of the vehicle which concerns on 3rd Embodiment of this invention. It is a block diagram of the airbag system which concerns on 3rd Embodiment of this invention. It is an internal block diagram of the charge pump circuit which concerns on the related technology of this invention. FIG. 15 is a waveform diagram of the output voltage of the charge pump circuit of FIG. 14.

Hereinafter, an example of an embodiment of the present invention will be specifically described with reference to the drawings. In each drawing referred to, the same portions are denoted by the same reference numerals, and in principle, duplicated description of the same portions will be omitted. In this specification, for simplification of description, a symbol or code that refers to information, a signal, a physical quantity, an element, a member, or the like is described, and information, a signal, a physical quantity, an element, or a member corresponding to the symbol or the code is described. The names such as "" may be omitted or abbreviated. For example, the reference clock signal referred to by “PCLK” described later (see FIG. 3) may be referred to as the reference clock signal PCLK or may be abbreviated as the clock signal PCLK, but they are all Refers to the same thing.

First, some terms used in the description of this embodiment will be described. The ground refers to a conductive portion having a reference potential of 0 V (zero volt) or the reference potential itself. In each embodiment, a voltage shown without a reference represents a potential viewed from the ground. Line is synonymous with wiring. A level refers to a potential level, and a high level has a higher potential than a low level with respect to an arbitrary signal or voltage.

Regarding an arbitrary transistor configured as a FET (field effect transistor), the on state means that the drain and the source of the transistor are in a conductive state, and the off state means that the drain and the source of the transistor are connected. Indicates a non-conducting state (cutoff state). Hereinafter, the ON state and the OFF state may be simply referred to as ON and OFF.

<<First Embodiment>>
A first embodiment of the present invention will be described. FIG. 1 is a schematic overall block diagram of an EEPROM (Electrically Erasable Programmable Read-Only Memory) 1 according to the first embodiment of the present invention. FIG. 1 also shows an MPU (Micro Processing Unit) 2 which is an example of a signal processing device connected to the EEPROM 1. The EEPROM 1 includes a charge pump circuit 10, a voltage selection unit 20, a memory unit 30, and a control unit 40. Each circuit forming the EEPROM 1 including the charge pump circuit 10, the voltage selection unit 20, the memory unit 30, and the control unit 40 is integrated with a semiconductor to form a semiconductor integrated circuit.

FIG. 2 is an external perspective view of the semiconductor device IC1 including the EEPROM 1. The semiconductor device IC1 is an electronic component formed by encapsulating a semiconductor integrated circuit including each element forming the EEPROM 1 in a housing (package) made of resin. A plurality of external terminals are provided on the housing of the semiconductor device IC1, and the plurality of external terminals include the power supply input terminal VCC, the ground terminal GND, and the communication terminal COM shown in FIG. Terminals other than these may be included in the plurality of external terminals. The MPU 2 is connected to the communication terminal COM. The communication terminal COM may be composed of two or more external terminals. The MPU 2 can give various commands to the EEPROM 1 via the communication terminal COM. It may be understood that the command is given to the control unit 40. It should be noted that the number of external terminals of the semiconductor device IC1 and the appearance of the semiconductor device IC1 shown in FIG. 2 are merely examples, and the number of external terminals and the type of housing in the semiconductor device IC1 are arbitrary. The following description of the EEPROM 1 is also the description of the semiconductor device IC1.

The charge pump circuit 10 boosts the power supply voltage Vcc to generate a voltage higher than the power supply voltage Vcc as the output voltage Vpp. A power supply voltage Vcc, which is a positive DC voltage, is input to the power supply input terminal VCC from outside the EEPROM 1. For example, a voltage within the range of 1.6 V or more and 5.5 or less is input as the power supply voltage Vcc. On the other hand, the target reference voltage Vtg of the output voltage Vpp is set to, for example, about 15V to 20V. The ground terminal GND is connected to the ground.

Under the control of the control unit 40, the voltage selection unit 20 supplies one of the power supply voltage Vcc and the output voltage Vpp of the charge pump circuit 10 to the memory unit 30 as the memory drive voltage Vm.

The memory unit 30 includes a memory array composed of a plurality of memory cells arranged in a matrix. One bit of data is stored in each memory cell. The memory unit 30 is a non-volatile memory that can retain the stored contents in each memory cell even when the supply of the power supply voltage Vcc to the power supply input terminal VCC is interrupted. An address space consisting of a large number of addresses is defined in the memory unit 30, and 8-bit data can be stored at each address.

The control unit 40 includes a control logic, an address register, an address decoder, a data register, and the like, controls the operations of the charge pump circuit 10 and the voltage selection unit 20 based on a command received from the MPU 2, and reads/writes data from/to the memory unit 30. To execute.

The commands transmitted from the MPU 2 to the EEPROM 1 include a write command for instructing the EEPROM 1 to write data and a read command for instructing the EEPROM 1 to read data. The command transmitted by the MPU 2 to the EEPROM 1 may further include commands other than the write command and the read command.

When the read command is received by the EEPROM 1, the control unit 40 executes the following read processing. In the read processing, the control unit 40 controls the voltage selection unit 20 so that the power supply voltage Vcc is supplied to the memory unit 30 as the memory drive voltage Vm, and the data in the address specified by the read command is stored in the memory unit 30. The read data is read from the memory 30, and the read data is transmitted to the MPU 2 via the communication terminal COM.

When the EEPROM 1 receives the write command, the control unit 40 executes the following write processing. In the write process, the control unit 40 controls the voltage selection unit 20 so that the output voltage Vpp is supplied to the memory unit 30 as the memory drive voltage Vm, and the address is specified in the memory unit 30 by the write command. Write the data specified by the write command. Although the erase process of erasing the data in the memory unit 30 can be executed in the EEPROM 1, the erase process is equivalent to writing a prescribed value (for example, a value of “0”) in the memory unit 30, and therefore the erase process will be described below. Is also a kind of write processing.

An operation that is performed by the charge pump circuit 10 and that generates a voltage higher than the power supply voltage Vcc as the output voltage Vpp by boosting the power supply voltage Vcc is called a boost operation. During execution of the boosting operation, the output voltage Vpp is stabilized at the reference voltage Vtg which is a target voltage preset with respect to the output voltage Vpp. Stabilization here means that the output voltage Vpp is maintained in the vicinity of the reference voltage Vtg, and the output voltage Vpp may temporarily exceed the reference voltage Vtg or may slightly fall below the reference voltage Vtg. There is also.

The control unit 40 has a function of controlling execution/non-execution of the boosting operation by the charge pump circuit 10. Specifically, the control unit 40 causes the charge pump circuit 10 to perform the boosting operation in the section in which the write process is performed, and stops the boosting operation by the charge pump circuit 10 in the other sections. This is because the relatively high voltage (Vpp) is required only when writing data. Therefore, the boosting operation is stopped in the section in which the write processing is not performed, including the section in which the read processing is performed. It should be noted that the output voltage Vpp does not reach the reference voltage Vtg until a certain time has elapsed after the boost operation is started. However, the actual writing of data in the memory unit 30 requires the output voltage Vpp after the boost operation starts. Is executed after reaching the reference voltage Vtg.

FIG. 3 shows the internal configuration of the charge pump circuit 10. The charge pump circuit 10 is a so-called Dickson type charge pump circuit. The charge pump circuit 10 includes n rectifiers D[1] to D[n], n capacitors C[1] to C[n], a clock driver 110, a voltage detection circuit 120, and a voltage input. The circuit 130 and the oscillator 140 are provided, and at least one depletion type MOSFET (metal-oxide-semiconductor field-effect transistor) is provided. Here, it is assumed that the charge pump circuit 10 is provided with two transistors MA and MB as depletion type and N channel type MOSFETs. It should be noted that the oscillator 140 may be considered as a circuit provided inside the EEPROM 1 and outside the charge pump circuit 10. n is an arbitrary integer of 4 or more, and is “n=34”, for example. In the following, it is considered that “n=34” unless otherwise stated. Lines LL1, LL2, LL1' and LL2' represent clock lines provided in the charge pump circuit 10.

The oscillator 140 generates and outputs the reference clock signal PCLK. The oscillator 140 is a circuit that generates the reference clock signal PCLK only when necessary. That is, the oscillator 140 starts the generation and output of the reference clock signal PCLK in response to the reception of the write command in the EEPROM 1, and stops the generation of the reference clock signal PCLK in response to the completion of the write processing. The generation of the reference clock signal PCLK is stopped in the section in which the write processing is not performed, including the section in which the read processing is performed. However, the oscillator 140 may always generate the reference clock signal PCLK. All the clock signals described in this embodiment including the reference clock signal PCLK are rectangular wave signals having a predetermined frequency, and therefore, high level and low level signal levels are periodically and alternately set.

The rectifying elements D[1] to D[n] are inserted in series between the voltage input terminal 151 and the voltage output terminal 152. Here, it is assumed that each rectifying element is composed of a diode-connected N-channel MOSFET (metal-oxide-semiconductor field-effect transistor). Arbitrary MOSFETs including MOSFETs as rectifying elements are assumed to be enhancement type MOSFETs unless otherwise specified, except for the transistors MA and MB. The output voltage Vpp of the charge pump circuit 10 is generated at the voltage output terminal 152.

Specifically, in the MOSFET as the rectifying element D[i], the drain and the gate are commonly connected to each other. "I" represents an arbitrary integer. That is, for example, the drain and the gate are commonly connected to each other in the MOSFET as the rectifying element D[1], and the drain and the gate are commonly connected to each other in the MOSFET as the rectifying element D[2]. The same applies to the rectifying elements D[3] to D[n]. Then, from the voltage input terminal 151 to the voltage output terminal 152, rectifying elements D[1], D[2], D[3],..., D[n-1], D[n] are arranged in this order. The rectifying elements D[1] to D[n] are connected in series. Each rectifying element functions as a charge transfer element. In the MOSFET as each rectifying element, the drain corresponds to the charge input side and the source corresponds to the charge output side.

From the voltage input terminal 151 to the voltage output terminal 152, the one closer to the voltage input terminal 151 corresponds to the former stage, and the closer to the voltage output terminal 152 corresponds to the latter stage. Therefore, as viewed from the rectifying element D[i], the rectifying element D[i-1] is located on the front side, and the rectifying element D[i+1] is located on the rear side (where "i" is 2 or more and ( n-1) an integer less than or equal to). The drains of the rectifying elements except the rectifying element D[1] are connected to the sources of the rectifying elements adjacent to the front stage side, and the sources of the rectifying elements except the rectifying element D[n] are adjacent to the rear stage side. Connected to the drain of. That is, when expressed using a variable "i" that is an integer of 2 or more and (n-1) or less, the drain of the rectifying element D[i] is connected to the source of the rectifying element D[i-1], and the rectifying element D[i-1] is connected. The source of D[i] is connected to the drain of the rectifying element D[i+1]. The drain of the rectifying element D[1] arranged on the most front side (that is, the rectifying element D[1] arranged on the first stage) is connected to the voltage input terminal 151, and the rectifying element D arranged on the most rear side. The source of [n] (that is, the rectifying element D[n] arranged in the final stage) is connected to the voltage output terminal 152.

A connection node between two rectifying elements D[i-1] and D[i] adjacent to each other (more specifically, the source of the rectifying element D[i-1] and the drain of the rectifying element D[i] are Nodes that are connected to each other are represented by the code “ND[i]”. Further, for convenience, the voltage input terminal 151 to which the drain of the rectifying element D[1] is connected is expressed as a connection node ND[1], and the voltage output terminal 152 to which the source of the rectifying element D[n] is connected is a connection node. It may be expressed as [n+1]. One end of the capacitor C[i] is connected to the node ND[i] (where “i” is any integer from 1 to n).

Of the capacitors C[1] to C[n-2], the other end of the odd-numbered capacitor is connected to the first clock line LL1 and the other end of the even-numbered capacitor is connected to the second clock line LL2. That is, for an integer “m” of 1 or more (n/2−1) or less, the other end of the capacitor C[2·m−1] is connected to the first clock line LL1 and the other end of the capacitor C[2·m] The end is connected to the second clock line LL2. The other end of the capacitor C[n-1] is connected to the clock line LL1', and the other end of the capacitor C[n] is connected to the clock line LL2'. Also, the source of the transistor MB is connected to the clock line LL1', and the source of the transistor MA is connected to the clock line LL2'. The drain of the transistor MB is connected to the first clock line LL1 and the drain of the transistor MA is connected to the second clock line LL2. That is, the transistor MB is inserted in series between the other end of the capacitor C[n-1] whose one end is connected to the node ND[n-1] and the first clock line LL1, and the one end is connected to the node ND[n]. A transistor MA is inserted in series between the other end of the capacitor C[n] connected to the second clock line LL2. Note that one end and the other end of the capacitor C[i] correspond to the first end and the second end, respectively. The first end of the capacitor C[i] corresponds to the rectifying element connection end, and the second end of the capacitor C[i] corresponds to the clock line connection end.

FIG. 4 shows a configuration example of the clock driver 110. The clock driver 110 is a circuit for supplying the clock signals CLK and CLKB to the clock lines LL1 and LL2, respectively. The clock driver 110 of FIG. 4 includes AND circuits 111 and 112, an inverter circuit 113, and , Is provided. The reference clock signal PCLK from the oscillator 140 is supplied to the clock driver 110.

The inverter circuit 113 generates and outputs an inverted signal of the reference clock signal PCLK. The AND circuit 111 outputs a logical product signal of the reference clock signal PCLK and the enable signal CPEN supplied from the voltage detection circuit 120. The AND circuit 112 outputs a logical product signal of the output signal of the inverter circuit 113 (that is, an inverted signal of the reference clock signal PCLK) and the enable signal CPEN supplied from the voltage detection circuit 120. The output terminal of the AND circuit 111 to which the output signal of the AND circuit 111 is applied is connected to the first clock line LL1, and the output terminal of the inverter circuit 112 to which the output signal of the inverter circuit 112 is applied is connected to the second clock line LL2.

Therefore, when the enable signal CPEN is at the high level, the reference clock signal PCLK is directly output to the first clock line LL1 as the first clock signal CLK through the AND circuit 111, and the clock signal obtained by inverting the reference clock signal PCLK is generated. The second clock signal CLKB is output to the second clock line LL2 through the inverter circuit 113 and the AND circuit 112. When the enable signal CPEN is at the low level, the levels of the output signals of the AND circuits 111 and 112 (hence the signal levels of the clock lines LL1 and LL2) are maintained at the low level.

As described above, when the enable signal CPEN is at the high level, the clock driver 110 outputs the clock signal in phase with the reference clock signal PCLK as the first clock signal CLK to the first clock line LL1 and reverses the reference clock signal PCLK. An operation of outputting the phase clock signal as the second clock signal CLKB to the second clock line LL2 (hereinafter, referred to as clock output operation) is executed. The above-described boosting operation is realized by the clock output operation. When the enable signal CPEN is at the low level, the clock output operation is not executed (in other words, the clock output operation is stopped).

During execution of the clock output operation, the output voltage Vpp rises by repeating conduction/non-conduction of each rectifying element and accumulation of electric charge in each capacitor. When the output voltage Vpp reaches the reference voltage Vtg, the clock output operation is stopped by the function of the voltage detection circuit 120 described later. In the period in which the clock output operation is stopped, the supply of charges from the voltage input terminal 151 to the voltage output terminal 152 is interrupted, so that at least the rise of the output voltage Vpp is stopped and the load (memory unit 30) connected to the voltage output terminal 152 is stopped. Output voltage Vpp decreases. Then, when the output voltage Vpp falls below the reference voltage Vtg, the clock output operation is restarted. By repeating these sequences, the output voltage Vpp is maintained near the reference voltage Vtg.

The circuit configuration of the clock driver 110 is arbitrary as long as the above clock output operation can be realized. For example, the clock driver 110 is provided with a flip-flop that latches the enable signal CPEN in synchronization with the switching from the low level to the high level or the switching from the high level to the low level in the signal level of the reference clock signal PCLK. The clock output operation may be switched between execution and non-execution based on the signal.

The voltage detection circuit 120 will be described. The voltage detection circuit 120 is connected to the voltage output terminal 152 and outputs a low level or high level enable signal CPEN according to the output voltage Vpp of the charge pump circuit 10. Specifically, the voltage detection circuit 120 detects the level relationship between the output voltage Vpp generated at the voltage output terminal 152 and the predetermined reference voltage Vtg, and generates and outputs the enable signal CPEN according to the level relationship.

FIG. 5 shows a configuration example of the voltage detection circuit 120. The voltage detection circuit 120 of FIG. 5 includes a Zener diode 121, transistors 122 to 124, a constant current circuit 125, and a buffer circuit 126. The transistor 122 is configured as a P-channel type MOSFET, and the transistors 123 and 124 are configured as N-channel type MOSFETs.

The cathode of the Zener diode 121 is connected to the voltage output terminal 152, and the anode of the Zener diode 121 is connected to the source of the transistor 122. The Zener diode 121 may be a plurality of Zener diodes connected in series, or may be a single Zener diode. The drain of the transistor 122, the drain and gate of the transistor 123, and the gate of the transistor 124 are commonly connected to each other. The sources of the transistors 123 and 124 are connected to the ground. The transistors 123 and 124 form a current mirror circuit. The drain of the transistor 124 is connected to the constant current circuit 125 and the input terminal of the buffer circuit 126. The constant current circuit 125 operates so that a constant current flows toward the drain of the transistor 124 based on the power supply voltage Vcc. The buffer circuit 126 outputs a low level enable signal CPEN if the voltage at the drain of the transistor 124 is less than a predetermined threshold voltage, and outputs a high level if the voltage at the drain of the transistor 124 is at least the predetermined threshold voltage. The level enable signal CPEN is output. The buffer circuit 126 may be configured by connecting two inverter circuits in series.

The voltage detection circuit 120 of FIG. 5 operates as follows. When the output voltage Vpp is lower than the predetermined reference voltage Vtg, the Zener diode 121 becomes non-conductive and no current flows through the transistors 122 and 123. Therefore, no current flows through the transistor 124. Therefore, the drain voltage of the transistor 124 becomes the threshold voltage. The voltage becomes higher than the voltage and the enable signal CPEN becomes high level. On the other hand, when the output voltage Vpp is equal to or higher than the predetermined reference voltage Vtg, the Zener diode 121 is turned on and a current flows through the transistors 122 and 123. Therefore, a current also flows through the transistor 124. Therefore, the drain voltage of the transistor 124 is equal to the threshold voltage. And the enable signal CPEN becomes low level.

A predetermined adjustment voltage Vg is applied to the gate of the transistor 122. The adjustment voltage Vg is, for example, 0 V or a predetermined positive DC voltage. The source voltage of the transistor 122 when a current flows through the Zener diode 121 increases or decreases as the adjustment voltage Vg increases or decreases. Therefore, the reference voltage Vtg described above can be set by setting the adjustment voltage Vg.

In practice, it can be considered that the boundary between conduction and non-conduction of the Zener diode 121 when the output voltage Vpp is near the reference voltage Vtg has a width. A state in which a current flows through the Zener diode 121 to such an extent that the enable signal CPEN becomes a low level corresponds to the conductive state of the Zener diode 121, and the other states of the Zener diode 121 correspond to the non-conductive state of the Zener diode 121. You can also think of it.

In any case, the circuit configuration shown in FIG. 5 is merely an example. When the output voltage Vpp is equal to or higher than the predetermined reference voltage Vtg, the low level enable signal CPEN is output, while the output voltage Vpp is lower than the reference voltage Vtg. At this time, the internal configuration of the voltage detection circuit 120 is arbitrary as long as it has a function of outputting the enable signal CPEN of high level. The low-level enable signal CPEN functions as a signal indicating that the output voltage Vpp is equal to or higher than the predetermined reference voltage Vtg. On the other hand, the high-level enable signal CPEN functions as a signal indicating that the output voltage Vpp is lower than the predetermined reference voltage Vtg.

Next, the voltage input circuit 130 (see FIG. 3) will be described. The voltage input circuit 130 is a circuit that inputs a voltage based on the power supply voltage Vcc to the voltage input terminal 151.

FIG. 6 shows a configuration example of the voltage input circuit 130. The voltage input circuit 130 of FIG. 6 includes a transistor 131 configured as a P-channel MOSFET, transistors 132 and 133 configured as an N-channel MOSFET, and a capacitor 134. The power supply voltage Vcc is applied to the source of the transistor 131. The gate of the transistor 131 is connected to the ground. The drain of the transistor 131, the drain of the transistor 132, the drain and the gate of the transistor 133 are commonly connected to each other. The source of the transistor 132 is connected to the voltage input terminal 151. One end of the capacitor 134 is commonly connected to the gate of the transistor 132 and the source of the transistor 133, and the other end of the capacitor 134 is connected to the second clock line LL2.

By using such a voltage input circuit 130, a voltage higher than the power supply voltage Vcc can be generated in the voltage input terminal 151 in the period in which the clock output operation is performed, and the voltage at the voltage input terminal 151 can be generated. Can be further increased by rectifying elements D[1] to D[n] and capacitors C[1] to C[n] to obtain the output voltage Vpp.

The charge pump circuit 10 may be configured so that the power supply voltage Vcc itself is applied to the voltage input terminal 151. In this case, the voltage input circuit 130 is unnecessary and the capacitor C[1] can be omitted.

As is clear from the above description, the first clock line LL1 is a wiring to which the first clock signal CLK should be propagated, and the second clock line LL2 is a wiring to which the second clock signal CLKB should be propagated. The capacitors C[1] to C[n] are the first capacitors to be supplied with the clock signal in phase with the first clock signal CLK (the clock signal CLK itself or a clock signal CLK′ described later), and the second capacitor. It can be said that it is classified as one of the second capacitors to be supplied with the clock signal having the same phase as the clock signal CLKB (the clock signal CLKB itself or a clock signal CLKB′ described later), and two connection nodes ND[i] adjacent to each other And ND[i+1], one node is connected to one end of the first capacitor and the other node is connected to one end of the second capacitor.

The capacitors C[1] to C[n-2] are directly connected to the first clock line LL1 or the second clock line LL2 and supplied with the first clock signal CLK or the second clock signal CLKB. However, the capacitor C[n-1] is connected to the first clock line LL1 via the transistor MB, and the capacitor C[n] is connected to the second clock line LL2 via the transistor MA. Therefore, the amplitude of the clock signal CLK′ applied to the capacitor C[n−1] is smaller than the amplitude of the clock signal CLK, and the amplitude of the clock signal CLKB′ applied to the capacitor C[n] is the amplitude of the clock signal CLKB. Will be smaller than. Clock signals CLK' and CLKB' represent clock signals applied to the clock lines LL1' and LL2', respectively.

FIG. 7A shows a waveform example of the clock signals CLK and CLK', and FIG. 7B shows a waveform example of the clock signals CLKB and CLKB'. The oscillator 140 and the clock driver 110 are circuits that generate each clock signal based on the power supply voltage Vcc. Therefore, the high level of the signal in each of the reference clock signal PCLK, the first clock signal CLK, and the second clock signal CLKB The level of the power supply voltage Vcc and the low level of the signal match the level of the ground. That is, the amplitudes of the clock signals PCLK, CLK, and CLKB all match the magnitude of the power supply voltage Vcc. Although the power supply voltage Vcc can be changed variously, it is assumed here that the specifications of the EEPROM 1 determine that a voltage within the range of 1.6 V or more and 5.5 or less is input as the power supply voltage Vcc. .. In FIGS. 7A and 7B, it is assumed that the power supply voltage Vcc matches the maximum voltage of 5.5 V of the specification.

The gate voltage of the transistors MA and MB (that is, the voltage applied to the gates of the transistors MA and MB) is represented by the symbol "Vdg" (see FIG. 3). Although the specific value of the gate voltage Vdg of the transistor MA and the specific value of the gate voltage Vdg of the transistor MB can be different from each other, here, the common gate voltage Vdg is common to the transistors MA and MB. Shall be added.

Further, the gate threshold voltage of each of the transistors MA and MB is represented by the symbol “Vth”. When the gate-source voltage of the transistor MA (that is, the gate potential seen from the source potential) is equal to or higher than the gate threshold voltage Vth, the transistor MA is turned on, and the gate-source voltage of the transistor MA is the gate threshold voltage Vth. When less than, the transistor MA is turned off. Similarly, when the gate-source voltage of the transistor MB (that is, the gate potential viewed from the source potential) is equal to or higher than the gate threshold voltage Vth, the transistor MB is turned on, and the gate-source voltage of the transistor MB is gated. When it is less than the threshold voltage Vth, the transistor MB is turned off.

Then, the clock signal CLK' applied to the clock line LL1' becomes a clock signal in phase with the first clock signal CLK applied to the first clock line LL1. That is, the clock signal CLK' becomes high level when the first clock signal CLK is high level, and becomes low level when the first clock signal CLK is low level. Similarly, the clock signal CLKB' applied to the clock line LL2' becomes a clock signal in phase with the second clock signal CLKB applied to the second clock line LL2. That is, the clock signal CLKB' becomes high level when the second clock signal CLKB is high level, and becomes low level when the second clock signal CLKB is low level.

However, the high level voltage in the first clock signal CLK matches the power supply voltage Vcc, while the high level voltage in the clock signal CLK' is a voltage Vq smaller than the power supply voltage Vcc. Similarly, the high level voltage in the second clock signal CLKB matches the power supply voltage Vcc, while the high level voltage in the clock signal CLKB' is a voltage Vq smaller than the power supply voltage Vcc. The low level of the clock signals CLK, CLK', CLKB and CLKB' matches the level of ground. The clock signals CLK and CLKB are rectangular wave signals having a predetermined reference amplitude that matches the magnitude of the power supply voltage Vcc, whereas the clock signals CLK′ and CLKB′ are rectangular wave signals having an amplitude smaller than the reference amplitude. Become.

The amplitudes of the clock signals CLK' and CLKB' match the magnitude of the voltage Vq, and the voltage Vq is represented by "Vq=Vdg-Vth". Therefore, for example, for the transistors MA and MB, if the gate voltage Vdg is 1.2V and the gate threshold voltage is (−0.4V), the voltage Vq is 1.6V.

FIGS. 8A and 8B show the relationship between the voltages around the transistor MA when the voltages on the clock line LL2 are 5.5 V and 0 V, respectively. However, in FIGS. 8A and 8B, it is assumed that the gate voltage Vdg is 1.2V and the gate threshold voltage is (−0.4V). When the voltage on the clock line LL2 is 1.6 V or more, the voltage on the clock line LL2′ includes the voltage “(Vdg−Vth)”, that is, when the voltage on the clock line LL2 is 5.5 V. It is fixed at 1.6V (=1.2-(-0.4)V). When the voltage on the clock line LL2 is less than 1.6V, the transistor MA becomes conductive, so that the voltage on the clock line LL2' matches the voltage on the clock line LL2. The same applies to the voltages on the clock lines LL1 and LL1'.

As described above, when the clock signal rises, a relatively large voltage is momentarily applied to the corresponding element (rectifying element and capacitor) (see FIG. 16). On the other hand, if an excessive voltage is applied to the element, the element is likely to be defective (destructed or deteriorated). In consideration of this, in the charge pump circuit 10 according to the present embodiment, among the capacitors C[1] to C[n], the capacitors C[n-1] and C[n] to which a relatively large voltage is applied are applied. Then, a clock signal having an amplitude smaller than that of the other capacitors C[1] to C[n-2] is supplied. Therefore, even when the power supply voltage Vcc is relatively high, the element (including the rectifying element D[n-1] and the capacitor C[n-1]) connected to the node ND[n-1] and the node ND[. n] is applied to the elements (including the rectifying element D[n] and the capacitor C[n]) that have the same level of peak voltage as that in the case where the power supply voltage Vcc is relatively low, and therefore these elements are defective. The probability of occurrence of is suppressed low.

It is sufficient that a predetermined positive voltage is applied to the transistors MA and MB as the gate voltage Vdg only in the section in which the clock output operation is executed, and the gate voltage Vdg may be 0V in the section in which the clock output operation is not executed. .. A gate voltage supply circuit (not shown) that supplies such a gate voltage Vdg to the gates of the transistors MA and MB is built in the charge pump circuit 10. The gate voltage supply circuit, for example, raises the gate voltage Vdg from 0V to a predetermined positive voltage (for example, 1.2V) in synchronization with the start of generation of the reference clock signal PCLK by the oscillator 140 in response to the reception of the write command, and then performs the write operation. The gate voltage Vdg may be returned to 0V in synchronization with the stop of the generation of the reference clock signal PCLK in response to the completion of the processing.

It is preferable that the amplitudes of the clock signals CLK' and CLKB' corresponding to the magnitude of the voltage Vq match the minimum voltage in the specifications of the power supply voltage Vcc. That is, for example, when the specification of the EEPROM 1 specifies that a voltage within the range of 1.6 V or more and 5.5 or less is input as the power supply voltage Vcc, the gate is set so that the voltage Vq becomes 1.6 V. It is preferable to set the threshold voltage Vth and the gate voltage Vdg when the clock output operation is executed. As a result, within the above range, the amplitudes of the clock signals CLK' and CLKB' are constant regardless of the power supply voltage Vcc. As a result, the withstand voltage design can be performed under the assumption that the amplitudes thereof are constant, which is advantageous. When those amplitudes fluctuate, the size of the device may be increased due to the need for a withstand voltage design adapted to the maximum amplitude. However, the voltage Vq may be different from the minimum voltage in the specifications of the power supply voltage Vcc.

Of the capacitors C[1] to C[n], a capacitor supplied with the clock signal CLK′ or CLKB′ is referred to as a target capacitor, and the other capacitors (that is, the second end connected to the clock line LL1 or LL2). A capacitor that receives the supply of the clock signal CLK or CLKB) is called an asymmetrical capacitor. In the configuration of FIG. 3, only the capacitors C[n-1] and C[n] function as target capacitors. At this time, it can be said that the capacitors C[n] and C[n-1] correspond to the first and second target capacitors, respectively. As the number of target capacitors increases, the time required for the output voltage Vpp to reach the reference voltage Vtg increases. Therefore, only a part of the capacitors C[1] to C[n] is set as the target capacitor. Here, it is assumed that “n=34”, but when two capacitors among the capacitors C[1] to C[n] are the target capacitors, “n” is an arbitrary integer of 4 or more. Good to have Therefore, for example, if “n=4”, the capacitors C[3] and C[4] can be set as the target capacitors and the capacitors C[1] and C[2] can be set as the non-target capacitors. ..

Of the capacitors C[1] to C[n], three or more capacitors may be set as the target capacitors. That is, for example, in the case of “n≧6”, a total of four capacitors C[n−3] to C[n] are set as target capacitors, and other capacitors C[1] to C[n-4] are not target capacitors. It can also be set to. In this case, based on the configuration of FIG. 3, not only the capacitor C[n-1] but also the second end of the capacitor C[n-3] is connected to the clock line LL1' instead of the clock line LL1, and The second end of the capacitor C[n-2] as well as the capacitor C[n-2] may be connected to the clock line LL2′ instead of the clock line LL2. In order to set only a part of the capacitors C[1] to C[n] as the target capacitors, it is necessary to give “n” an integer value that is 2 or more larger than the number of target capacitors.

The number of target capacitors included in the capacitors C[1] to C[n] may be one. When the number of target capacitors is 1, “n” may be any integer of 3 or more (of course, “n” may be any integer of 4 or more). In this case, the target capacitor may be the capacitor C[n] to which a relatively high voltage is applied among the capacitors C[1] to C[n]. In that case, the transistor shown in FIG. MB may be deleted, and a modification may be performed in which the second end of the capacitor C[n-1] is connected to the clock line LL1 instead of the clock line LL1' as shown in FIG. 9 (this modification is performed in FIG. 9). Charge pump circuit 10a is shown). Alternatively, the target capacitor may be the capacitor C[n-1], in which case the transistor MA is deleted based on the configuration of FIG. 3 and the second end of the capacitor C[n] is removed as shown in FIG. Is connected to the clock line LL2 instead of the clock line LL2′ (FIG. 10 shows the modified charge pump circuit 10b).

However, in the circuit composed of the rectifying elements D[1] to D[n] and the capacitors C[1] to C[n], the peak voltage is changed at the instant when the respective low levels of the clock signals CLK and CLKB are switched to the high level. Occurs, and its peak voltage is assumed to be as high as the same between the nodes ND[n-1] and ND[n]. Therefore, both capacitors C[n] and C[n-1] are set as target capacitors. It is desirable to include it.

As can be understood from the fact that “n=3”, the number of rectifying elements D[1] to D[n] may be an odd number (however, 3 or more). When the number of rectifying elements D[1] to D[n] is an odd number, the other end (second end) of the even-numbered capacitors among the capacitors C[1] to C[n-2] is the first. The other end (second end) of the odd-numbered capacitors connected to the clock line LL1 may be connected to the second clock line LL2.

Here, the relationship between the reference clock signal PCLK and the clock signals CLK and CLKB may be reversed. That is, the clock signal CLKB may be in phase with the reference clock signal PCLK and the clock signal CLK may be in antiphase with the reference clock signal PCLK.

Taking these modification techniques into consideration, it can be considered that the charge pump circuit according to the present invention (referred to as a charge pump circuit W for convenience) has the following configuration. That is, the charge pump circuit W according to the present invention includes a plurality of rectifying elements (D[1] to D[n]) inserted in series between the voltage input terminal (151) and the voltage output terminal (152). , A plurality of capacitors (C[1] to C[1], whose first end is connected to a connection node between adjacent rectifying elements of the plurality of rectifying elements and which receives a clock signal in phase with or opposite to the reference clock signal at the second end). C[n]) and a charge pump circuit for generating an output voltage (Vpp) higher than the voltage at the voltage input terminal at the voltage output terminal, the target pump being a part of a plurality of capacitors. And an amplitude reducing unit that reduces the amplitude of the clock signal supplied to the non-target capacitor different from the target capacitor.

The amplitude reduction unit includes the transistors MA and MB in the configuration example of FIG. 3, the transistor MA in the configuration example of FIG. 9, and the transistor MB in the configuration example of FIG. 10. The charge pump circuits (10, 10a, 10b) of FIGS. 3, 9, and 10 are specific examples of the charge pump circuit W.

In the case of “n≧4”, the charge pump circuit W can be configured as follows. That is, in the charge pump circuit W, among the plurality of capacitors (C[1] to C[n]), the connection node (ND[n]) between the (n−1)th rectifying element and the nth rectifying element is connected to the first node. The first end is connected to a capacitor (C[n]) to which one end is connected and a connection node (ND[n-1]) between the (n-2)th rectifying element and the (n-1)th rectifying element. The selected capacitor (C[n-1]) may be included in the target capacitors as the first target capacitor and the second target capacitor.

In the case of “n≧4”, the charge pump circuit W has the first clock line (LL1) to which the first clock signal (CLK) having the predetermined reference amplitude is applied, and the first clock line (LL1) having the reference amplitude and the first clock. A second clock line (LL2) to which a second clock signal (CLKB) having a phase opposite to that of the signal is further provided, and the first target capacitor and the second target capacitor, the first clock line and the second clock line (LL1, LL2). ) With an amplitude reduction unit (MA, MB), the amplitude reduction unit supplies a clock signal (CLK′) having the same phase as the first clock signal (CLK) and a smaller amplitude than the reference amplitude. It is supplied to the second end (the second end of the capacitor C[n-1] in the configuration of FIG. 3) of one of the first target capacitor and the second target capacitor and is in phase with the second clock signal (CLKB). And a clock signal (CLKB′) having an amplitude smaller than the reference amplitude is applied to the second end (of the capacitor C[n] in the configuration of FIG. 3) of the other of the first target capacitor and the second target capacitor. It is better to supply it to the second end).

The capacitor that receives the clock signal (CLK') having the same phase as the first clock signal (CLK) and smaller than the reference amplitude at the second end is the capacitor C[n-1] in the configuration of FIG. However, it can be a capacitor C[n]. Similarly, the capacitor that receives the clock signal (CLKB') in phase with the second clock signal (CLKB) and having an amplitude smaller than the reference amplitude at the second end is the capacitor C[n] in the configuration of FIG. , But can be a capacitor C[n−1].

In the case of “n≧3” or the case of “n≧4”, the charge pump circuit W can be configured as follows. That is, in the charge pump circuit W, among the plurality of capacitors (C[1] to C[n]), a connection node (ND[n]) or a connection node (ND[n]) between the (n-1)th rectifying element and the nth rectifying element. A capacitor (C[n] or C[n-1]) whose first end is connected to a connection node (ND[n-1]) between the (n-2) rectifying device and the (n-1)th rectifying device. May be included in the target capacitor.

Then, in the case of “n≧3” or the case of “n≧4”, the charge pump circuit W includes a first clock line (LL1) to which a first clock signal (CLK) having a predetermined reference amplitude is applied, and a reference A second clock line (LL2) having an amplitude and to which a second clock signal (CLKB) having a phase opposite to that of the first clock signal is applied; and any one of the target capacitor, the first clock line and the second clock line An amplitude reduction unit (MA or MB) is provided between the two and one of them, and the amplitude reduction unit has a clock signal (CLK′) in phase with the first clock signal or the second clock signal and having an amplitude smaller than the reference amplitude. Alternatively, CLKB′) may be supplied to the second end of the target capacitor.

<<Second Embodiment>>
A second embodiment of the present invention will be described. The second embodiment and third and fourth embodiments to be described later are embodiments based on the first embodiment, and matters not particularly mentioned in the second to fourth embodiments are the first as long as there is no contradiction. The description of the embodiment also applies to the second to fourth embodiments. In interpreting the description of the second embodiment, the description of the second embodiment may be prioritized for matters that are inconsistent between the first and second embodiments (the same applies to the third and fourth embodiments described later). .. As long as there is no contradiction, arbitrary plural embodiments among the first to fourth embodiments may be combined.

The example in which the amplitude reduction unit is configured by the depletion type MOSFET has been described above. The configuration may be arbitrary.

For example, in the charge pump circuit 10, as shown in FIG. 11, a level shifter 170 may be provided instead of the transistors MA and MB, and the level shifter 170 may function as an amplitude reduction unit. In FIG. 11, the second end of the capacitor C[n-1] and the second end of the capacitor C[n] are connected to clock lines LL1′ and LL2′, respectively, and the level shifter 170 is connected to the clock lines LL1 and LL1. It is inserted between the LL1' and the clock lines LL2 and LL2'. Then, the level shifter 170 generates clock signals obtained by shifting the high levels of the clock signals CLK and CLKB to the low potential side as clock signals CLK' and CLKB', respectively. That is, the level shifter 170 generates a clock signal CLK′ which is in phase with the clock signal CLK and whose high-level potential is lower than that of the clock signal CLK, and which is in phase with the clock signal CLKB and has a high level. To generate a clock signal CLKB′ whose potential is lower than that of the clock signal CLKB. Therefore, the amplitudes of the clock signals CLK' and CLKB' are smaller than the amplitudes of the clock signals CLK and CLKB. How to determine the amplitudes of the clock signals CLK' and CLKB' is as described in the first embodiment. The generated clock signals CLK' and CLKB' are output to the clock lines LL1' and LL2', respectively.

When the level shifter is applied to the configuration of FIG. 9, the level shifter may have only the function of inserting the level shifter only between the clock lines LL2 and LL2' to generate the clock signal CLKB' from the clock signal CLKB. Similarly, when the level shifter is applied to the configuration of FIG. 10, the level shifter has only the function of inserting the level shifter only between the clock lines LL1 and LL1′ and generating the clock signal CLK′ from the clock signal CLK. ..

<<Third Embodiment>>
A third embodiment of the present invention will be described. The EEPROM 1 is mounted on any electric device, or the EEPROM 1 and the MPU 2 are mounted on any electric device. Electric equipment generally includes equipment classified as electronic equipment, and electric equipment in the following description may be read as electronic equipment. Examples of the electric device on which the EEPROM 1 is mounted or the EEPROM 1 and the MPU 2 are mounted include an information terminal, a mobile phone (including a mobile phone classified as a smart phone), a personal computer, a television receiver, a washing machine, and an air conditioner. Besides, it may be a vehicle-mounted electric device.

FIG. 12 shows an example of an external view of a vehicle CR which is an automobile. The vehicle CR is equipped with a battery (not shown) and electric devices E11 to E18 that operate by receiving a drive voltage based on the output voltage of the battery. The mounting positions of the electric devices E11 to E18 shown in FIG. 12 are merely examples, and the mounting positions thereof may be variously changed. The EEPROM 1 and the MPU 2 can be incorporated in any of the electric devices E11 to E18.

The electric device E11 is an engine control unit that performs control related to the engine of the vehicle CR (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, and the like). The electric device E12 is a lamp control unit that controls lighting and extinguishment of a high intensity discharged lamp (HID) and a DRL (daytime running lamp) provided in the vehicle CR. The electric device E13 is a transmission control unit that performs control related to the transmission of the vehicle CR. The electric device E14 is a body control unit that performs control related to the motion of the vehicle CR, such as ABS (anti-lock brake system) control, EPS (electric power steering) control, and electronic suspension control.

The electric device E15 is a security control unit that performs drive control such as a door lock of the vehicle CR and a crime prevention alarm. The electric device E16 is an electric device incorporated into the vehicle CR at the factory shipment stage of the vehicle CR as a standard equipment item or a manufacturer option item such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof and an electric seat. is there. The electric device E17 is an electric device such as an in-vehicle A/V (audio/visual) device, a car navigation system, and an ETC (electronic toll collection system) device, which is optionally attached to the vehicle CR as a user option item. The electric device E18 is an electric device equipped with a high withstand voltage motor such as a blower, an oil pump, a water pump, and a battery cooling fan in the vehicle CR.

FIG. 13 shows an example of an airbag system 400 that can be mounted on the vehicle CR. An airbag system 400 shown in FIG. 13 includes an ECU (Electronic Control Unit) 410, a collision detection sensor 420, an ignition device (squib) 430, and an airbag 440. The ECU 410 includes an MPU 411, an ignition circuit 412 and an EEPROM 413. The EEPROM 1 according to the first or second embodiment can be used as the EEPROM 413, and the MPU 411 functions as the MPU 2 in FIG.

The collision detection sensor 420 detects impacts from the front and sides of the vehicle CR. The MPU 411 calculates an impact evaluation value based on the detection result of the collision detection sensor 420, and activates the ignition circuit 412 when the calculated impact evaluation value exceeds a predetermined collision determination value. As a result, a current flows through the ignition device 430 and the airbag 440 is deployed. The EEPROM 413 can store data on the operating status of the airbag system 400. The data may be written in the EEPROM 413 when a failure is detected by failure diagnosis. The written data is useful for analysis of the cause of failure.

<<Fourth Embodiment>>
A fourth embodiment of the present invention will be described. In the fourth embodiment, modification techniques and the like applicable to the above-described first to third embodiments will be described.

Each of the rectifying elements D[1] to D[n] may be a diode (semiconductor diode) configured by a PN junction instead of a diode-connected MOSFET.

The EEPROM 1 is an example of a semiconductor memory device as a non-volatile memory. The semiconductor memory device according to the present invention is not limited to the EEPROM 1 and is a memory device that is driven by using the output voltage Vpp of the charge pump circuit 10 (especially, a memory device that performs write processing by using the output voltage Vpp of the charge pump circuit 10). ) Is optional. For example, the semiconductor memory device may be a flash memory.

In the semiconductor memory device such as the EEPROM 1, the charge pump circuit 10 may be provided outside the semiconductor memory device. That is, to explain the configuration of FIG. 1 as an example, an EEPROM in which the charge pump circuit 10 is removed from the EEPROM 1 shown in FIG. 1 is formed as a semiconductor memory device, and the charge pump circuit 10 is externally connected to the semiconductor memory device. It may be done.

The application destination of the charge pump circuit 10 is not limited to the semiconductor memory device. That is, for example, the charge pump circuit 10 may be used to configure a step-up power supply device. It can be understood that the charge pump circuit 10 itself is a step-up power supply device. If the charge pump circuit 10 is composed of a semiconductor integrated circuit, the boost type power supply device corresponds to a kind of semiconductor device.

The relationship between the high level and the low level of any signal or voltage may be reversed without impairing the above-mentioned gist. Further, the channel type of the FET can be arbitrarily changed without impairing the above-mentioned gist.

Each of the above transistors may be any type of transistor. For example, the transistor described above as the MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor. Any transistor has a first electrode, a second electrode and a control electrode. In the FET, one of the first and second electrodes is the drain and the other is the source, and the control electrode is the gate. In the IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to the IGBT, one of the first and second electrodes is the collector and the other is the emitter, and the control electrode is the base.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiment is merely an example of the embodiment of the present invention, and the meanings of the terms of the present invention and each constituent element are not limited to those described in the above embodiment. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

1 EEPROM
10 charge pump circuit 20 voltage selection unit 30 memory unit 40 control unit 110 clock driver 120 voltage detection circuit 130 voltage input circuit 140 oscillator 151 voltage input terminal 152 voltage output terminal D[i] rectifying element C[i] capacitor Nd[i] Connection node MA, MB Depletion type transistor

Claims (11)

A plurality of rectifying elements inserted in series between the voltage input terminal and the voltage output terminal,
A plurality of capacitors each having a first end connected to a connection node between adjacent rectifiers in the plurality of rectifiers and receiving a clock signal in-phase or anti-phase with the reference clock signal at a second end; In a charge pump circuit that produces an output voltage at the voltage output terminal that is higher than the voltage at the voltage input terminal,
The amplitude of the clock signal supplied to the target capacitor that is a part of the plurality of capacitors is greater than the amplitude of the clock signal supplied to the non-target capacitor different from the target capacitor among the plurality of capacitors. A charge pump circuit comprising an amplitude reduction unit for reducing the size. The plurality of rectifying elements include a first rectifying element to an n-th rectifying element (n is an integer of 4 or more), and the first, second,..., (from the voltage input terminal to the voltage output terminal). n-1), the plurality of rectifying elements are directly connected in the order of the n-th rectifying element,
Among the plurality of capacitors, a capacitor having a first end connected to a connection node between the (n-1)th rectifying element and the nth rectifying element, an (n-2)th rectifying element, and a (n-1)th rectifying element. The charge pump circuit according to claim 1, wherein a capacitor having a first end connected to a connection node between the rectifying elements is included in the target capacitor as a first target capacitor and a second target capacitor. A first clock line to which a first clock signal having a predetermined reference amplitude is applied;
A second clock line to which a second clock signal having the reference amplitude and having a phase opposite to that of the first clock signal is applied,
A second end of the asymmetric capacitor is connected to the first clock line or the second clock line to receive the first clock signal or the second clock signal;
The amplitude reduction unit is provided between the first target capacitor and the second target capacitor and the first clock line and the second clock line,
The amplitude reduction unit supplies a clock signal in phase with the first clock signal and having an amplitude smaller than the reference amplitude to a second end of one of the first target capacitor and the second target capacitor. And a clock signal in phase with the second clock signal and having an amplitude smaller than the reference amplitude, to the second end of the other one of the first target capacitor and the second target capacitor. The charge pump circuit according to claim 2, wherein: The amplitude reduction unit includes a first depletion type MOSFET inserted between one of the first clock line and the second clock line and a second end of the first target capacitor, and the first depletion type MOSFET. 4. A second depletion type MOSFET inserted between the other clock line of the one clock line and the second clock line and the second end of the second target capacitor. The charge pump circuit described in. The plurality of rectifying elements includes a first rectifying element to an nth rectifying element (n is an integer of 3 or more), and the first, second,..., (from the voltage input terminal to the voltage output terminal). n-1), the plurality of rectifying elements are directly connected in the order of the n-th rectifying element,
A first end of a connection node between the (n-1)th rectifying element and the nth rectifying element or a connection node between the (n-2)th rectifying element and the (n-1)th rectifying element of the plurality of capacitors. The charge pump circuit according to claim 1, wherein a capacitor to which is connected is included in the target capacitor. A first clock line to which the first clock signal having a predetermined reference amplitude is applied;
A second clock line having a second clock signal having the reference amplitude and having a phase opposite to that of the first clock signal;
A second end of the asymmetric capacitor is connected to the first clock line or the second clock line to receive the first clock signal or the second clock signal;
The amplitude reduction unit is provided between the target capacitor and one of the first clock line and the second clock line,
The amplitude reduction unit supplies a clock signal, which is in phase with the first clock signal or the second clock signal and has an amplitude smaller than the reference amplitude, to the second end of the target capacitor. The charge pump circuit according to claim 5. The amplitude reduction unit includes a depletion type MOSFET inserted between one of the first clock line and the second clock line and a second end of the target capacitor. Item 7. The charge pump circuit according to item 6. 8. The charge pump circuit according to claim 1, wherein each rectifying element is composed of a diode-connected MOSFET or is composed of a diode. A semiconductor device comprising a semiconductor integrated circuit including the charge pump circuit according to claim 1. A charge pump circuit according to claim 1;
A memory unit capable of storing data,
A semiconductor memory device, wherein data is written to the memory section by using an output voltage of the charge pump circuit. A semiconductor memory device according to claim 10.
An electric device, comprising: a signal processing device connected to the semiconductor memory device, which outputs a command for instructing the semiconductor memory device to write or read data.

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