JP2020161721A - Semiconductor device - Google Patents

Abstract

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device comprises an input/output pad electrode PD1, a protection element ESD1 formed in a p-type well region PW, an n-type well region NW arranged so as to surround the p-type well region PW, an n-type guard ring NH which is formed in the n-type well region NW and arranged so as to surround the p-type well region PW, power potential wirings VDD1 and VDD2, and a reference potential wiring GND1. The protection element ESD1 is composed of a plurality of n-type unit transistors UTN arranged in a matrix. An n-type drain region ND of the n-type unit transistor UTN is connected to the input-output pad electrode PD1, and an n-type source region NS is connected to the reference potential wiring GND1. In an input/output cell CL1, the n-type guard ring NH is connected to the power potential wiring VDD2, but is not connected to the power potential wiring VDD1.SELECTED DRAWING: Figure 8

Description

The present invention relates to a semiconductor device, and relates to a technique effective by applying to a semiconductor device including, for example, a protective element that protects an internal circuit from electrostatic breakdown.

Japanese Patent Application Laid-Open No. 2008-78354 (Patent Document 1) describes an internal circuit arranged in the central portion of the semiconductor chip, a plurality of input / output cells arranged around the internal circuit, and an outer peripheral portion of the semiconductor chip. A semiconductor device including a plurality of arranged pads is disclosed.

Japanese Unexamined Patent Publication No. 2008-78354

The input / output cell is provided with a protective element that protects the internal circuit from electrostatic damage.

In the semiconductor device under consideration by the inventor of the present application, one protection element is composed of a plurality of unit transistors connected in parallel. As semiconductor devices become finer, the electrostatic resistance of individual unit transistors decreases, making them more susceptible to thermal breakdown. As will be described later, it has been found that when a specific unit transistor constituting one protective element is thermally destroyed, sufficient electrostatic resistance cannot be ensured as the protective element, and the reliability of the semiconductor device is lowered.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

The semiconductor device in one embodiment includes an input / output pad electrode, a protective element formed in a p-type well region, an n-type well region arranged so as to surround the p-type well region, and an n-type well region. It is provided with an n-type guard ring formed in the above and arranged so as to surround the p-type well region, a first power supply potential wiring and a second power supply potential wiring, and a reference potential wiring. The protection element is composed of a plurality of n-type unit transistors arranged in a matrix, the drain region of the n-type unit transistor is connected to the input / output pad electrode, and the source region is connected to the reference potential wiring. Then, in the input / output cell CL1, the n-type guard ring is connected to the second power supply potential wiring, but is not connected to the first power supply potential wiring.

According to one embodiment, the reliability of the semiconductor device can be improved.

It is a top view of the semiconductor device of this embodiment. It is a top view of the input / output cell of the semiconductor device of the study example. It is sectional drawing in X1-X1 of FIG. It is sectional drawing in X2-X2 of FIG. It is sectional drawing in X3-X3 of FIG. It is a main part equivalent circuit diagram of the semiconductor device of the study example. It is operation explanatory drawing of the semiconductor device of the study example. It is a top view of the input / output cell of the semiconductor device of this embodiment. It is sectional drawing in X4-X4 of FIG. It is operation explanatory drawing of the semiconductor device of this embodiment. It is a main part equivalent circuit diagram of the semiconductor device of the modification 1. It is a top view of the input / output cell of the semiconductor device of the modification 1. It is sectional drawing in X5-X5 of FIG. It is sectional drawing of the semiconductor device of the comparative example. It is a top view of the input / output cell of the semiconductor device of the modification 2. It is sectional drawing in X6-X6 of FIG. It is sectional drawing of the semiconductor device of the modification 3.

In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is the other. It is related to some or all of the modified examples, details, supplementary explanations, etc.

In addition, in the following embodiments, when the number of elements (including the number, numerical value, quantity, range, etc.) is referred to, when it is specified in particular, or when it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number.

Furthermore, in the following embodiments, the components (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered to be essential in principle. Needless to say.

Similarly, in the following embodiments, when the shape, positional relationship, etc. of a component or the like is referred to, it is substantially the same unless otherwise specified or when it is considered that it is not clearly the case in principle. It shall include those that are similar to or similar to the shape, etc. This also applies to the above numerical values and ranges.

Further, in all the drawings for explaining the embodiment, the same members are, in principle, given the same reference numerals, and the repeated description thereof will be omitted. In addition, in order to make the drawing easy to understand, hatching may be added even if it is a plan view.

Further, in the p-channel transistor NMOS and the n-channel transistor NMOS, for convenience, one of the semiconductor regions arranged on both sides of the gate electrode is referred to as a source region and the other is referred to as a drain region. Depending on the potential relationship, the source region and the drain region are referred to. It may be reversed from.

(Embodiment)
FIG. 1 is a plan view of the semiconductor device of the present embodiment. As shown in FIG. 1, the semiconductor device includes an internal circuit region RIT, a plurality of cell CLs, and a plurality of pad electrode (terminal) PDs. An internal circuit area RIT is arranged in the central portion of the main surface SUB of the semiconductor substrate SUB, and a plurality of cell CLs are arranged so as to surround the internal circuit area RIT around the internal circuit area RIT. A plurality of pad electrodes PDs are arranged on the outer peripheral portion of the main surface SUBa so as to surround the plurality of cells CL.

In the internal circuit region RIT, an internal circuit ITC composed of a p-channel transistor MIMO and an n-channel transistor NMOS (not shown) is formed, and the internal circuit ITC is supplied with a power supply potential and a reference potential for the internal circuit. The power supply potential wiring (internal power supply potential wiring) VDDL and the reference potential wiring (internal reference potential wiring) GNDL are connected.

On the outer peripheral portion of the internal circuit region RIT, the power supply potential wires VDD1 and VDD2 and the reference potential wires GND1 and GND2 are arranged on the plurality of cells CL. The power supply potential wires VDD1 and VDD2 and the reference potential wires GND1 and GND2 are wirings that supply the power supply potential and the reference potential for input / output to each cell CL, and extend so as to intersect each cell. The power supply potential wiring VDD1 and VDD2 and the reference potential wiring GND1 and GND2 are arranged in a ring shape, and the power supply potential wiring VDD1, the reference potential wiring GND1, the power supply potential wiring VDD2 and the reference are arranged from the pad electrode PD side toward the internal circuit area RIT. The potential wiring GND2 is arranged in this order.

The plurality of pad electrodes PD include input pad electrodes PD1 and PD2, a power potential pad electrode PVD, and a reference potential pad electrode PDG. Further, the plurality of cell CLs include input / output cells CL1 and CL2, and a power supply cell CLP.

The input / output cell CL1 includes a protection element area RA in which the protection element ESD1 is arranged, and a logic circuit area (input / output logic circuit area) RB in which the logic circuit (input / output logic circuit) ESL1 is arranged. Similarly, the input / output cell CL2 includes a protection element region RA in which the protection element ESD2 is arranged, and a logic circuit region (input / output logic circuit region) RB in which the logic circuit (input / output logic circuit) ESL2 is arranged. Further, a power clamp circuit PC is arranged in the power cell CLP. Further, in the power cell CLP, the power potential wirings VDD1 and VDD2 are directly connected to each other, and the reference potential wirings GND1 and GND2 are also directly connected to each other. Here, the direct connection means connecting with a conductor layer, wiring, or the like without interposing a switch element between them. Note that the term "connection" simply means a direct connection.

Next, the room for improvement in the study example will be described with reference to FIGS. 2 to 7. The study example is a technique having a problem found by the inventor of the present application, but is not a known technique. Further, in the embodiment described later, the description of the part common to the study example will be omitted. That is, the explanation of the common part can be substituted for the explanation of the study example. FIG. 2 is a plan view of the input / output cell CL1 of the semiconductor device of the study example, FIG. 3 is a sectional view taken along line X1-X1 of FIG. 2, FIG. 4 is a sectional view taken along line X2-X2 of FIG. 2 is a cross-sectional view taken along the line X3-X3, FIG. 6 is a main equivalent circuit diagram of the semiconductor device of the study example, and FIG. 7 is an operation explanatory view of the semiconductor device of the study example.

As shown in FIG. 2, the input / output cell CL1 includes a protection element ESD1 and a logic circuit ESL1, and the logic circuit ESL1 is composed of a plurality of p-channel transistor MOSFETs and a plurality of n-channel transistors NMOS. The protection element ESD1 and the plurality of n-channel transistors NMOS are formed in the p-type well region (p-type semiconductor region) PW, and the plurality of p-channel transistors MOSFET are formed in the n-type well region (n-type semiconductor region). It is formed in the NW.

The protection element ESD1 is composed of a plurality of n-type unit transistors UTN. The plurality of n-type unit transistors UTN are arranged in a grid pattern in the X direction and the Y direction. The protective element ESD1 is surrounded by a p-type guard ring (p-type semiconductor region) PH formed in a ring shape with a predetermined width. The p-type guard ring PH is formed in the p-type well region PW and is a region for supplying a reference potential to the p-type well region PW. The p-type guard ring PH is connected to the reference potential wiring GND1 by the feeding section PFD3, and the reference potential is fed to the p-type well region PW via the feeding section PFD3.

The n-type unit transistor UTN includes an n-type drain region (n-type semiconductor region) ND and an n-type source region (n-type semiconductor region) NS arranged on both sides of the gate electrode GE and the gate electrode GE, and includes an n-type drain region. The ND is connected to the input / output pad electrode PD1, and the n-type source region NS is connected to the reference potential wiring GND1. A plurality of n-type unit transistors UTNs are arranged in a matrix in the X direction and the Y direction, and are connected in parallel to each other. That is, when the protection element ESD1 is composed of m n-type unit transistors UTN, the current resistance of the protection element ESD1 is m times the current resistance of the n-type unit transistor UTN.

Further, the n-channel transistor NMOS includes a gate electrode GE, an n-type drain region (n-type semiconductor region) ND and an n-type source region (n-type semiconductor region) NS arranged on both sides of the gate electrode GE. As shown in FIGS. 5 and 6, the source region NS of the n-channel transistor NMOS constituting the logic circuit ESL1 is connected to the reference potential wiring GND2. A linear p-type guard ring PH is arranged between the n-channel transistor NMOS and the ring-shaped p-type guard ring PH. The linear p-type guard ring PH is connected to the reference potential wiring GND2 by the feeding unit PFD4. The linear p-type guard ring PH may have a ring shape that surrounds a plurality of n-channel transistor MOSFETs.

Further, the p-channel transistor MOSFET includes a gate electrode GE, a p-type drain region (p-type semiconductor region) PDN arranged on both sides of the gate electrode GE, and a p-type source region (n-type semiconductor region) PS. As shown in FIGS. 4 and 6, the source region PS of the p-channel transistor MOSFET constituting the logic circuit ESL1 is connected to the power supply potential wiring VDD2.

An n-type guard ring NH for supplying a power supply potential to the n-type well region NW is formed in the n-type well region NW, and the n-type guard ring NH is connected to the power supply potential wiring VDD1 by the power feeding unit PFD1. It is connected to the power potential wiring VDD2 by the power feeding unit PFD2.

In a plan view, the n-type guard ring NH is provided in a ring shape so as to surround the protection element ESD1, the p-type guard ring PH, the n-channel transistor NMOS and the p-channel transistor NMOS.

The power feeding unit PFD1 is at the intersection of the n-type guard ring NH and the power potential wiring VDD1 (in other words, the overlapping region), and the power feeding unit PFD2 is at the intersection of the n-type guard ring NH and the power potential wiring VDD2 (in other words). , Overlapping area). Further, the power feeding unit PFD3 is at the intersection (in other words, the overlapping region) of the p-type guard ring PH and the reference potential wiring GND1, and the power feeding unit PFD4 is at the intersection of the p-type guard ring PH and the reference potential wiring GND2 (in other words, the overlapping region). In other words, it is arranged in the overlapping area).

Further, as shown in FIG. 2, the power supply potential wiring VDD1 and the reference potential wiring GND1 are arranged on the protection element ESD1 so as to overlap with the protection element ESD1. The power potential wiring VDD2 and the reference potential wiring GND2 are arranged on the logic circuit ESL1 so as to overlap the logic circuit ESL1. Specifically, the power potential wiring VDD2 is arranged on the p-channel transistor MOSFET so as to overlap the p-channel transistor NMOS, and the reference potential wiring GND2 is on the n-channel transistor NMOS in the n-channel type. It is arranged so as to overlap the transistor NMOS.

As shown in FIG. 3, the n-type unit transistor UTN constituting the protection element ESD1 is formed in the p-type well region PW. The p-type well region PW is formed in the p-type semiconductor substrate SUB via the n-type deep well region (n-type well region, n-type semiconductor region) DNW. The p-type well region PW is surrounded by an n-type well region NW (see FIG. 2), and the n-type well region NW extends from the main surface SUBa in the depth direction of the semiconductor substrate SUB. , N-type deep well region DNW has been reached. That is, the p-type well region PW is electrically separated from the semiconductor substrate SUB by the n-type well region NW and the n-type deep well region DNW.

A p-type guard ring PH is formed in the p-type well region PW, and an n-type guard ring NH is formed in the n-type well region NW. Further, on the main surface SUBa of the semiconductor substrate SUB, a plurality of layers of insulating films (interlayer insulating films) IL1 to IL6, a plurality of layers of metal wirings M1 to M3, and a plurality of layers of plug electrodes PG1 to PG3 are provided. Here, a three-layer metal wiring will be described as an example, but four or more layers of metal wiring may be used. The metal wirings M1 to M3 are made of aluminum or copper, and the plug electrodes PG1 to PG3 are made of tungsten, copper or the like.

As shown in FIG. 3, in the power feeding unit PFD1, the n-type guard ring NH is connected to the power potential wiring VDD1 in this order via the plug electrode PG1, the metal wiring M1, the plug electrode PG2, the metal wiring M2, and the plug electrode PG3. ing.

The n-type unit transistor UTN is arranged on both sides of the gate electrode GE formed on the main surface SUBa of the semiconductor substrate SUB via the gate insulating film GI and in the p-type well region PW on both sides of the gate electrode GE. It includes an n-type drain region ND and an n-type source region NS. A silicide layer SIL is formed on the n-type drain region ND and the n-type source region NS. Further, a silicide layer SIL is also formed on the p-type guard phosphorus PH and the n-type guard ring NH. The metal wiring M1 is connected to the n-type drain region ND via the plug electrode PG1, and the metal wiring M1 is connected to the input / output pad electrode PD1. Further, the metal wiring M1 is connected to the n-type source region NS via the plug electrode PG1, and the metal wiring M1 is connected to the reference potential wiring GND1.

An element separation membrane STI is formed between the n-type unit transistor UTN and the p-type guard phosphorus PH to electrically separate the two. Further, an element separation membrane STI is also formed between the p-type guard phosphorus PH and the n-type guard phosphorus NH to electrically separate the two.

As shown in FIG. 4, the p-channel transistor MOSFET constituting the logic circuit ESL1 is formed in the n-type well region NW. The n-type well region NW is formed in the p-type semiconductor substrate SUB, and a deep well region DNW is interposed between the n-type well region NW and the p-type semiconductor substrate SUB.

The p-channel transistor MOSFET is arranged on both sides of the gate electrode GE formed on the main surface SUBa of the semiconductor substrate SUB via the gate insulating film GI and in the n-type well region NW on both sides of the gate electrode GE. It includes a p-type drain region PDN and a p-type source region PS. A silicide layer SIL is formed on the p-type drain region PDN and the p-type source region PS. Further, the p-type source region PS is connected to the power potential wiring VDD2 in this order via the plug electrode PG1, the metal wiring M1, the plug electrode PG2, the metal wiring M2, and the plug electrode PG3.

As shown in FIG. 5, the n-channel transistor NMOS constituting the logic circuit ESL1 is formed in the p-type well region PW. The p-type well region PW is electrically separated from the semiconductor substrate SUB by the n-type well region NW and the n-type deep well region DNW.

The n-channel transistor NMOS is arranged on both sides of the gate electrode GE formed on the main surface SUBa of the semiconductor substrate SUB via the gate insulating film GI and in the p-type well region PW on both sides of the gate electrode GE. It includes an n-type drain region ND and an n-type source region NS. A silicide layer SIL is formed on the n-type drain region ND and the n-type source region NS. Further, the n-type source region NS is connected to the reference potential wiring GND2 in this order via the plug electrode PG1, the metal wiring M1, the plug electrode PG2, the metal wiring M2, and the plug electrode PG3.

As shown in FIG. 6, for example, the signals input to the input / output pad electrode PD1 from the outside of the semiconductor device are sequentially transferred to the internal circuit ITC via the logic circuit ESL1 and the level shift circuit LS. The logic circuit ESL1 is composed of a p-channel transistor MOSFET and an n-channel transistor NMOS, the p-channel transistor NMOS is connected to the power supply potential wiring VDD2, and the n-channel transistor NMOS is connected to the reference potential wiring GND2. Has been done. The power potential wiring VDD2 is connected to the power potential wiring VDD1, and the power potential pad electrode PDV is connected to the power potential wiring VDD1. The reference potential wiring GND2 is connected to the reference potential wiring GND1, and the reference potential pad electrode PDV is connected to the reference potential wiring GND1.

Further, the internal circuit ITC is connected to the power supply potential wiring VDDL and the reference potential wiring GNDL. The power potential VL applied to the power potential wiring VDDL is lower than the power potential VH applied to the power potential wires VDD1 and VDD2. For example, the power potential VH is 5 [V] or 3.3 [V], and the power potential. The VL is 1.2 [V].

A protective element ESD1 is connected between the input / output pad electrode PD1 and the reference potential wiring GND1. The protective element ESD1 is provided, for example, to prevent destruction of the internal circuit ITC or the like due to electrostatic discharge (hereinafter, referred to as “surge”) invading from the input / output pad electrode PD1 of the semiconductor device. In the input / output cell CL1, the protection element ESD1 is provided between the input / output pad electrode PD1 and the reference potential wiring GND1, but is not provided between the input / output pad electrode PD1 and the power supply potential wiring VDD1. ..

Further, a power clamp circuit PC is connected between the power potential wiring VDD1 and the reference potential wiring GND1. The power clamp circuit PC has, for example, a function of short-circuiting between the power potential wiring VDD1 and the reference potential wiring GND1 when a surge invades the input / output pad electrode PD1.

For example, when a surge invades the input / output pad electrode PD1 with reference to the power potential pad electrode PDV, the internal circuit ITC or the like can be protected by passing a current through the current path I1 shown in FIG. The surge that has entered the input / output pad electrode PD1 escapes to the power potential pad electrode PDV in this order via the protection element ESD1, the reference potential wiring GND1, the power clamp circuit PC, and the power potential wiring VDD1. The current path I1 is the original current path.

Next, with reference to FIG. 7, room for improvement of the study example clarified by the study of the inventor of the present application will be described. In the equivalent circuit diagram shown in FIG. 7, the NPN-type parasitic transistor BiP1 is composed of an n-type drain region ND and an n-type source region NS of an n-type unit transistor UTN and a p-type well region PW, and is an NPN-type parasitic transistor. The transistor BiP2 is composed of an n-type drain region ND, an n-type well region NW, and a p-type well region PW.

First, the original current path I1 will be described. When a surge enters the input / output pad electrode PD1, the PN junction between the n-type drain region ND and the p-type well region PW of the n-type unit transistor breaks down, and the breakdown current flows into the p-type well region PW. Then, when the base potential of the parasitic transistor BiP1 rises due to the parasitic resistance R1 of the p-type well region PW and exceeds the threshold voltage Vbe, a current flows between the collector and the emitter of the parasitic transistor BiP1. That is, the surge that has entered the input / output pad electrode PD1 escapes to the power potential pad electrode PDV via the protection element ESD1, the reference potential wiring GND1, the power clamp circuit PC, and the power potential wiring VDD1.

According to the study by the inventor of the present application, it has been found that an unexpected current path I2 is generated in addition to the original current path I1. That is, when the base potential of the parasitic transistor BiP2 rises due to the above-mentioned breakdown current and exceeds the threshold voltage Vbe, a current flows from the input / output pad electrode PD1 to the power supply potential pad electrode PDV via the parasitic transistor BiP2. As the n-type unit transistor UTN becomes finer, the current withstandability of the n-type unit transistor UTN decreases. Therefore, an unexpected current path I2 is generated in addition to the original current path I1, resulting in a large amount of current. It was found that the n-type unit transistor UTN was thermally destroyed.

Further, thermal breakdown occurs in the n-type unit transistor UTN arranged in the vicinity of the input / output pad electrode PD1 and the feeding portion PFD1 of the power supply potential wiring VDD1 among the plurality of n-type unit transistors UTN shown in FIG. It turned out to be. In the case of the n-type unit transistor UTN close to the feeding unit PFD1, it is presumed that the base potential of the parasitic transistor BiP2 easily exceeds the threshold voltage Vbe because the parasitic resistance connected to the emitter of the parasitic transistor BiP2 is small. ..

If a part of the plurality of n-type unit transistors UTN constituting the protection element ESD1 is destroyed, the current resistance of the protection element ESD1 is lowered, so that the destruction of the internal circuit ITC or the like due to the surge cannot be prevented, and the reliability of the semiconductor device is increased. Decreases.

In this embodiment, the above-mentioned room for improvement has been devised, and the contents thereof will be described below. 8 is a plan view of the input / output cell CL1 of the semiconductor device of the present embodiment, FIG. 9 is a cross-sectional view of X4-X4 of FIG. 8, and FIG. 10 is an operation explanatory view of the semiconductor device of the present embodiment. is there.

As shown in FIG. 8, the input / output cell CL1 includes a protection element ESD1, a p-type guard ring PH that surrounds the protection element ESD1 in a plan view, an n-channel transistor NMOS and a p-channel transistor for the logic circuit ESL1. It includes a NMOS and an n-type guard ring NH that surrounds the protection element ESD1 and the n-channel transistor NMOS and the p-channel transistor NMOS in plan view. The difference between the input / output cell CL1 and the input / output cell CL1 of the study example is that the power feeding unit PFD1 is not provided at the intersection of the n-type guard ring NH and the power potential wiring VDD1. For convenience, the intersection of the n-type guard ring NH and the power potential wiring VDD1 in which the power feeding portion PFD1 is arranged in the study example is referred to as the A portion. That is, in the input / output cell CL1 of the semiconductor device of the present embodiment, the n-type guard ring NH is not connected to the power potential wiring VDD1. However, the n-type guard ring NH is connected to the power supply potential wiring VDD2 in the power feeding unit PFD2 arranged apart from the protection element ESD1 and the A unit. For example, the size of the input / output cell CL1 is about 50 μm in the X direction and about 60 to 80 μm in the Y direction.

As shown in FIG. 9, the A portion and the feeding portion PFD2 are connected by a laminated structure of an n-type well region NW, an n-type guard ring NH, and a silicide layer SIL. Then, in the power feeding unit PFD2, the n-type well region NW, the n-type guard ring NH, and the silicide layer SIL are connected to the power potential wiring VDD2.

That is, as shown in FIG. 10, the wiring resistor R2 is inserted between the A portion and the feeding portion PFD2. Here, the wiring resistor R2 can be regarded as the wiring resistance of the silicide layer SIL from the A portion to the feeding portion PFD2. This is because if the specific resistors of the n-type well region NW, the n-type guard ring NH, and the silicide layer SIL constituting the laminated structure are the specific resistors r1, r2, and r3, respectively, the relationship of r3 << r1 and r2 is established. Is. For example, the wiring resistance R2 can be about 10 [Ω].

As shown in FIG. 10, since the wiring resistor R2 is connected in series to the emitter of the parasitic transistor BiP2, the base potential of the parasitic transistor BiP2 exceeds the threshold value Vbe even if a breakdown current flows in the p-type well region PW. Can be prevented. That is, it is possible to prevent the current flowing from the input / output pad electrode PD1 to the power potential pad electrode PDV in the unexpected current path I2. Therefore, it is possible to prevent thermal destruction of the n-type unit transistor UTN arranged in the vicinity of the A portion and the input / output pad electrode PD1 shown in FIG. Further, since it is possible to prevent a decrease in the current resistance of the protection element ESD1 due to thermal destruction of a part of the n-type unit transistor UTN, the reliability of the semiconductor device can be improved.

<Modification example 1>
Modification 1 is a modification of the above embodiment, FIG. 11 is a main equivalent circuit diagram of the semiconductor device of modification 1, and FIG. 12 is an input / output cell CL1 and CL2 of the semiconductor device of modification 1. The plan view and FIG. 13 are cross-sectional views taken along the line X5-X5 of FIG. The first modification is an example in which the input / output cell CL2 including the protection element ESD2 having a CMOS structure is arranged adjacent to the input / output cell CL1 as shown in FIGS. 1 and 12.

As shown in FIG. 11, the input / output cell CL2 is a protection element composed of a logic circuit ESL2 composed of a p-channel transistor NMOS and an n-channel transistor NMOS, an n-type unit transistor UTN, and a p-type unit transistor UTP. Includes ESD2. For example, the signals input to the input / output pad electrode PD2 from the outside of the semiconductor device are sequentially transferred to the internal circuit ITC via the logic circuit ESL2 and the level shift circuit LS.

A protection element ESD2 composed of an n-type unit transistor UTN is connected between the input / output pad electrode PD2 and the reference potential wiring GND1, and a p-type unit transistor is connected between the input / output pad electrode PD2 and the power supply potential wiring VDD1. A protective element ESD2 made of UTP is connected.

As shown in FIG. 12, the input / output pad electrode PD2 is connected to the input / output cell CL2, the input / output pad electrode PD2 is adjacent to the input / output pad electrode PD1 in the X direction, and the input / output cell CL2 is It is adjacent to the input / output cell CL1. Here, "adjacent" means that no other pad electrode is inserted between the two pad electrodes, or that no other cell is inserted between the two input / output cells.

As shown in FIG. 12, the protection element ESD2 includes a p-type protection element ESD2 composed of a plurality of p-type unit transistors UTP and an n-type protection element ESD2 composed of a plurality of n-type unit transistors UTN. Including. The p-type protection element ESD2 and the n-type protection element ESD2 may be composed of a plurality of p-type unit transistors UTP and a plurality of n-type unit transistors UTN arranged in a matrix in the X and Y directions, respectively. Good.

The plurality of p-type unit transistors UTP are provided in the n-type well region NW, and an n-type guard ring NH surrounding the plurality of p-type unit transistors UTP is formed in the n-type well region NW. A power feeding unit PFD5 is provided at the intersection of the n-type guard ring NH and the power supply potential wiring VDD1, and the n-type guard ring NH is connected to the power supply potential wiring VDD1 in the power supply unit PFD5.

A plurality of n-type unit transistors UTNs are provided in the p-type well region PW, and a p-type guard ring PH surrounding the plurality of n-type unit transistors UTNs is formed in the p-type well region PW. A feeding portion PFD3 is provided at the intersection of the p-type guard ring PH and the reference potential wiring GND1, and the p-type guard ring PH is connected to the reference potential wiring GND1 in the feeding portion PFD3. Further, an n-channel transistor NMOS that constitutes a logic circuit ESL2 is also formed in the p-type well region PW.

Further, an n-type well region NW is arranged so as to surround the p-type well region PW, and in the n-type well region NW, in addition to a plurality of p-type unit transistors UTP, a logic circuit ESL2 is formed. A channel-type transistor MOSFET is also formed. Further, in the n-type well region NW, a p-type guard ring PH and an n-type guard ring NH surrounding the p-channel transistor MOSFET and the n-channel transistor nMOS constituting the logic circuit ESL2 are provided. The n-type guard ring NH is connected to the power supply potential wiring VDD2 in the power feeding unit PFD2.

As shown in FIG. 13, a deep well region DNW is provided below the n-type well region NW included in the input / output cell CL2. Further, the n-type guard ring NH of the A portion of the input / output cell CL1 and the n-type guard ring NH of the power feeding portion PFD5 of the input / output cell CL2 are electrically connected in the n-type well region NW.

Therefore, in order to prevent the current flowing in the unexpected current path I2 of the above-mentioned study example, it is important to separate the power feeding unit PFD5 of the input / output cell CL2 from the A part of the input / output cell CL1 by a desired distance D. Is. In other words, it is necessary to separate the n-type guard ring NH of the input / output cell CL2 from the n-type guard ring NH of the input / output cell CL2 by a desired distance D in the lower part of the power potential wiring VDD1.

That is, the wiring resistance R3 of the n-type well region NW from the n-type guard ring NH of the input / output cell CL1 to the n-type guard ring NH of the input / output cell CL2 is transferred from the A portion to the power supply portion PFD2 described in FIG. It is important to make it larger than the wiring resistance R2 of the silicide layer SIL. Since the specific resistance of the n-type well region NW is larger than the specific resistance of the silicide layer SIL, the distance D can be made smaller than the distance from the A portion to the feeding portion PFD2 in FIGS. 8 and 9. Incidentally, the distance D can be about 10 μm.

<Modification 2>
The modification 2 is a modification of the above embodiment, and is an example in which the input / output cell CL2 including the protection element ESD2 having a CMOS structure is arranged adjacent to the input / output cell CL1 as in the modification 1. is there. 14 is a cross-sectional view of the semiconductor device of the comparative example, FIG. 15 is a plan view of the semiconductor device of the modified example 2, and FIG. 16 is a cross-sectional view of X6-X6 of FIG.

As shown in FIG. 14, when the input / output cell CL2 including the protection element ESD2 having a CMOS structure is arranged adjacent to the input / output cell CL1, in other words, the n-type constituting the protection element ESD1 of the input / output cell CL1. When the unit transistor UTN and the p-type unit transistor UTP constituting the protection element ESD2 of the input / output cell CL2 are arranged adjacent to each other, a thyristor structure including the parasitic transistors BiP3 and BiP4 is built in the semiconductor device. Then, there is a possibility that a latch-up phenomenon occurs in which a current continues to flow from the power potential pad electrode PDV toward the reference potential pad electrode PDG.

The PNP-type parasitic transistor BiP3 uses the p-type source region PS of the p-type unit transistor UTP of the input / output cell CL2 as an emitter and the p-type well region PW of the n-type unit transistor UTN of the input / output cell CL1 as a collector. Based on the n-type well region NW in which the p-type unit transistor UTP of the output cell CL2 is formed. Further, the NPN type parasitic transistor BiP4 collects the n-type well region NW in which the p-type unit transistor UTP of the input / output cell CL2 is formed, and emits the n-type source region NS of the n-type unit transistor UTN of the input / output cell CL1. Based on the p-type well region PW in which the n-type unit transistor UTN of the input / output cell CL1 is formed.

When the power potential is supplied to the n-type guard ring NH from the power potential wiring VDD2, the wiring resistor R2 is interposed between the A unit and the above-mentioned power supply unit PFD2. On the other hand, the power potential is supplied to the p-type source region PS and the n-type gate ring NH of the p-type unit transistor UTP from the power potential wiring VDD1 arranged therein. Due to the influence of the wiring resistor R2, a potential difference is likely to occur between the p-type source region PS (emitter of the parasitic transistor BiP3) of the p-type unit transistor UTP and the n-type well region NW (base of the parasitic transistor BiP3). Then, the base current of the parasitic transistor BiP3 is generated, and the parasitic transistor BiP3 is turned on. When the parasitic transistor BiP3 is turned on, the collector current of the parasitic transistor BiP3 raises the base potential of the parasitic transistor BiP4, so that the parasitic transistor BiP4 is turned on and a latch-up phenomenon occurs.

As shown in FIGS. 15 and 16, in the semiconductor device of the second modification, a p-type well region PW is provided between the input / output cells CL1 and CL2, and the n-type well region NW and the input / output cell CL2 of the input / output cell CL1 are provided. Is separated from the n-type well region NW. Further, a p-type guard ring PH is provided on the surface of the p-type well region PW and connected to the reference potential pad electrode PDG to supply a reference potential to the p-type guard ring PH. The n-type well region NW of the input / output cell CL1 and the n-type well region NW of the input / output cell CL2 may be separated by a p-type semiconductor substrate SUB without providing the p-type well region PW.

With such a configuration, even if the PNP type parasitic transistor BiP3 is turned on, the collector current of the parasitic transistor BiP3 will be the reference potential pad electrode PDG via the p-type well region PW and the p-type guard ring PH. Therefore, it is possible to prevent the above-mentioned latch-up phenomenon from occurring.

<Modification example 3>
Modification 3 is a modification of the above embodiment. FIG. 17 is a cross-sectional view of the semiconductor device of Modification 3. Modification 3 is an example of reducing the wiring resistance R2 of the above embodiment.

As shown in FIG. 17, the metal wiring M1 is arranged along the n-type guard ring NH from the A portion to the feeding portion PFD2, and the metal wiring M1 is n at the plug electrode PG1 in the A portion and the feeding portion PFD2. It is connected to the type guard ring NH. The specific resistance r4 of the metal wiring M1 is about an order of magnitude lower than the specific resistance r3 of the silicide layer SIL, and can be regarded as r4 << r3. That is, by forming a laminated structure in which the silicide layer SIL and the metal wiring M1 are connected in parallel between the A portion and the feeding portion PFD2, the wiring resistor R4 between the A portion and the feeding portion PFD2 is wired as described above. It can be reduced more than the resistance R2.

Therefore, as compared with the above embodiment, the potential difference between the A unit and the power feeding unit PFD2 can be reduced, so that the occurrence of the latch-up phenomenon described in the second modification can be suppressed.

Although the invention made by the present inventor has been specifically described above based on the embodiment thereof, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say.

In addition, a part of the contents described in the above-described embodiment will be described below.
[Appendix 1]
A first conductive type semiconductor substrate having a main surface,
The first pad electrode and the second pad electrode formed on the main surface,
A first input / output cell formed on the main surface and connected to the first pad electrode, and a second input / output cell connected to the second pad electrode.
A first power supply potential wiring that is arranged so as to intersect the first input / output cell and the second input / output cell and supplies a power supply potential to the second input / output cell.
A second power supply potential wiring that is arranged so as to intersect the first input / output cell and the second input / output cell and supplies the power supply potential to the first input / output cell and the second input / output cell.
A first reference potential wiring that supplies a reference potential to the first input / output cell and the second input / output cell,
An internal circuit region formed on the main surface and arranged on the opposite side of the first pad electrode and the second pad electrode with respect to the first input / output cell and the second input / output cell.
With
The first input / output cell is
The first well region of the first conductive type formed in the semiconductor substrate and
A second well region of a second conductive type, which is a conductive type different from the first conductive type, formed in the semiconductor substrate and arranged so as to surround the first well region in a plan view.
The second conductive type third well region formed in the semiconductor substrate, in contact with the second well region, and arranged between the first well region and the semiconductor substrate in a cross-sectional view,
The first protective element formed in the first well region and
The second conductive type first guard ring formed in the second well region and arranged so as to surround the first well region in a plan view,
Including
The second input / output cell is
The second protective element formed in the second well region and
The second conductive type second guard ring formed in the second well region and surrounding the second protective element in a plan view,
Including
The first power supply potential wiring, the second power supply potential wiring, and the first reference potential wiring are arranged on the first input / output cell and the second input / output cell and extend in the first direction of the main surface. Being there
In the second direction intersecting the first direction, the first power supply potential wiring is arranged closer to the first pad electrode and the second pad electrode than the second power supply potential wiring.
The first protection element is composed of a plurality of first transistors.
The first transistor is
A first gate electrode formed on the main surface of the semiconductor substrate via a first gate insulating film,
On both sides of the first gate electrode, the second conductive type first semiconductor region and the second conductive type second semiconductor region arranged in the first well region,
Including
The second protection element is composed of a plurality of second transistors.
The second transistor is
A second gate electrode formed on the main surface of the semiconductor substrate via a second gate insulating film,
On both sides of the second gate electrode, the first conductive type third semiconductor region and the first conductive type fourth semiconductor region arranged in the second well region,
Including
The first semiconductor region is connected to the first pad electrode and is connected to the first pad electrode.
The second semiconductor region is connected to the first reference potential wiring and is connected to the first reference potential wiring.
The third semiconductor region is connected to the second pad electrode and is connected to the second pad electrode.
The fourth semiconductor region is connected to the first power supply potential wiring, and is connected to the first power supply potential wiring.
In the second direction intersecting the first direction, the first power supply potential wiring is arranged closer to the first pad electrode than the second power supply potential wiring.
In the second input / output cell, the second guard ring is connected to the first power supply potential wiring at the first power feeding unit.
In the first input / output cell, the first guard ring is connected to the second power supply potential wiring at the second power feeding unit, but is not connected to the first power supply potential wiring.
[Appendix 2]
In the semiconductor device described in Appendix 1,
A semiconductor device in which a silicide layer is formed on the surface of the first guard ring.
[Appendix 3]
In the semiconductor device described in Appendix 2,
In the first direction, the first resistance value of the second well region from the first guard ring to the second guard ring is from the region where the first guard ring and the first power supply potential wiring intersect. A semiconductor device having a value larger than the second resistance value of the silicide layer reaching the second feeding portion.

BiP1, BiP2, BiP3, BiP4 Parasitic transistor CL cell CL1, CL2 I / O cell CLP power supply cell DNW deep well region (n-type well region, n-type semiconductor region)
ESD1, ESD2 protection element ESL1, ESL2 logic circuit (input / output logic circuit)
GE gate electrode GI gate insulating film GND1, GND2 Reference potential wiring (reference potential wiring for input / output)
GNDL reference potential wiring (internal reference potential wiring)
I1, I2 current path IL1 to IL6 insulating film (interlayer insulating film)
ITC internal circuit (internal logic circuit)
LS level shift circuit M1, M2, M3 Metal wiring ND n-type drain region (n-type semiconductor region)
NH n-type guard ring (n-type semiconductor region)
NMOS n-channel transistor NS n-type source region (n-type semiconductor region)
NW n-type well region (n-type semiconductor region)
PC power clamp circuit PD pad electrode (terminal)
PD1, PD2 Input / output pad electrode PDG Reference potential pad electrode PDN p-type drain region (p-type semiconductor region)
PDV power potential pad electrode PFD1, PFD2, PFD3, PFD4, PFD5 Feeding part PG1, PG2, PG3 Plug electrode (metal conductor layer)
PH p-type guard ring (p-type semiconductor region)
NMOS p-channel transistor PS p-type source region (p-type semiconductor region)
PW p-type well region (p-type semiconductor region)
R1 Parasitic resistance R2, R3, R4 Wiring resistance (parasitic resistance)
RIT internal circuit area RA protection element area RB logic circuit area (input / output logic circuit area)
SIL ► layer STI element separation film SUB semiconductor substrate SUBa main surface UTN n-type unit transistor UTP p-type unit transistor VDD1, VDD2 Power potential wiring (power potential wiring for input / output)
VDDL power potential wiring (internal power potential wiring)

Claims (8)

A first conductive type semiconductor substrate having a main surface,
The first pad electrode formed on the main surface and
A first input / output cell formed on the main surface and connected to the first pad electrode,
The first power supply potential wiring arranged so as to intersect the first input / output cell,
A second power potential wiring that is arranged so as to intersect the first input / output cell and supplies a power potential to the first input / output cell.
A first reference potential wiring that is arranged so as to intersect the first input / output cell and supplies a reference potential to the first input / output cell.
An internal circuit region formed on the main surface and arranged on the opposite side of the first pad electrode with respect to the first input / output cell.
With
The first input / output cell is
The first well region of the first conductive type formed in the semiconductor substrate and
A second well region of a second conductive type, which is a conductive type different from the first conductive type, formed in the semiconductor substrate and arranged so as to surround the first well region in a plan view.
The second conductive type third well region formed in the semiconductor substrate, in contact with the second well region, and arranged between the first well region and the semiconductor substrate in a cross-sectional view,
The first protective element formed in the first well region and
The second conductive type first guard ring formed in the second well region and arranged so as to surround the first well region in a plan view,
Including
The first power supply potential wiring, the second power supply potential wiring, and the first reference potential wiring are arranged on the first input / output cell and extend in the first direction of the main surface.
The first power potential wiring is arranged closer to the first pad electrode than the second power potential wiring.
The first protective element is composed of a plurality of first transistors arranged in a matrix in the first direction and the second direction intersecting the first direction.
The first transistor is
A first gate electrode formed on the main surface of the semiconductor substrate via a first gate insulating film,
On both sides of the first gate electrode, the second conductive type first semiconductor region and the second conductive type second semiconductor region arranged in the first well region,
Including
The first semiconductor region is connected to the first pad electrode and is connected to the first pad electrode.
The second semiconductor region is connected to the first reference potential wiring and is connected to the first reference potential wiring.
In the first input / output cell, the first guard ring is connected to the second power supply potential wiring at the first power feeding unit, but is not connected to the first power supply potential wiring. In the semiconductor device according to claim 1,
In a plan view, the first guard ring has a ring shape and has a ring shape.
A semiconductor device in which the first power supply potential wiring and the second power supply potential wiring are connected to each other outside the first guard ring. In the semiconductor device according to claim 1,
A semiconductor device in which a silicide layer is formed on the surface of the first guard ring. In the semiconductor device according to claim 1,
The first power feeding unit
A first plug electrode arranged on the first guard ring and connected to the first guard ring,
A first metal wiring arranged on the first plug electrode and connected to the first plug electrode,
Including
A semiconductor device in which the first guard ring is connected to the second power supply potential wiring via the first plug electrode and the first metal wiring. In the semiconductor device according to claim 4,
The first input / output cell includes a second plug electrode arranged on the first guard ring in a region where the first guard ring and the first power supply potential wiring intersect.
A semiconductor device in which the first metal wiring extends along the first guard ring and is connected to the second plug electrode. In the semiconductor device according to claim 1,
The first input / output cell further includes a second transistor formed in the second well region.
The second transistor is
A second gate electrode formed on the main surface of the semiconductor substrate via a second gate insulating film,
On both sides of the second gate electrode, the first conductive type third semiconductor region and the first conductive type fourth semiconductor region arranged in the second well region,
Including
The third semiconductor region is a semiconductor device connected to the second power supply potential wiring. In the semiconductor device according to claim 6,
In the second direction, the first reference potential wiring is a semiconductor device arranged between the first power supply potential wiring and the second power supply potential wiring. In the semiconductor device according to claim 1,
further,
The second pad electrode formed on the main surface and
A second input / output cell adjacent to the first input / output cell in the first direction and connected to the second pad electrode.
With
The second input / output cell is
A fourth well region of the second conductive type formed in the semiconductor substrate and arranged apart from the second well region in the first direction.
The second protective element formed in the fourth well region and
The second conductive type second guard ring formed in the fourth well region and surrounding the second protective element in a plan view,
The first conductive type fifth well region formed in the semiconductor substrate and arranged between the second well region and the fourth well region in a plan view,
Including
The second protection element is composed of a plurality of third transistors.
The third transistor is
A third gate electrode formed on the main surface of the semiconductor substrate via a third gate insulating film,
On both sides of the third gate electrode, the first conductive type fifth semiconductor region and the first conductive type sixth semiconductor region arranged in the fourth well region,
Including
The fifth semiconductor region is connected to the second pad electrode, and is connected to the second pad electrode.
The second guard ring and the sixth semiconductor region are connected to the first power supply potential wiring.
The fifth well region is a semiconductor device connected to the first reference potential wiring.