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JP2020155474A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2020155474A
JP2020155474A JP2019050061A JP2019050061A JP2020155474A JP 2020155474 A JP2020155474 A JP 2020155474A JP 2019050061 A JP2019050061 A JP 2019050061A JP 2019050061 A JP2019050061 A JP 2019050061A JP 2020155474 A JP2020155474 A JP 2020155474A
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wiring
semiconductor device
semiconductor
semiconductor chips
thickness direction
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JP7222481B2 (en
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作井　康司
Koji Sakui
康司 作井
大場　隆之
Takayuki Oba
隆之 大場
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Honda Motor Co Ltd
Tokyo Institute of Technology NUC
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Tokyo Institute of Technology NUC
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Abstract

To provide a semiconductor device capable of achieving a high capacity of a built-in capacitor while suppressing an increase in a substrate area.SOLUTION: A semiconductor device 100 includes a plurality of semiconductor chips 101 arranged in a thickness direction T and a first through wire 107 and a second through wire 108 penetrating through the plurality of semiconductor chips 101 in the thickness direction T. One of two conductor layers 107, 108 constituting each semiconductor chip 101 and adjacent to each other in the thickness direction T is connected with a first through wire 102 and the other is connected with a second through wire 103.SELECTED DRAWING: Figure 1

Description

本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.

腕時計等のウェアラブルデバイスには、信号処理のためのＣＰＵ、メモリ、センサ等の素子が集積されている（特許文献１参照）。これらの素子は、蓄電器（大容量キャパシタ回路）に蓄えられた電力を使用して動作するように構成されている。また、多数の素子が集積されているウェアラブルデバイスには、素子の影響による電源電圧の不安定化を防ぐことを目的として、安定化キャパシタが備わっている。 In a wearable device such as a wristwatch, elements such as a CPU, a memory, and a sensor for signal processing are integrated (see Patent Document 1). These elements are configured to operate using the power stored in the power storage (large-capacity capacitor circuit). In addition, a wearable device in which a large number of elements are integrated is provided with a stabilizing capacitor for the purpose of preventing instability of the power supply voltage due to the influence of the elements.

特開２００６−１７９５６４号公報Japanese Unexamined Patent Publication No. 2006-179564

素子を高機能化、高集積化しようとすると、その消費電力を賄い、電源安定化の機能を高めるために、蓄電器、安定化キャパシタ等の内蔵キャパシタの大容量化が必要となり、その結果として、半導体チップ面積が増大し、コスト増加を招くことが問題になっている。 In order to increase the functionality and integration of elements, it is necessary to increase the capacity of built-in capacitors such as capacitors and stabilized capacitors in order to cover the power consumption and enhance the function of power supply stabilization. As a result, The problem is that the area of the semiconductor chip increases, leading to an increase in cost.

本発明は上記事情に鑑みてなされたものであり、基板面積の増大を抑えつつ、内蔵キャパシタを大容量化することが可能な、半導体装置を提供することを目的とする。 The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of increasing the capacity of an internal capacitor while suppressing an increase in a substrate area.

上記課題を解決するため、本発明は以下の手段を採用している。 In order to solve the above problems, the present invention employs the following means.

（１）本発明の一態様に係る半導体装置は、厚み方向に並ぶ複数の半導体チップと、複数の前記半導体チップを、前記厚み方向に貫通する第一貫通配線および第二貫通配線と、を有し、各半導体チップを構成し、前記厚み方向に隣接する二つの導電体層のうち、一方が前記第一貫通配線に接続され、他方が前記第二貫通配線に接続されている。 (1) The semiconductor device according to one aspect of the present invention includes a plurality of semiconductor chips arranged in the thickness direction, and a first through wiring and a second through wiring that penetrate the plurality of the semiconductor chips in the thickness direction. Of the two conductor layers adjacent to each other in the thickness direction of each semiconductor chip, one is connected to the first through wiring and the other is connected to the second through wiring.

（２）前記（１）に記載の半導体装置において、複数の前記半導体チップ同士が、直接または中間層を挟んで密着していることが好ましい。 (2) In the semiconductor device according to (1), it is preferable that a plurality of the semiconductor chips are in close contact with each other directly or with an intermediate layer interposed therebetween.

（３）前記（１）または（２）のいずれかに記載の半導体装置において、前記第一貫通配線および前記第二貫通配線が、いずれも銅を主成分として含む材料によって構成されていることが好ましい。 (3) In the semiconductor device according to any one of (1) or (2), the first through wiring and the second through wiring are both made of a material containing copper as a main component. preferable.

（４）前記（１）〜（３）のいずれか一つに記載の半導体装置において、複数の前記半導体チップのそれぞれに、リングオシレータ、ＡＤコンバータが搭載され、二つの前記導電体層に対し、電気的に接続されていてもよい。 (4) In the semiconductor device according to any one of (1) to (3), a ring oscillator and an AD converter are mounted on each of the plurality of semiconductor chips, and the two conductor layers are subjected to. It may be electrically connected.

（５）前記（１）〜（３）のいずれか一つに記載の半導体装置において、複数の半導体チップの厚み方向における一方の側に、リングオシレータ、ＡＤコンバータが搭載されたベースロジックチップをさらに有し、それぞれの前記半導体チップの二つの前記導電体層に対し、前記第一貫通配線および前記第二貫通配線を介して電気的に接続されていてもよい。 (5) In the semiconductor device according to any one of (1) to (3) above, a base logic chip on which a ring oscillator and an AD converter are mounted is further mounted on one side of a plurality of semiconductor chips in the thickness direction. It may be electrically connected to the two conductor layers of each of the semiconductor chips via the first through wiring and the second through wiring.

本発明の半導体装置では、第一貫通配線に接続された各半導体チップの一方の導電体層同士が等電位となり、かつ、第二貫通配線に接続された各半導体チップの他方の導電体層同士が等電位となる。したがって、各半導体チップにおいて、一方の導電体層と他方の導電体層とで構成されるキャパシタは、他の全ての半導体チップのキャパシタと並列接続されることになるため、合成容量が、各半導体チップのキャパシタの容量を足し合わせた大きさになる。本発明の半導体装置は、半導体チップをいくつ重ねても基板面積が変わることはないため、多層構造とすることにより、基板面積の増大を抑えつつ、内蔵キャパシタを大容量化することが可能となる。 In the semiconductor device of the present invention, one conductor layer of each semiconductor chip connected to the first through wiring has an equal potential, and the other conductor layers of each semiconductor chip connected to the second through wiring have equal potentials. Is equal potential. Therefore, in each semiconductor chip, the capacitor composed of one conductor layer and the other conductor layer is connected in parallel with the capacitors of all the other semiconductor chips, so that the combined capacity of each semiconductor is increased. The size is the sum of the capacities of the chip capacitors. Since the substrate area of the semiconductor device of the present invention does not change no matter how many semiconductor chips are stacked, the multilayer structure makes it possible to increase the capacity of the built-in capacitor while suppressing the increase in the substrate area. ..

本発明の一実施形態に係る半導体装置とその実装基板の断面図である。It is sectional drawing of the semiconductor device which concerns on one Embodiment of this invention and its mounting substrate. 図１の半導体装置を、その積層方向から平面視した図である。FIG. 5 is a plan view of the semiconductor device of FIG. 1 from the stacking direction. 変形例１に係る半導体装置を、その積層方向から平面視した図である。It is a figure which viewed the semiconductor device which concerns on modification 1 from the stacking direction in a plan view. 変形例２に係る半導体装置を、その積層方向から平面視した図である。It is a figure which looked at the semiconductor device which concerns on modification 2 from the stacking direction.

以下、本発明を適用した実施形態に係る半導体装置について、図面を用いて詳細に説明する。なお、以下の説明で用いる図面は、特徴をわかりやすくするために、便宜上特徴となる部分を拡大して示している場合があり、各構成要素の寸法比率などが実際と同じであるとは限らない。また、以下の説明において例示される材料、寸法等は一例であって、本発明はそれらに限定されるものではなく、その要旨を変更しない範囲で適宜変更して実施することが可能である。 Hereinafter, the semiconductor device according to the embodiment to which the present invention is applied will be described in detail with reference to the drawings. In addition, in the drawings used in the following description, in order to make the features easy to understand, the featured parts may be enlarged for convenience, and the dimensional ratio of each component may not be the same as the actual one. Absent. Further, the materials, dimensions, etc. exemplified in the following description are examples, and the present invention is not limited thereto, and the present invention can be appropriately modified without changing the gist thereof.

図１は、本発明の一実施形態に係る半導体装置１００と、半導体装置１００を実装した基板（実装基板）２００の断面図である。半導体装置１００は、厚み方向Ｔに並ぶ複数の半導体チップ１０１と、それらを厚み方向Ｔに貫通する第一貫通配線１０２および第二貫通配線１０３と、を有する。半導体装置１００は、実装基板２００に対してバンプを介さずに接合されている。 FIG. 1 is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention and a substrate (mounting substrate) 200 on which the semiconductor device 100 is mounted. The semiconductor device 100 includes a plurality of semiconductor chips 101 arranged in the thickness direction T, and a first through wiring 102 and a second through wiring 103 penetrating them in the thickness direction T. The semiconductor device 100 is joined to the mounting substrate 200 without a bump.

半導体チップ１０１は、主に、チップ基板１０４と、チップ基板の一方の主面１０４ａ側に設けられた機能素子（不図示）と、キャパシタ１０５と、それらの隙間を埋める層間絶縁膜１０６と、で構成されている。 The semiconductor chip 101 is mainly composed of a chip substrate 104, a functional element (not shown) provided on one main surface 104a side of the chip substrate, a capacitor 105, and an interlayer insulating film 106 that fills a gap between them. It is configured.

キャパシタ１０５は、平板状の二つの導電体層１０７、１０８を、それぞれの一方の主面１０７ａ、１０８ａ同士が対向するように、かつ略平行になるように設けられている。ここでの導電体層１０７、１０８は、それぞれ、キャパシタ１０５の上部電極、下部電極として機能するものである。 The capacitor 105 is provided with two flat plate-shaped conductor layers 107 and 108 so that one of the main surfaces 107a and 108a faces each other and are substantially parallel to each other. The conductor layers 107 and 108 here function as upper electrodes and lower electrodes of the capacitor 105, respectively.

導電体層１０７、１０８の材料としては、例えば、銅、アルミニウム等の金属、ポリシリコン、シリサイド等が用いられる。層間絶縁膜１０６は、チップ基板１０４と導電体層１０８の間に形成される絶縁体層１０６−１、導電体層１０７と導電体層１０８の間に形成される絶縁体層１０６−２、導電体層１０７より上に形成される絶縁体層１０６−３を有する。絶縁体層１０６−１、１０６−２、１０６−３は、例えば、酸化シリコン（ＳｉＯ２）、酸化アルミニウム（Ａｌ２Ｏ３）等の半導体酸化膜、金属酸化膜等によって構成されていることが好ましい。絶縁体層１０６−２を比誘電率の高い材料で形成することにより、導電体層１０７と導電体層１０８の間のキャパシタ容量を増大させることができる。なお、導電体層１０７、１０８の材料は、半導体装置１００としての合成容量を求める観点から、積層される半導体チップ１０１全体で揃っていることが好ましい。 As the materials of the conductor layers 107 and 108, for example, metals such as copper and aluminum, polysilicon, silicide and the like are used. The interlayer insulating film 106 includes an insulator layer 106-1 formed between the chip substrate 104 and the conductor layer 108, an insulator layer 106-2 formed between the conductor layer 107 and the conductor layer 108, and conductivity. It has an insulator layer 106-3 formed above the body layer 107. The insulator layers 106-1, 106-2, 106-3 may be composed of, for example, a semiconductor oxide film such as silicon oxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ), a metal oxide film, or the like. preferable. By forming the insulator layer 106-2 with a material having a high relative permittivity, the capacitor capacity between the conductor layer 107 and the conductor layer 108 can be increased. The materials of the conductor layers 107 and 108 are preferably aligned in the entire semiconductor chip 101 to be laminated from the viewpoint of obtaining the combined capacity of the semiconductor device 100.

各半導体チップを構成し、厚み方向Ｔに隣接する二つの導電体層１０７、１０８のうち一方の導電体層１０７は、第一貫通配線１０２に対して電気的に接続され、他方の導電体層１０８は、第二貫通配線１０２に対して電気的に接続されている。より詳細には、導電体層１０７の端部に貫通孔１０７Ｈが設けられており、ここに第一貫通配線１０２が挿入され、第一貫通配線１０２の外壁面と、貫通孔１０７Ｈの内壁面とが接触することにより、導電体層１０７と第一貫通配線１０２とが電気的に接続されている。同様に、導電体層１０８の端部に貫通孔１０８Ｈが設けられており、ここに第二貫通配線１０３が挿入され、第二貫通配線１０３の外壁面と、貫通孔１０８Ｈの内壁面とが接触することにより、導電体層１０８と第二貫通配線１０３とが電気的に接続されている。 One of the two conductor layers 107 and 108 constituting each semiconductor chip and adjacent to each other in the thickness direction T is electrically connected to the first through wiring 102, and the other conductor layer 107 is electrically connected to the first through wiring 102. The 108 is electrically connected to the second through wiring 102. More specifically, a through hole 107H is provided at the end of the conductor layer 107, and the first through wiring 102 is inserted therein, and the outer wall surface of the first through wiring 102 and the inner wall surface of the through hole 107H The conductor layer 107 and the first through wiring 102 are electrically connected by the contact with each other. Similarly, a through hole 108H is provided at the end of the conductor layer 108, and the second through wiring 103 is inserted into the through hole 108H, so that the outer wall surface of the second through wiring 103 and the inner wall surface of the through hole 108H come into contact with each other. By doing so, the conductor layer 108 and the second through wiring 103 are electrically connected.

第一貫通配線１０２および第二貫通配線１０３は、少なくとも、半導体装置１００を構成する全半導体チップの厚みの合計以上の長さを有する。これらは、加工性、電気特性、コストの観点から、いずれも、銅のみ、または銅を主成分として約８０％以上含む材料によって、構成されていることが好ましい。第一貫通配線１０２および第二貫通配線１０３の他の材料としては、例えば、タングステン（Ｗ）等も挙げることができる。 The first through wiring 102 and the second through wiring 103 have a length equal to or greater than the total thickness of all the semiconductor chips constituting the semiconductor device 100. From the viewpoint of processability, electrical properties, and cost, it is preferable that these are composed of copper alone or a material containing about 80% or more of copper as a main component. As other materials of the first through wiring 102 and the second through wiring 103, for example, tungsten (W) and the like can be mentioned.

図１では、複数の半導体チップ１０１同士が、互いに離間した状態を示しているが、実用上、これらは直接または中間層（接着剤層等）を挟んで密着していることが好ましい。 Although FIG. 1 shows a state in which a plurality of semiconductor chips 101 are separated from each other, it is practically preferable that they are in close contact with each other directly or with an intermediate layer (adhesive layer or the like) sandwiched between them.

図２は、図１の半導体装置１００を、半導体チップ１０１が並ぶ方向（厚み方向Ｔ）から平面視した図である。ここでは、導電体層１０７、１０８の重なり具合が明示されるように、層間絶縁膜１０６を透明化している。 FIG. 2 is a plan view of the semiconductor device 100 of FIG. 1 from the direction in which the semiconductor chips 101 are arranged (thickness direction T). Here, the interlayer insulating film 106 is made transparent so that the overlapping condition of the conductor layers 107 and 108 is clearly shown.

同平面視において、２つの導電体層１０７、１０８は、互いに重なっている領域Ｒ１と、重なっていない領域Ｒ２とを有し、２つの領域の面積は、互いに反比例の関係にある。キャパシタ１０５の電気容量を大きくするためには、領域Ｒ１の面積を大きくすることが好ましいが、少なくとも第一貫通配線１０２、第二貫通配線１０３が貫通できる分の面積を領域Ｒ２に確保する必要がある。なお、同平面視における導電体層１０７、１０８の面積、および領域Ｒ１、Ｒ２の面積は、積層される半導体チップ１０１ごとに異なっていてもよい。 In the plan view, the two conductive layers 107 and 108, has a region R 1 that overlap each other and a region R 2 that do not overlap, the areas of the two regions is inversely proportional to each other. In order to increase the electric capacity of the capacitor 105, it is preferable to increase the area of the region R 1 , but at least the area that the first through wiring 102 and the second through wiring 103 can penetrate is secured in the region R 2 . There is a need. The areas of the conductor layers 107 and 108 and the areas of the regions R 1 and R 2 in the same plan view may be different for each of the semiconductor chips 101 to be laminated.

第一貫通配線１０２、第二貫通配線１０３は、それぞれ導電体層１０７、１０８に対し、少なくとも１本ずつ設けられていればよいが、電荷の供給速度を向上させる観点、構造を安定化する観点から、図２に示すように複数本を略等間隔で設けることが好ましい。 At least one first through wiring 102 and one second through wiring 103 may be provided for the conductor layers 107 and 108, respectively, but from the viewpoint of improving the charge supply rate and stabilizing the structure. Therefore, as shown in FIG. 2, it is preferable to provide a plurality of wires at substantially equal intervals.

図３は、２つの導電体層１０７、１０８の重なり方に関する変形例１として、半導体装置を図２と同様に平面視した図である。図２では、領域Ｒ１が２つの領域Ｒ２に挟まれている場合について例示しているが、ここでは、領域Ｒ１が全周囲（ここでは４方向）の領域Ｒ２から囲まれた状態になっている。変形例１の構成は、加工上の難しさはあるが、電荷の供給速度を向上させる観点、構造を安定化する観点から好ましい。 FIG. 3 is a plan view of a semiconductor device in the same manner as in FIG. 2 as a modification 1 regarding how the two conductor layers 107 and 108 overlap. In FIG. 2, the case where the region R 1 is sandwiched between the two regions R 2 is illustrated, but here, the region R 1 is surrounded by the region R 2 on the entire circumference (here, four directions). It has become. The configuration of the first modification is preferable from the viewpoint of improving the charge supply rate and stabilizing the structure, although there are some difficulties in processing.

図４は、複数のキャパシターの配置に関する変形例２として、半導体装置を図２、３と同様に平面視した図である。図４では、一つの半導体チップ１０１に、導電体層１０７Ａと導電体層１０８Ａとで構成されるキャパシタ１０５Ａ、導電体層１０７Ｂと導電体層１０８Ｂとで構成されるキャパシタ１０５Ｂが設けられている場合について例示している。二つの導電体層の間に挟まれる絶縁層は共通となる。ここでは、一つの半導体チップ１０１に対し、２つのキャパシタ１０５Ａ、１０５Ｂが設けられている場合について例示しているが、３つ以上のキャパシタが設けられていてもよい。複数のキャパシタの導電体層同士の面積は、揃っていてもよいし、揃っていなくてもよい。 FIG. 4 is a plan view of a semiconductor device in the same manner as in FIGS. 2 and 3 as a modification 2 regarding the arrangement of a plurality of capacitors. In FIG. 4, one semiconductor chip 101 is provided with a capacitor 105A composed of a conductor layer 107A and a conductor layer 108A, and a capacitor 105B composed of a conductor layer 107B and a conductor layer 108B. Is illustrated. The insulating layer sandwiched between the two conductor layers is common. Here, the case where two capacitors 105A and 105B are provided for one semiconductor chip 101 is illustrated, but three or more capacitors may be provided. The areas of the conductor layers of the plurality of capacitors may or may not be the same.

キャパシタ動作に関連するリングオシレータ、ＡＤコンバータ等の機能素子については、複数の半導体チップ１０１のそれぞれに搭載し、二つの導電体層１０７、１０８に対して電気的に接続することができる。 Functional elements such as a ring oscillator and an AD converter related to capacitor operation can be mounted on each of a plurality of semiconductor chips 101 and electrically connected to the two conductor layers 107 and 108.

複数の半導体チップ１０１の厚み方向Ｔにおける一方の側（図１では上側または下側のいずれか）に、これらの機能素子が搭載されたベースロジックチップをさらに有する場合には、別の接続を行うこともできる。すなわち、当該機能素子を、それぞれの半導体チップ１０１の二つの導電体層１０７、１０８に対し、第一貫通配線１０２および第二貫通配線１０３を介して電気的に接続することができる。 If a base logic chip on which these functional elements are mounted is further provided on one side (either the upper side or the lower side in FIG. 1) of the plurality of semiconductor chips 101 in the thickness direction T, another connection is made. You can also do it. That is, the functional element can be electrically connected to the two conductor layers 107 and 108 of the respective semiconductor chips 101 via the first through wiring 102 and the second through wiring 103.

上述した半導体装置は、主に、次の手順で製造することができる。まず、所定の機能素子を搭載した複数の半導体チップを準備し、それぞれの半導体チップに対し、貫通孔の形成が可能な厚さ（５〜１０μｍ程度）になるように、基板側から研磨を行う。 The above-mentioned semiconductor device can be mainly manufactured by the following procedure. First, a plurality of semiconductor chips equipped with predetermined functional elements are prepared, and each semiconductor chip is polished from the substrate side so as to have a thickness (about 5 to 10 μm) capable of forming through holes. ..

次に、研磨された複数の半導体チップを、接着剤を用いて厚み方向に貼り合わせた上で、所定の位置において、エッチング法を用いて、貼り合わせた全半導体チップを貫通する貫通孔を形成する。続いて、形成された貫通孔に対し、スパッタリング法等を用いて導電材料を埋め込むことにより、第一貫通配線１０７、第二貫通配線１０８を形成する。 Next, a plurality of polished semiconductor chips are bonded together in the thickness direction using an adhesive, and then, at a predetermined position, an etching method is used to form a through hole penetrating all the bonded semiconductor chips. To do. Subsequently, the first through wiring 107 and the second through wiring 108 are formed by embedding a conductive material in the formed through holes by using a sputtering method or the like.

最後に、第一貫通配線、第二貫通配線が形成された半導体チップの積層体を、実装基板に取り付けることにより、本実施形態の半導体装置１００を得ることができる。 Finally, the semiconductor device 100 of the present embodiment can be obtained by attaching the laminate of the semiconductor chips on which the first through wiring and the second through wiring are formed to the mounting substrate.

以上により、本実施形態に係る半導体装置１００では、第一貫通配線１０２に接続された各半導体チップ１０１の一方の導電体層１０７同士が等電位となり、かつ、第二貫通配線１０８に接続された各半導体チップ１０１の他方の導電体層１０８同士が等電位となる。したがって、各半導体チップ１０１において、一方の導電体層１０７と他方の導電体層１０８とで構成されるキャパシタ１０５は、他の全ての半導体チップ１０１のキャパシタと並列接続されることになるため、合成容量が、各半導体チップのキャパシタ１０５の容量を足し合わせた大きさになる。本実施形態の半導体装置１００は、半導体チップ１０１をいくつ重ねても基板面積が変わることはないため、多層構造とすることにより、基板面積の増大を抑えつつ、内蔵キャパシタを大容量化することが可能となる。 As described above, in the semiconductor device 100 according to the present embodiment, one of the conductor layers 107 of each semiconductor chip 101 connected to the first through wiring 102 has an equal potential and is connected to the second through wiring 108. The other conductor layers 108 of each semiconductor chip 101 have equal potentials. Therefore, in each semiconductor chip 101, the capacitor 105 composed of one conductor layer 107 and the other conductor layer 108 is connected in parallel with the capacitors of all the other semiconductor chips 101. The capacity is the sum of the capacities of the capacitors 105 of each semiconductor chip. In the semiconductor device 100 of the present embodiment, the substrate area does not change no matter how many semiconductor chips 101 are stacked. Therefore, by adopting a multilayer structure, it is possible to increase the capacity of the built-in capacitor while suppressing an increase in the substrate area. It will be possible.

１００・・・半導体装置
１０１・・・半導体チップ
１０２・・・第一貫通配線
１０３・・・第二貫通配線
１０４・・・チップ基板
１０４ａ・・・チップ基板の一方の主面
１０５・・・キャパシタ
１０６・・・層間絶縁膜
１０７、１０７Ａ、１０７Ｂ、１０８、１０８Ａ、１０８Ｂ・・・導電体層
１０７ａ、１０８ａ・・・導電体層の一方の主面
２００・・・実装基板
Ｒ１、Ｒ２・・・領域
Ｔ・・・厚み方向 100 ... Semiconductor device 101 ... Semiconductor chip 102 ... First through wiring 103 ... Second through wiring 104 ... Chip substrate 104a ... One main surface 105 of the chip substrate ... Capacitor 106 ... Interlayer insulating film 107, 107A, 107B, 108, 108A, 108B ... Conductor layer 107a, 108a ... One main surface of the conductor layer 200 ... Mounting substrate R 1 , R 2 ...・ ・ Region T ・ ・ ・ Thickness direction

Claims (5)

厚み方向に並ぶ複数の半導体チップと、
複数の前記半導体チップを、前記厚み方向に貫通する第一貫通配線および第二貫通配線と、を有し、
各半導体チップを構成し、前記厚み方向に隣接する二つの導電体層のうち、一方が前記第一貫通配線に接続され、他方が前記第二貫通配線に接続されていることを特徴とする半導体装置。 With multiple semiconductor chips lined up in the thickness direction,
It has a first through wiring and a second through wiring that penetrate the plurality of semiconductor chips in the thickness direction.
A semiconductor that constitutes each semiconductor chip and is characterized in that one of two conductor layers adjacent to each other in the thickness direction is connected to the first through wiring and the other is connected to the second through wiring. apparatus. 複数の前記半導体チップ同士が、直接または中間層を挟んで密着していることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the plurality of semiconductor chips are in close contact with each other directly or with an intermediate layer interposed therebetween. 前記第一貫通配線および前記第二貫通配線が、いずれも銅を主成分として含む材料によって構成されていることを特徴とする請求項１または２のいずれかに記載の半導体装置。 The semiconductor device according to claim 1 or 2, wherein the first through wiring and the second through wiring are both made of a material containing copper as a main component. 複数の前記半導体チップのそれぞれに、リングオシレータ、ＡＤコンバータが搭載され、二つの前記導電体層に対し、電気的に接続されていることを特徴とする請求項１〜３のいずれか一項に記載の半導体装置。 The invention according to any one of claims 1 to 3, wherein a ring oscillator and an AD converter are mounted on each of the plurality of semiconductor chips and are electrically connected to the two conductor layers. The semiconductor device described. 複数の半導体チップの厚み方向における一方の側に、
リングオシレータ、ＡＤコンバータが搭載されたベースロジックチップをさらに有し、
それぞれの前記半導体チップの二つの前記導電体層に対し、前記第一貫通配線および前記第二貫通配線を介して電気的に接続されていることを特徴とする請求項１〜３のいずれか一項に記載の半導体装置。 On one side of multiple semiconductor chips in the thickness direction,
It also has a base logic chip equipped with a ring oscillator and AD converter.
Any one of claims 1 to 3, wherein the two conductor layers of each of the semiconductor chips are electrically connected via the first through wiring and the second through wiring. The semiconductor device according to the section.
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