JP2020043181A - Thin film transistor substrate, manufacturing method thereof, and organic el display device using thin film transistor substrate - Google Patents

Abstract

To provide the structure of a TFT substrate suitable for high definition, and a manufacturing method thereof.SOLUTION: A thin film transistor substrate includes a substrate, a semiconductor layer provided on the substrate, and having a channel region and a pair of contact regions sandwiching the channel region, a gate electrode provided in the channel region via a gate insulation layer, an insulation layer covering the semiconductor layer and the gate electrode, and provided with a contact hole, a hard mask layer provided on the insulation layer, and having an opening at a position corresponding to the contact hole, and an upper electrode provided on the hard mask layer and electrically connected with any one of the contact region or the gate electrode via the contact hole, where the bore diameter of the contact hole provided in the insulation layer increases gradually as approaching the upper electrode side from the substrate side.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a thin film transistor substrate, a method for manufacturing the same, and an organic EL display device using the thin film transistor substrate.

Conventionally, a thin film transistor (TFT) substrate has been used for a display device such as an organic EL display panel or a liquid crystal display panel. In a display device, a TFT is used as a switching element, a driving transistor, or the like.
In recent years, a TFT substrate using an oxide semiconductor typified by InGaZnO for a channel layer, as disclosed in Patent Document 1, has been used as a TFT substrate having better performance.

JP 2014-183238 A

  However, the upper insulating layer located on the display element side from the semiconductor (the “upper” here refers to the stacking direction, and does not necessarily indicate vertically upward; the same applies to the following). A contact hole for electrical connection is required. An organic insulating layer also functioning as a planarizing layer is used as the upper insulating layer. However, if a contact hole is formed by a conventional exposure technique, the inner diameter of the contact hole tends to become wider and tapered toward the upper side. Therefore, even if an attempt is made to increase the definition of the display device, there is a problem that it is difficult to increase the definition of the display device because the lower limit of the area per pixel is caused by the contact size.

  The present disclosure has been made in view of the above problems, and has as its object to provide a structure of a TFT substrate suitable for high definition and a manufacturing method thereof.

  A thin film transistor substrate according to one embodiment of the present invention includes a substrate, a semiconductor layer provided over the substrate, having a channel region and a pair of contact regions sandwiching the channel region, and a gate insulating layer in the channel region. A gate electrode provided, an insulating layer covering the semiconductor layer and the gate electrode and having a contact hole provided therein, and a hard mask provided on the insulating layer and provided with an opening at a position corresponding to the contact hole A layer, and an upper electrode provided on the hard mask layer and electrically connected to any of the contact region and the gate electrode via the contact hole, the contact provided on the insulating layer. The inner diameter of the hole gradually increases from the substrate side to the upper electrode side.

  According to the above configuration, since the contact holes are formed using the hard mask, the contact size can be reduced as compared with the case where the contact holes are formed by the exposure technique. Further, since the inner diameter of the contact hole gradually increases as approaching from the substrate side to the upper electrode side, connection failure is less likely to occur as compared with the case where the inner diameter of the contact hole is uniform.

FIG. 2 is a schematic block diagram illustrating a circuit configuration of the organic EL display device 1000 according to the embodiment. FIG. 3 is a schematic circuit diagram showing a circuit configuration in each subpixel 10se of the organic EL display panel 100 used in the organic EL display device 1000 according to the embodiment. FIG. 2 is a schematic cross-sectional view of each organic EL element 10 used in the organic EL display panel 100 according to the embodiment. FIG. 2 is an enlarged partial schematic view of a TFT substrate 11 in the organic EL element 10 according to the embodiment. 5A to 5C are schematic cross-sectional views illustrating states in respective steps in the manufacture of the TFT substrate 11, in which FIGS. 7A to 7C illustrate a step of forming a lower CS electrode 101, and FIG. 7D illustrates a step of forming lower insulating layers 102 and 103. (E) and (f) show a step of forming the semiconductor layer 104. FIGS. 4A to 4C are schematic cross-sectional views illustrating states in respective steps in manufacturing the TFT substrate 11, in which (a) to (c) illustrate steps of forming a gate insulating layer 106 and a gate electrode 107, and (d) illustrates a first inorganic insulating layer. 105 shows a forming step. It is a schematic cross section which shows the state in each process in manufacture of the TFT substrate 11, (a)-(b) shows the formation process of the inorganic insulating layers 108 and 109, (c) shows the formation process of the organic insulating layer 1010. Is shown. 5A to 5C are schematic cross-sectional views illustrating a state in each step in manufacturing the TFT substrate 11, and FIGS. It is a schematic cross section which shows the state in each process in manufacture of the TFT substrate 11, (a) is the first partial etching process of the organic insulating layer 1010, (b) is the second etching process of the hard mask 1101, ( c) shows a second partial etching step of the organic insulating layer 1010. It is a schematic cross section which shows the state in each process in manufacture of the TFT substrate 11, (a) shows the 3rd etching process of the hard mask 1101, and (b) shows the 3rd partial etching process of the organic insulating layer 1010. . It is a schematic cross section which shows the state in each process in manufacture of the TFT substrate 11, (a) shows the 4th etching process of the hard mask 1101, and (b) shows the 4th partial etching process of the organic insulating layer 1010. . It is a schematic cross section which shows the state in each process in manufacture of the TFT substrate 11, (a) shows the fifth etching process of the hard mask 1101, and (b) shows the 5th partial etching process of the organic insulating layer 1010. . It is a schematic cross section which shows the state in each process in manufacture of the TFT substrate 11, (a) shows the etching process of an inorganic insulating layer, (b), (c) shows the formation process of the upper electrode 1102. 4 is a flowchart illustrating a method for manufacturing the TFT substrate 11 according to the embodiment. 5 is a partial flowchart showing a process of forming an organic insulating layer 1010 and a hard mask 1101 according to the embodiment. It is a schematic cross section which shows the state in each process in manufacture of the TFT board | substrate which concerns on a modification, (a) is a formation process of a partial organic insulating layer, (b), (c) is a formation process of an intermediate mask, (d) ) Shows a step of forming a partial organic insulating layer. It is a schematic cross section which shows the state in each process in manufacture of the TFT board | substrate which concerns on a modification, (a), (b) shows the formation process of an intermediate mask, (c) shows the formation process of a partial organic insulating layer. It is a schematic cross section which shows the state in each process in manufacture of the TFT board | substrate which concerns on a modification, a), (b) shows the formation process of a hard mask, and (c) shows the formation process of a contact hole. 11 is a partial flowchart showing a process of forming an organic insulating layer 1010 and a hard mask 1101 according to a modification. It is the partial schematic diagram which expanded the TFT substrate s part in the organic EL element which concerns on another modification.

<< History of One Embodiment of the Present Disclosure >>
In general, a TFT substrate using an oxide semiconductor has a structure in which the upper side of the semiconductor is protected by a stacked structure of an inorganic insulating layer for protecting the semiconductor from hydrogen and an organic insulating layer also serving as a planarization layer. . Then, in order to electrically connect the transistor and the light emitting element formed over the TFT substrate, a contact hole is formed through the insulating layer above the semiconductor, and an upper electrode is formed over the insulating layer.

  Conventionally, a positive photoresist such as a polyimide resin has been used as an organic insulating layer. Since a positive photoresist can remove only a region exposed to light of a specific wavelength such as ultraviolet light with a developer, a contact hole can be easily formed by exposing only a region where a contact hole is to be formed. Can be. However, in the exposure technique using a photomask, semi-exposure is likely to occur near the boundary between the exposure area and the non-exposure area, and when the thickness of the photoresist is large, the semi-exposure area is likely to spread farther from the upper surface. Therefore, as the contact hole approaches the lower surface from the upper surface, the inner diameter tends to be tapered so that the inner diameter becomes narrower. In particular, when the thickness of the organic insulating layer is large, the inner diameter of the contact hole on the insulating layer upper surface side may be excessively large. On the other hand, in an active matrix display panel, a drive transistor is required for each display element, so when trying to reduce the pixel size for higher definition, the size of the contact hole becomes an obstacle to higher definition. sell.

  Therefore, the inventors have conducted intensive studies on a method of manufacturing a TFT substrate and a structure of the TFT substrate so that the inner diameter of the upper surface of the contact hole is not excessive. Then, the idea was obtained that the organic insulating layer was processed by etching, and at that time, a hard mask, in which the opening was not easily expanded by etching, was used. According to this method, since the organic insulating layer under the hard mask is difficult to be removed by etching, a contact hole having a substantially constant inner diameter can be formed, and high definition can be easily achieved. On the other hand, when the thickness of the organic insulating layer is larger than the thickness of the upper electrode, when the conductive material is difficult to adhere to the inner wall of the contact hole, the thickness of the organic insulating layer is reduced to one of the source region, the drain region, and the gate electrode existing at the bottom of the contact hole. In some cases, electrical connection with the upper electrode becomes difficult. In order to solve this problem, the inventors have further studied a method of manufacturing a TFT substrate and a structure of the TFT substrate such that the inner diameter of the upper surface side of the contact hole is not excessive while ensuring electrical connection in the contact hole. The present disclosure has been achieved.

<< Aspects of the Present Disclosure >>
A thin film transistor substrate according to one embodiment of the present disclosure includes a substrate, a semiconductor layer provided over the substrate, having a channel region and a pair of contact regions sandwiching the channel region, and a gate insulating layer in the channel region. A gate electrode provided, an insulating layer covering the semiconductor layer and the gate electrode and having a contact hole provided therein, and a hard mask provided on the insulating layer and provided with an opening at a position corresponding to the contact hole A layer, and an upper electrode provided on the hard mask layer and electrically connected to any of the contact region and the gate electrode via the contact hole, the contact provided on the insulating layer. The inner diameter of the hole gradually increases from the substrate side to the upper electrode side.

  According to the above configuration, since the contact holes are formed using the hard mask, the contact size can be reduced as compared with the case where the contact holes are formed by the exposure technique. Further, since the inner diameter of the contact hole gradually increases as approaching from the substrate side to the upper electrode side, connection failure is less likely to occur as compared with the case where the inner diameter of the contact hole is uniform.

Further, in the thin film transistor substrate according to an aspect of the present disclosure, the value of the thickness of the upper electrode on the hard mask layer is equal to or greater than a value of a length at which the inner diameter of the contact hole does not change in the thickness direction of the insulating layer. It may be.
According to the above configuration, in the case where the conductive member and the upper electrode in the contact hole are formed at one time, even when the contact hole is not completely filled with the conductive material, the electrical connection between the transistor and the upper electrode is established. It can be done reliably.

Further, in the thin film transistor substrate according to an aspect of the present disclosure, the insulating layer may further include an intermediate mask layer provided with an opening at a position corresponding to the contact hole.
According to the above configuration, when forming a contact hole in the insulating layer, the contact hole can be formed by a single etching step.
Further, in the thin film transistor substrate according to an aspect of the present disclosure, the insulating layer includes a plurality of intermediate mask layers for one contact hole, and an opening of the intermediate mask layer is larger as the intermediate mask layer is closer to the upper electrode. , May be.

According to the above configuration, the length of the contact hole having substantially the same inner diameter can be reduced, and the electrical connection between the transistor and the upper electrode through the contact hole can be reliably performed.
Further, a light-emitting panel according to one embodiment of the present disclosure is provided on the thin film transistor substrate according to one embodiment of the present disclosure, a pixel electrode electrically connected to each of the upper electrodes, and an upper portion of each of the pixel electrodes. It is characterized by comprising a light emitting layer and a common electrode provided on the light emitting layer.

With the above structure, a high-definition light-emitting panel can be realized.
Further, a method for manufacturing a thin film transistor substrate according to one embodiment of the present disclosure includes preparing a substrate, providing a semiconductor layer on the substrate, providing a gate insulating layer and a gate electrode in a first region of the semiconductor layer, Providing an insulating layer covering the layer and the gate electrode, providing a hard mask layer on the insulating layer, opening an opening in the hard mask layer, and at a position in the insulating layer corresponding to the opening of the hard mask layer. A second region and a third region, wherein a contact hole having an inner diameter of a portion in contact with the semiconductor is smaller than an inner diameter of an opening of the hard mask layer, and the first region of the semiconductor layer is sandwiched through the contact hole; An upper electrode connected to each of the gate electrodes is provided on the hard mask layer.

  According to the above method, since the contact hole is formed using the hard mask, the contact size can be reduced as compared with the case where the contact hole is formed by the exposure technique. In addition, since the inner diameter of the contact hole increases from the substrate side to the upper electrode side, connection failure is less likely to occur as compared with the case where the inner diameter of the contact hole is uniform.

Further, in the method for manufacturing a thin film transistor substrate according to an aspect of the present disclosure, the amount of increase in the length of the contact hole in the thickness direction of the insulating layer per etching of the upper region may be greater than the upper part. The thickness of the electrode on the hard mask may be equal to or less than the value of the thickness.
According to the above-described method, since the substantially same length in the contact hole is equal to or less than the thickness of the upper electrode, when the conductive member and the upper electrode in the contact hole are formed at one time, the contact hole becomes conductive. Even when the transistor is not completely filled with the conductive material, electrical connection between the transistor and the upper electrode can be reliably performed.

  Further, in the method for manufacturing a thin film transistor substrate according to one embodiment of the present disclosure, at least an upper region of the insulating layer that is in contact with the hard mask is formed of an organic material, and the opening is formed in the hard mask layer with the organic material. The hard mask layer may be etched using a mask to be formed, and when opening the contact hole, the etching for the upper region and the mask and the etching for the hard mask layer may be alternately repeated a plurality of times. .

According to the above method, since the partial etching is repeated while increasing the diameter of the opening of the hard mask, the inner diameter of the contact hole gradually increases as approaching from the substrate side to the upper electrode side, and the inner diameter of the contact hole is uniform. Connection failure is less likely to occur than in certain cases.
Further, the method for manufacturing a thin film transistor substrate according to one aspect of the present disclosure is a method for forming an organic insulating layer using an organic material, and forming an intermediate mask layer on the organic insulating layer when providing the insulating layer. The process of providing an opening in a layer may be alternately repeated one or more times.

According to the above method, since the inner diameter of the contact hole can be changed at the position where the intermediate mask layer is located, the inner diameter of the contact hole gradually increases as approaching from the substrate side to the upper electrode side. Connection failure is less likely to occur as compared with the case where the inner diameter of the is uniform.
In the method for manufacturing a thin film transistor substrate according to an aspect of the present disclosure, the thickness of the organic insulating layer may be equal to or less than the thickness of the upper electrode on the hard mask.

According to the above configuration, since the substantially same length in the contact hole is equal to or less than the thickness of the upper electrode, when the conductive member and the upper electrode in the contact hole are formed at one time, the contact hole becomes conductive. Even when the transistor is not completely filled with the conductive material, electrical connection between the transistor and the upper electrode can be reliably performed.
The method for manufacturing a thin film transistor substrate according to one embodiment of the present disclosure includes performing a process of forming an organic insulating layer with an organic material and a process of forming the intermediate mask layer and providing an opening in the intermediate mask layer a plurality of times. A larger opening may be opened in the intermediate mask layer farther from the intermediate mask layer.

According to the above method, a plurality of locations where the inner diameter of the contact hole changes can be created per contact hole, and connection failure is less likely to occur.
Embodiment
1. 1. Circuit Configuration 1.1 Circuit Configuration of Display Device 1000 Hereinafter, a circuit configuration of the organic EL display device 1000 (hereinafter, referred to as “display device 1000”) according to the embodiment will be described with reference to FIG.

As shown in FIG. 1, the display device 1000 has a configuration including an organic EL display panel 100 (hereinafter, referred to as “display panel 100”) and a drive control circuit unit 200 connected thereto.
The display panel 100 is an organic EL (Electro Luminescence) panel using an electroluminescence phenomenon of an organic material, and is configured by arranging a plurality of organic EL elements in a matrix, for example. The drive control circuit unit 200 includes four drive circuits 210 to 240 and a control circuit 250.

In the display device 1000, the layout of each circuit of the drive control circuit unit 200 with respect to the display panel 100 is not limited to the configuration shown in FIG.
1.2 Circuit Configuration of Display Panel 100 The plurality of organic EL elements in the display panel 100 are composed of three color sub-pixels (not shown) that emit R (red), G (green), and B (blue) light. You. The circuit configuration of each sub-pixel 10se will be described with reference to FIG.

FIG. 2 is a schematic circuit diagram showing a circuit configuration of the organic EL element 10 corresponding to each sub-pixel 10se of the display panel 100 used in the display device 1000. In the display panel 100, the organic EL elements 10 forming the pixels 10e are arranged on a matrix to form a display area.
As shown in FIG. 2, in the display panel 100 according to the present embodiment, each sub-pixel 10se has two transistors Tr ₁ and Tr ₂ , one capacitor CS, and an organic EL element unit EL as a light emitting unit. It is configured. Transistor Tr ₁ is a driving transistor, the transistor Tr ₂ is a switching transistor.

The gate G ₂ of the switching transistor Tr ₂ is connected to the scanning line Vscn, the source S ₂ is connected to the data line Vdat. The drain D ₂ of the switching transistor Tr ₂ is connected to the gate G ₁ of the driving transistor Tr _1.
The drain D ₁ of the driving transistor Tr ₁ is connected to the power line Va, source S ₁ is connected to the pixel electrode layer of the EL element portion EL (anode). The opposing electrode layer (cathode) in the EL element section EL is connected to the ground line Vcat.

Incidentally, capacitance C, and the gate G ₁ of the drain D ₂ and the drive transistor Tr ₁ of the switching transistor Tr _2, is provided so as to connect the power line Va.
In the display panel 100, one unit pixel 10e is configured by combining a plurality of adjacent sub-pixels 10se (for example, three sub-pixels 10e of emission colors of red (R), green (G), and blue (B)). The sub-pixels 10se are arranged so as to be distributed to form a pixel area. Then, the gate lines GL from the gate G ₂ of each sub-pixel 10se is drawn out respectively, is connected to the scanning line Vscn connected from the outside of the display panel 100. Similarly, connected to the data line Vdat to the source line SL from the source S ₂ of the sub-pixels 10se is connected from each drawn outside of the display panel 100.

The power line Va of each sub-pixel sa and the ground line Vcat of each sub-pixel 10se are collected and connected to the power line Va and the ground line Vcat.
2 Configuration of Organic EL Display Panel 2.1 Overall Configuration of Organic EL Display Panel 100 A display panel 100 according to the present embodiment will be described with reference to the drawings. Note that the drawings are schematic diagrams, and the scales may be different from actual ones.

FIG. 3 is a partial cross-sectional view showing a part of the display panel according to the embodiment. The organic EL display panel 100 includes a plurality of pixels including organic EL elements 10 (R), 10 (G), and 10 (B) that emit three colors (red, green, and blue). FIG. 1 shows a cross section of the one pixel.
In the organic EL display panel 100, each organic EL element 10 is of a so-called top emission type that emits light forward (upward on the plane of FIG. 1).

The organic EL element 10 (R), the organic EL element 10 (G), and the organic EL element 10 (B) have almost the same configuration.
As shown in FIG. 1, the organic EL element 10 includes a TFT substrate 11, an interlayer insulating layer 12, a pixel electrode 13, a partition layer 14, a hole injection layer 15, a hole transport layer 16, a light emitting layer 17, and an electron transport layer 18. , An electron injection layer 19, a counter electrode 20, and a sealing layer 21.

Note that the TFT substrate 11, the interlayer insulating layer 12, the electron transport layer 18, the electron injection layer 19, the counter electrode 20, and the sealing layer 21 are not formed for each pixel, but are used for the organic EL display panel 100. The plurality of organic EL elements 10 are formed in common.
<TFT substrate>
The TFT substrate 11 includes a base material 111 that is an insulating material, and a TFT (Thin Film Transistor) layer 112. Details will be described later.

<Interlayer insulating layer>
The interlayer insulating layer 12 is formed on the TFT substrate 11. The interlayer insulating layer 12 is made of a resin material and is for flattening a step on the upper surface of the TFT layer 112. Examples of the resin material include a positive photosensitive material. In addition, examples of such a photosensitive material include an acrylic resin, a polyimide resin, a siloxane resin, and a phenol resin. Although not shown in the cross-sectional view of FIG. 3, a contact hole is formed in the interlayer insulating layer 12 for each pixel.

<Pixel electrode>
The pixel electrode 13 includes a metal layer made of a light-reflective metal material, and is formed on the interlayer insulating layer 12. The pixel electrode 13 is provided for each pixel, and is electrically connected to the TFT layer 112 through a contact hole.
In the present embodiment, the pixel electrode 13 functions as an anode.

  Specific examples of the metal material having light reflectivity include Ag (silver), Al (aluminum), an aluminum alloy, Mo (molybdenum), APC (alloy of silver, palladium, and copper) and ARA (silver, rubidium, and gold). Alloy), MoCr (an alloy of molybdenum and chromium), MoW (an alloy of molybdenum and tungsten), NiCr (an alloy of nickel and chromium), and the like.

The pixel electrode 13 may be composed of a metal layer alone, but has a laminated structure in which a layer made of a metal oxide such as ITO (indium tin oxide) or IZO (indium zinc oxide) is laminated on the metal layer. Is also good.
<Partition layer>
The partition layer 14 is formed on the hole injection layer 15 in such a manner that a part of the upper surface of the pixel electrode 13 and the hole injection layer 15 is exposed and the surrounding area is covered. A region on the upper surface of the hole injection layer 15 that is not covered with the partition layer 14 (hereinafter, referred to as an “opening”) corresponds to a subpixel. That is, the partition layer 14 has the opening 14a provided for each sub-pixel.

In the present embodiment, the partition layer 14 is formed on the interlayer insulating layer 12 in a portion where the pixel electrode 13 is not formed. That is, in a portion where the pixel electrode 13 is not formed, the bottom surface of the partition layer 14 is in contact with the upper surface of the interlayer insulating layer 12.
The partition layer 14 is made of, for example, an insulating organic material (for example, an acrylic resin, a polyimide resin, a novolak resin, a phenol resin, or the like). The partition layer 14 functions as a structure for preventing the applied ink from overflowing when the light-emitting layer 17 is formed by a coating method, and an evaporation mask when the light-emitting layer 17 is formed by an evaporation method. Function as a structure for placing the In the present embodiment, the partition layer 14 is made of a resin material, and examples of the material of the partition layer 14 include an acrylic resin, a polyimide resin, a siloxane resin, and a phenol resin. In the present embodiment, a phenolic resin is used.

<Hole injection layer>
The hole injection layer 15 is provided on the pixel electrode 13 for the purpose of promoting injection of holes from the pixel electrode 13 into the light emitting layer 17. The hole injection layer 15 is made of, for example, an oxide such as Ag (silver), Mo (molybdenum), Cr (chromium), V (vanadium), W (tungsten), Ni (nickel), Ir (iridium), or the like. This is a layer made of a conductive polymer material such as PEDOT (a mixture of polythiophene and polystyrene sulfonic acid). Among the above, the hole injection layer 15 made of a metal oxide has a function of injecting holes into the light emitting layer 17 stably or assisting generation of holes, and Has a function. In the present embodiment, hole injection layer 15 is made of tungsten oxide. When the hole injection layer 15 is formed of a transition metal oxide, a plurality of oxidation levels are obtained, so that a plurality of levels can be obtained. As a result, hole injection becomes easy, which contributes to a reduction in driving voltage. I do.

<Hole transport layer>
The hole transport layer 16 is formed in the opening 14a using a polymer compound having no hydrophilic group. For example, a high molecular compound such as polyfluorene or a derivative thereof or polyarylamine or a derivative thereof and having no hydrophilic group can be used.
The hole transport layer 16 has a function of transporting holes injected from the hole injection layer 15 to the light emitting layer 17.

<Light-emitting layer>
The light emitting layer 17 is formed in the opening 14a. The light emitting layer 17 has a function of emitting light of each color of R, G, and B by recombination of holes and electrons. Known materials can be used as the material of the light emitting layer 17. Specifically, for example, oxinoid compounds, perylene compounds, coumarin compounds, azacoumarin compounds, oxazole compounds, oxadiazole compounds, perinone compounds, pyrrolopyrrole compounds, naphthalene compounds, anthracene compounds, fluorene compounds, fluoranthene compounds, tetracene compounds, pyrene Compound, coronene compound, quinolone compound and azaquinolone compound, pyrazoline derivative and pyrazolone derivative, rhodamine compound, chrysene compound, phenanthrene compound, cyclopentadiene compound, stilbene compound, diphenylquinone compound, styryl compound, butadiene compound, dicyanomethylenepyran compound, dicyanomethylene Thiopyran compounds, fluorescein compounds, pyrylium compounds, thiapyrylium compounds, selena Lilium compounds, telluropyrylium compounds, aromatic aldadienes, oligophenylene compounds, thioxanthene compounds, cyanine compounds, acridine compounds, metal complexes of 8-hydroxyquinoline compounds, metal complexes of 2-bipyridine compounds, Schiff salts and Group III metals It is preferably formed of a fluorescent substance such as a complex, an oxine metal complex, and a rare earth complex.

<Electron transport layer>
The electron transport layer 18 has a function of transporting electrons from the counter electrode 20 to the light emitting layer 17. The electron transport layer 18 is made of an organic material having a high electron transport property and does not include an alkali metal and an alkaline earth metal.
Examples of the organic material used for the electron transport layer 18 include π-electron low molecular weight organic materials such as oxadiazole derivatives (OXD), triazole derivatives (TAZ), and phenanthroline derivatives (BCP, Bphen).

<Electron injection layer>
The electron injection layer 19 has a function of injecting electrons supplied from the counter electrode 20 to the light emitting layer 17 side. The electron injection layer 19 is formed, for example, by doping an organic material having a high electron transporting property with a doping metal selected from an alkali metal, an alkaline earth metal, and yttrium. In the embodiment, Ba is doped. The doping concentration of Ba is 40 wt% or less, preferably 20 wt% or less, and more preferably 15 wt% or less.

Examples of the organic material used for the electron injection layer 19 include π-electron low molecular weight organic materials such as an oxadiazole derivative (OXD), a triazole derivative (TAZ), and a phenanthroline derivative (BCP, Bphen).
Further, as the electron injection layer 19, an alkali metal fluoride such as sodium fluoride (NaF) may be used, or a stacked structure of an alkali metal fluoride and an organic layer may be used.

<Counter electrode>
The counter electrode 20 is made of a light-transmitting conductive material and is formed on the electron injection layer 19. The counter electrode 20 functions as a cathode.
As a material of the counter electrode 20, for example, ITO or IZO can be used. Alternatively, a metal such as silver, a silver alloy, aluminum, or an aluminum alloy may be used as a material of the counter electrode 20. In this case, since the counter electrode 20 needs to have a light transmitting property, the counter electrode 20 is formed as a thin film having a thickness of about 20 nm or less.

<Sealing layer>
The sealing layer 21 has a function of suppressing exposure of organic layers such as the hole transport layer 16, the light emitting layer 17, the electron transport layer 18, and the electron injection layer 19 to moisture or air. For example, it is formed using a light-transmitting material such as silicon nitride (SiN) or silicon oxynitride (SiON). Further, a sealing resin layer formed of a resin material such as an acrylic resin or a silicone resin may be provided over a layer formed using a material such as silicon nitride (SiN) or silicon oxynitride (SiON).

In the present embodiment, since the organic EL display panel 100 is of a top emission type, the sealing layer 21 needs to be formed of a light transmissive material.
<Others>
Although not shown in FIG. 1, a color filter or an upper substrate may be attached to the sealing layer 21 via a sealing resin. By bonding the upper substrate, the hole transport layer 16, the light emitting layer 17, the electron transport layer 18, and the electron injection layer 19 can be protected from moisture, air, and the like.

2.2 TFT Substrate Hereinafter, the TFT substrate 11 according to the present embodiment will be described in more detail with reference to the drawings. FIG. 4 is a partial cross-sectional view showing a part of the display panel according to the embodiment, and shows a cross section of one organic EL element 10.
As shown in FIG. 4, the TFT substrate 11 includes a base material 111, a CS lower electrode 101, lower insulating layers 102 and 103, a semiconductor layer 104, a gate insulating layer 106, a gate electrode 107, inorganic insulating layers 105, 108, 109, An organic insulating layer 1010, a hard mask 1101, and an upper electrode 1102 are provided.

Note that the base material 111, the lower insulating layers 102 and 103, the inorganic insulating layers 105, 108 and 109, and the organic insulating layer 1010 are not formed for each TFT but are common to a plurality of TFT elements included in the TFT substrate 11. It is formed.
<Substrate>
The base material 111 is formed of an insulating material. Specific materials include, for example, glass substrates, quartz substrates, silicon substrates, molybdenum sulfide, copper, zinc, aluminum, stainless steel, magnesium, iron, nickel, gold, silver and other metal substrates, gallium arsenide and other semiconductor substrates, A plastic substrate or the like can be employed. As the plastic material, either a thermoplastic resin or a thermosetting resin may be used. For example, polyethylene, polypropylene, polyamide, polyimide (PI), polycarbonate, acrylic resin, polyethylene terephthalate (PET), polybutylene terephthalate, polyacetal, other fluororesins, styrene, polyolefin, polyvinyl chloride, polyurethane, Fluororubber-based, various thermoplastic elastomers such as chlorinated polyethylene, epoxy resin, unsaturated polyester, silicone resin, polyurethane and the like, or copolymers, blends, polymer alloys and the like mainly containing these, Among them, a laminate in which one kind or two or more kinds are laminated can be used.

<CS lower electrode>
The CS lower electrode 101 is one electrode constituting the above-described capacitor CS, and is made of a conductive material. Specific materials include, for example, metals such as titanium, aluminum, molybdenum, copper, tungsten, manganese, chromium, tantalum, niobium, silver, gold, platinum, palladium, indium, nickel, neodymium, and alloys thereof ( For example, MoW) can be used.

<Lower insulating layer>
The lower insulating layers 102 and 103 are inorganic insulating layers provided on the base material 111 and function as an undercoat layer for the TFT and also function as a dielectric constituting the capacitor CS. In the embodiment, the lower insulating layer includes a first lower insulating layer 102 made of SiN and a second lower insulating layer 103 made of SiO. The thickness of the lower insulating layer is, for example, 100 nm or more and 1000 nm or less.

<Semiconductor layer>
The semiconductor layer 104 functions as the channel layer of the transistors Tr ₁ and Tr ₂ and the other electrode of the capacitor CS. In the embodiment, the semiconductor layer 104 is mainly composed of a transparent amorphous oxide semiconductor (TAOS). The material of TAOS is an oxide of indium, gallium, zinc, or the like, and more specifically, for example, InGaZnO, InTiZnO, ZnO, InGaO, InZnO.

4, the oxide semiconductor layer 104d is a component of the transistor Tr _1, comprising a channel region 104b, and a pair of drain regions 104a and source regions 104c which follow. Further, the source region 104c is electrically connected to the CS lower electrode 101 through the connection electrode 104e. The CS upper electrode 104f forms a capacitor CS together with the CS lower electrode 101. Note that each of the drain region 104a, the source region 104c, the connection electrode 104e, and the CS upper electrode 104f has high conductivity (low resistivity) due to the formation of oxygen defects. Although the oxide semiconductor layer of the transistor Tr ₂ are not shown in FIG. 4 has the same structure as the oxide semiconductor layer 104d.

<Gate insulating layer>
The gate insulating layer 106 is an insulator existing between the channel region 104b and the gate electrode 107. In the embodiment, it is formed of SiO.
<Gate electrode>
Gate electrode 107 is made of a conductive material. As a specific material, for example, a metal such as titanium, aluminum, molybdenum, copper, tungsten, and chromium, or an alloy thereof (for example, MoW) can be used.

<Inorganic insulating layer>
The inorganic insulating layers 105, 108, and 109 are insulating films having a function of a protective film for preventing entry of hydrogen into the semiconductor layer. The inorganic insulating layer has, for example, a laminated structure of a first inorganic insulating layer 105 formed of AlO, a second inorganic insulating layer 108 formed of SiO, and a third inorganic insulating layer formed of AlO. Note that the second inorganic insulating layer 108 is not limited to SiO, and may be formed of SiON, SiN, AlO, or the like. Further, it is preferable that the dielectric constant of the second inorganic insulating layer 108 be low in order to reduce the parasitic capacitance.

<Organic insulating layer>
The organic insulating layer 1010 is an insulating film formed on the inorganic insulating layer, and has a function of flattening the upper surface of the TFT substrate 11. The material of the organic insulating layer is, for example, polyimide.
<Hard mask>
The hard mask 1101 is a mask provided for forming a contact hole penetrating from each of the drain region 104a, the source region 104c, and the gate electrode 107 to above the organic insulating layer 1010. The hard mask 1101 is provided on at least the periphery of the contact hole on the organic insulating layer 1010, and an opening corresponding to the contact hole is provided. The hard mask layer includes, for example, any one of copper, cobalt, tungsten, aluminum oxide, aluminum nitride, aluminum oxynitride, tungsten oxide, titanium, titanium nitride, zirconium oxide, hafnium oxide, and tantalum oxide. When the hard mask layer has conductivity, the hard mask layer needs to be provided independently for each contact hole.

<Upper electrode>
The upper electrode 1102 g is formed in a contact hole penetrating the organic insulating layer 1010 and the inorganic insulating layers 105, 108, and 109, on the organic insulating layer 1010 and on the hard mask 1101, and is electrically connected to the gate electrode 107. The upper electrode 1102sd is formed in a contact hole penetrating the organic insulating layer 1010 and the inorganic insulating layers 105, 108, and 109, on the organic insulating layer 1010, and on the hard mask 1101, and is formed on any of the drain region 104a and the source region 104c. Is electrically connected to the other. The upper electrodes 1102g and 1102sd are formed of a conductive material, and are formed, for example, of aluminum, molybdenum, tungsten, molybdenum tungsten, copper, titanium, and chromium.

  Here, the shape of the contact hole has a structure in which the inner diameter gradually increases from at least the portion penetrating the organic insulating layer 1010 toward the hard mask 1101 from the base material 111 side. Further, the length with the same inner diameter is equal to or less than the thickness of the upper electrodes 1102 g and 1102 sd on the hard mask 1101. Accordingly, even when the conductive material is hard to adhere to the inner wall of the contact hole when the upper electrodes 1102g and 1102sd are formed, the hard mask 1101 is formed starting from the step portion where the inner diameter of the contact hole changes. A conductive material is formed on the hard mask 1101 side by the same distance as the film thickness of the upper electrodes 1102g and 1102sd. Therefore, even when the entire inside of the contact hole cannot be filled with the conductive material, a stacked body of a conductive material that connects two adjacent steps is formed on each step provided on the inner wall of the contact hole. It is hard to cause disconnection inside the hole. Therefore, electrical connection between the upper electrode 1102g and the gate electrode 107, and electrical connection between the upper electrode 1102sd and the drain region 104a or the source region 104c can be reliably performed.

3. Method for Manufacturing TFT Substrate 11 A method for manufacturing the TFT substrate 11 will be described with reference to the drawings. FIG. 5 to FIG. 13 are schematic cross-sectional views showing states in respective steps in manufacturing the TFT substrate 11. FIG. 14 is a flowchart showing a method for manufacturing the TFT substrate 11.
(1) Formation of CS Lower Electrode 101 First, a base material 111 is prepared (FIG. 5A). Next, the CS lower electrode material layer 101L is formed on the base material 111 by using a sputtering method or a vacuum evaporation method (FIG. 5B, step S10). Next, the CS lower electrode 101 is formed by patterning using a photolithography method and an etching method (FIG. 5C, step S20).

(2) Formation of Lower Insulating Layers 102 and 103 Next, a lower insulating layer is formed on the CS lower electrode 101 and the base material 111 (FIG. 5D, step S30). The lower insulating layer is formed, for example, by forming a first lower insulating layer 102 made of SiN by CVD using silane and ammonia as source gases, and then forming a second lower insulating layer 102 made of SiO by CVD using silane as a source gas in an oxidizing atmosphere. This is performed by forming the insulating layer 103.

(3) Formation of Semiconductor Layer 104 Next, a semiconductor material layer 104L is formed on the lower insulating layer 103 (FIG. 5E, step S40). The semiconductor material layer 104L can be formed by, for example, a sputtering method. Next, the semiconductor layers 104d, 104e, and 104f are formed by patterning the semiconductor material layer 104L using a photolithography method and an etching method (FIG. 5F, step S50).

(4) Formation of Gate Insulating Layer 106 and Gate Electrode 107 Next, a gate insulating material layer 106L is formed on the semiconductor layers 104d, 104e, 104f and the lower insulating layer 103 (FIG. 6A, step S60). The gate insulating material layer 106L can be formed by, for example, a CVD method. Next, a gate electrode material layer 107L is formed on the gate insulating material layer 106L (FIG. 6B, step S70). Then, the gate insulating layer 106 and the gate electrode 107 are formed by patterning using a photolithography method and an etching method (FIG. 6C, step S80).

Note that annealing may be performed after the gate insulating layer 106 and the gate electrode 107 are formed. Thus, the resistance of each of the drain region 104a, the source region 104c, the connection electrode 104e, and the CS upper electrode 104f that are not covered with the gate insulating layer 106 is reduced.
(5) Formation of inorganic insulating layers 105, 108 and 109 Next, an inorganic insulating layer is formed. First, a first inorganic insulating layer 105 is formed by a sputtering method so as to cover the whole of the semiconductor layer 104, the gate insulating layer 106, and the gate electrode 107 (FIG. 6D), and a second inorganic insulating layer 105 is formed on the first inorganic insulating layer 105. The inorganic insulating layer 108 is formed by the CVD method (FIG. 7A), and the third inorganic insulating layer 109 is formed on the second inorganic insulating layer 108 by the sputtering method (FIG. 7B, step S90).

(6) Formation of Organic Insulating Layer 1010 and Hard Mask 1101, Opening of Contact Hole Next, the organic insulating layer 1010 and the hard mask 1101 are formed, and a contact hole penetrating the inorganic insulating layer and the organic insulating layer is opened (step). S100). FIG. 15 is a flowchart showing a step of forming a hard mask 1010 and opening a contact hole.
(I) Formation of Organic Insulating Layer 1010 First, an organic material is applied so as to cover the third inorganic insulating layer 109, and the surface is flattened to form the organic insulating layer 1010 (FIG. 7C, Step S210). The organic insulating layer 1010 is formed by a coating method such as a spin coating method.

(Ii) Formation of Hard Mask Material Layer 1101L Next, a hard mask material layer 1101L is formed on the organic insulating layer 1010 (FIG. 8A, step S220). The hard mask material layer 1101L is formed by, for example, a sputtering method or a vacuum evaporation method.
(Iii) Formation of Photomask 1103 Next, after forming a photoresist film on the hard mask material layer 1101L, drying is performed, a photomask provided with an opening corresponding to a contact hole is overlaid, exposed, and developed. Is performed, a photomask 1103 having an opening at a position where a contact hole is to be opened is formed (FIG. 8B, step S230). The photoresist film is formed, for example, by forming a solution containing a polyimide resin which is a positive photoresist by a coating method such as a spin coating method.

(Iv) Patterning of Hard Mask 1101 Next, the hard mask 1101L is etched to remove a portion exposed in the opening of the photomask 1103a, thereby forming the hard mask 1101a (FIG. 8C, Step S310). At this time, the opening provided in the hard mask 1101a and the opening of the photomask 1103 have substantially the same shape.

(V) Partial etching of the organic insulating layer 1010 Next, the organic insulating layer 1010 is etched to remove the portion exposed in the opening of the hard mask 1101a, thereby opening the opening 1102a (FIG. 9A ), Step S320). At this time, the etching conditions are set so that the depth d ₁ of the opening 1102a does not exceed the thickness of the upper electrode 1102, and the etching is performed even when the third inorganic insulating layer 109 is not exposed at the bottom of the opening 1102a. Interrupt.

  Note that, as described above, since the photomask 1103a is formed of the same organic material as the organic insulating layer 1010, the radius of the opening of the photomask 1103b after performing step S320 is increased by a small amount δ. On the other hand, since the hard mask 1101 is formed of an inorganic material, the opening diameter does not substantially change before and after step S320, and the opening of the photomask 1103b is wider than the opening provided in the hard mask 1101a.

(Vi) Patterning of Hard Mask 1101 Next, the hard mask 1101a is etched to remove a portion exposed in the opening of the photomask 1103b, thereby forming the hard mask 1101b (FIG. 9B, Step S310). Thus, the opening provided in the hard mask 1101b and the opening of the photomask 1103b have substantially the same shape.

(Vi) Partial etching of the organic insulating layer 1010 Next, the organic insulating layer 1010 is etched to remove the portion exposed in the opening of the hard mask 1101b, thereby opening the opening 1102b (FIG. 9C ), Step S320). At this time, the etching conditions are set so that the increase amount d ₂ of the depth of the opening 1102a does not exceed the film thickness of the upper electrode 1102, and the third inorganic insulating layer 109 is not exposed at the bottom of the opening 1102a. Even if the etching is interrupted. Note that d ₁ may be equal to d ₂ .

In this partial etching, an existing opening does not exist in a region of the organic insulating layer 1010 whose distance from the upper surface is larger than d ₁ , and the inner wall of the opening 1102a functions as a mask at the beginning of the partial etching. The opening having the same diameter as the opening 1102a is formed. On the other hand, in the region of the organic insulating layer 1010 whose distance from the upper surface is d ₁ or less, the existing opening 1102a exists and the diameter of the opening of the hard mask 1101b is larger than the opening 1102a. An opening having the same diameter as the opening of the mask 1101b is formed. As a result, the opening 1102b, the distance from the upper surface of the organic insulating layer distance from the upper surface of 1010 d ₁ organic than the opening of the larger area the insulating layer 1010 becomes large openings d ₁ smaller regions. Therefore, the opening 1102b, the distance from the upper surface of the organic insulating layer 1010 inside diameter is changed as a boundary position is d _1, a shape whose inner diameter increases with decreasing distance from the substrate 111 to the upper electrode 1102.

  Note that, as described above, since the photomask 1103b is formed of the same organic material as the organic insulating layer 1010, the radius of the opening of the photomask 1103c after performing step S320 is increased by a small amount δ. On the other hand, since the hard mask 1101 is formed of an inorganic material, the opening diameter does not substantially change before and after step S320, and the opening of the photomask 1103c is wider than the opening provided in the hard mask 1101b.

Hereinafter, the patterning of the hard mask 1101 and the partial etching of the organic insulating layer 1010 are repeated until the third inorganic insulating layer 109 is exposed at the bottom of all the openings 1102. In the embodiment, the depth of the opening 1102c is equal to or less than the thickness of the upper electrode 1102 by the third patterning of the hard mask 1101 (FIG. 10A) and the partial etching of the organic insulating layer 1010 (FIG. 10B). It increased by increasing the amount d ₃ is, for a contact hole corresponding to the gate electrode 107, a third inorganic insulating layer 109 is exposed at the bottom of the opening 1102c. Further, by the fourth patterning of the hard mask 1101 (FIG. 11A) and the partial etching of the organic insulating layer 1010 (FIG. 11B), the depth of the opening 1102d in the drain region 104a and the source region 104c is reduced. It increases by an increase d ₄ which is equal to or less than the thickness of the upper electrode 1102. Further, by the fifth patterning of the hard mask 1101 (FIG. 12A) and the partial etching of the organic insulating layer 1010 (FIG. 12B), the depth of the opening 1102e in the drain region 104a and the source region 104c is reduced. increased by increasing the amount d ₅ or less thickness of the upper electrode 1102, the third inorganic insulating layer 109 is exposed at the bottom of the opening 1102e.

(Vii) Removal of Photomask and Etching of Inorganic Insulating Layer After the third inorganic insulating layer 109 is exposed at the bottom of the opening for all contact holes by repeating Steps S310 and S320, etching of the inorganic insulating layer and the photomask 1103 are performed. (Steps S250 and S260 in FIG. 13A). As a result, a contact hole penetrating from the gate electrode 107, the drain region 104a, the connection electrode 104e, and the CS lower electrode 101 to above the hard mask 1101 is formed. Further, the contact hole has a shape in which the inner diameter changes at the boundary of the partial etching, and increases as the distance from the substrate 111 to the upper electrode 1102 increases.

(7) Formation of upper electrode 1102 Returning to FIG. 17, the description will be continued. After the contact holes are formed, an upper electrode is formed. First, an upper electrode material layer 1102L is formed in the contact hole, on the organic insulating layer 1010, and on the hard mask 1101 by using a sputtering method, a vacuum evaporation method, or the like (FIG. 13B). Then, the upper electrode material layer 1102L is patterned using a photolithography method and an etching method to form upper electrodes 1102g and 1102sd.

In the case where the hard mask 1101 exists across a plurality of contact holes as shown in FIG. 13B, the unnecessary hard mask 1101 that is not covered with the upper electrode 1102 is removed by etching. Short circuit due to the mask 1101 can be prevented.
Through the above steps, the TFT substrate 11 is completed.

4. Conclusion As described above, in the TFT substrate according to the embodiment, the organic insulating layer 1010 is etched with the hard mask 1101 being used. Therefore, in each partial etching step of the organic insulating layer 1010, the opening of the hard mask 1101 does not greatly widen, and the inner diameter of the contact hole does not largely differ between the third inorganic insulating layer 109 side and the hard mask 1101 side. Therefore, it is possible to prevent the inner diameter of the contact hole, particularly the inner diameter on the hard mask 1101 side, from being excessively large, and it is easy to increase the definition of the display panel. Further, in the TFT substrate according to the embodiment, the inner diameter of the contact hole gradually increases at intervals smaller than the thickness of the upper electrode 1102 as approaching the hard mask 1101. Therefore, when the upper electrode is formed by a sputtering method or a vacuum evaporation method, a conductor having substantially the same value as the thickness of the upper electrode is formed from the bottom of the contact hole or a position having a different inner diameter toward the hard mask 1101 side. Is done. Since the distance between the positions where the conductors are formed is equal to or less than the length of the conductor, even if the entire inside of the contact hole is not filled with the conductor, the electrical connection from the bottom of the contact hole to the upper electrode is not established. Almost certainly done. Therefore, the inner diameter of the contact hole can be reduced while ensuring the electrical connection.

≪Modified example≫
In the embodiment, the case where the etching of the hard mask 1101 and the etching of the organic insulating layer 1010 are repeated with the photomask 1103 over the hard mask 1101 left is described. However, the method of manufacturing the TFT substrate 11 is not limited to the above method, and may be the following method.

16 to 18 are schematic cross-sectional views showing states in respective steps in forming an organic insulating layer 1010 and a hard mask 1101 and opening a contact hole according to a modification. FIG. 19 is a flowchart showing a method of forming the organic insulating layer 1010 and the hard mask 1101, and forming a contact hole.
(I) Formation of First Organic Insulating Layer 1010a First, an organic material is applied so as to cover the third inorganic insulating layer 109, and the surface is flattened to form the first organic insulating layer 1010a (FIG. 16). (A), Step S410). The first organic insulating layer 1010a is formed by using a coating method such as a spin coating method. At this time, the thickness of the first organic insulating layer 1010a is set to be equal to or less than the thickness of the upper electrode 1102.

(Ii) Formation of Intermediate Mask 1014 Next, an intermediate mask material layer 1014L is formed on the first organic insulating layer 1010a (FIG. 16B, step S430). The film formation of the intermediate mask material layer 1014L may be, for example, the same process using the same material as the film formation of the hard mask material layer 1101L, and is performed by a sputtering method, a vacuum evaporation method, or the like.

Next, the intermediate mask material layer 1014L is patterned using a photolithography method and an etching method, and an intermediate mask 1014a having an opening having the same size as the inner diameter of the contact hole is formed at a position where the contact hole is to be opened (FIG. 16 (c), step S430).
(Iii) Formation of Second Organic Insulating Layer 1010b Next, an organic material is applied so as to cover the intermediate mask 1014a and the first organic insulating layer 1010a, and the surface is flattened to laminate the second organic insulating layer 1010b. It is formed (FIG. 16C, step S410). At this time, the thickness of the second organic insulating layer 1010b is set to be equal to or less than the thickness of the upper electrode 1102.

(Iv) Formation of Intermediate Mask 1014 Next, an intermediate mask material layer 1014L is formed on the second organic insulating layer 1010b (FIG. 16D, step S430).
Next, the intermediate mask material layer 1014L is patterned using a photolithography method and an etching method, and an intermediate mask 1014b having an opening having the same size as the inner diameter of the contact hole is formed at a position where the contact hole is to be opened (FIG. 17 (a), step S430). At this time, the inner diameter of the opening formed in the intermediate mask 1014b is set to be larger than the inner diameter of the opening formed in the intermediate mask 1014a.

(V) Formation of Third Organic Insulating Layer 1010c Next, an organic material is applied so as to cover the intermediate mask 1014b and the second organic insulating layer 1010b, and the surface is flattened to laminate the third organic insulating layer 1010c. It is formed (FIG. 17C, step S410). At this time, the thickness of the third organic insulating layer 1010c is set to be equal to or less than the thickness of the upper electrode 1102.

(Vi) Formation of Hard Mask 1101 Next, a hard mask material layer 1101L is formed on the third organic insulating layer 1010c (FIG. 18A, step S450).
Next, the hard mask material layer 1101L is patterned using a photolithography method and an etching method, and a hard mask 1101 having an opening having the same size as the inner diameter of the contact hole is formed at a position where the contact hole is to be opened (FIG. 18 (b), step S460). At this time, the inner diameter of the opening formed in hard mask 1101 is set to be larger than the inner diameter of the opening formed in intermediate mask 1014b.

(Vii) Etching of Organic Insulating Layer 1010 Next, the organic insulating layer 1010 is etched to remove the portion exposed in the opening of the hard mask 1101, thereby opening the opening 1102h (FIG. 18C). , Step S420). At this time, an opening having the same inner diameter as the opening of the hard mask 1101 is provided between the hard mask 1101 and the intermediate mask 1014b. On the other hand, between the intermediate mask 1014b and the intermediate mask 1014a, the opening has the same inner diameter as the opening of the intermediate mask 1014b. Similarly, the opening between the intermediate mask 1014a and the third inorganic insulating layer 109 has the same inner diameter as the opening of the intermediate mask 1014a. As described above, since the sizes of the openings of the hard mask 1101, the intermediate mask 1014b, and the intermediate mask 1014a decrease in this order, the inner diameter of the opening 1102h becomes smaller from the base 111 toward the upper electrode 1102 with the intermediate mask as a boundary. The shape will increase.

  In the modification, the intermediate masks 1014a and 1014b are made of an insulator. However, when the intermediate masks 1014a and 1014b are made of an electric conductor, the patterning of the intermediate masks 1014a and 1014b requires a space between adjacent contact holes. Intermediate masks 1014a and 1014b are formed so as not to be connected. At this time, the intermediate masks 1014a and 1014b may have, for example, a ring shape having an outer diameter twice the opening diameter.

  According to the above steps, a contact hole having a shape whose inner diameter increases stepwise as it approaches the upper electrode 1102 from the base material 111 can be formed. In addition, since the thickness of each of the first organic insulating layer 1010a to the third organic insulating layer 1010c is equal to or less than the thickness of the upper electrode 1102, when the upper electrode is formed by a sputtering method or a vacuum evaporation method, the bottom surface of the contact hole is formed. To the intermediate mask 1014a, the intermediate mask 1014a to the intermediate mask 1014b, and the intermediate mask 1014b to the hard mask 1101 are electrically connected. Therefore, even when all of the inside of the contact hole is not filled with the conductor, the electrical connection from the bottom of the contact hole to the upper electrode is made almost reliably.

≪Other variations≫
In the embodiment, the TFT substrate 11 and the display panel 100 according to the present embodiment have been described. However, the present invention is not limited to the above embodiment except for essential characteristic components. Absent. For example, a form obtained by applying various modifications conceived by those skilled in the art to each embodiment, or a combination obtained by arbitrarily combining components and functions in each embodiment without departing from the spirit of the present invention. Embodiments are also included in the present invention. Hereinafter, modified examples of the TFT substrate 11 and the display panel 100 will be described as an example of such an embodiment.

  (1) In the method of manufacturing the TFT substrate 11 according to the embodiment, the etching of the hard mask 1101 and the etching of the organic insulating layer 1010 are repeated five times at a time. The number of repetitions may be arbitrary depending on the film thickness of 1010 and the film thickness of the upper electrode 1102. Similarly, in the manufacturing method of the TFT substrate according to the modified example, the number of partial organic insulating layers is three and the number of intermediate masks is two. However, depending on the film thickness of the organic insulating layer 1010 and the film thickness of the upper electrode 1102, It can be any number.

  (2) In the TFT substrate 11 according to the embodiment and the modified example, the gate insulating layer 106 and the gate electrode 107 are so-called top-gate TFTs in which the gate insulating layer 106 and the gate electrode 107 are located closer to the light emitting element than the channel region 104b. However, each TFT of the TFT substrate 11 may be a so-called bottom gate type TFT which is stacked from the base 111 side with a gate electrode, a gate insulating layer, and a channel region.

Further, in the TFT substrate according to the embodiments and modifications, but the CS lower electrode of the source region and the capacitor CS of the transistor Tr ₁ is in the form to be connected, the circuit configuration is not limited to this case, any configuration It may be.
(3) In the TFT substrate 11 according to the embodiment and the modification, the lower insulating layer has a laminated structure of the first lower insulating layer 102 made of SiN and the second lower insulating layer 103 made of SiO. However, the lower insulating layer may have a single-layer structure or a stacked structure of three or more layers. Similarly, the inorganic insulating layer has a laminated structure of a first inorganic insulating layer 105 formed of AlO, a second inorganic insulating layer 108 formed of SiO, and a third inorganic insulating layer 109 formed of AlO. However, a single-phase structure of AlO or a laminated structure of four or more layers may be used.

  (4) In the TFT substrate 11 according to the embodiment and the modification, the contact hole has a configuration in which the inner diameter gradually increases as approaching from the substrate side to the upper electrode side. As described above, a tapered contact hole having a small inner diameter difference between the base material side and the upper electrode side may be used. Such a contact hole can be formed, for example, by performing etching under such etching conditions that the removal rate of the hard mask layer is lower than the removal rate of the organic insulating layer.

(5) Although the display panel 100 according to the embodiment includes the organic EL element 10, the display panel 100 may include an arbitrary self-luminous element instead of the organic EL element, or a non-light emitting type such as a liquid crystal display element. A display element may be provided.
≪Supplement≫
Each of the embodiments described above shows a preferred specific example of the present invention. Numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of constituent elements, steps, order of steps, and the like described in the embodiments are merely examples, and do not limit the present invention. In addition, among the constituent elements in the embodiment, steps not described in the independent claims that indicate the highest concept of the present invention are described as arbitrary constituent elements that constitute a more preferable embodiment.

The order in which the above-described steps are performed is merely an example for specifically describing the present invention, and may be any other order. Further, some of the above steps may be performed simultaneously (in parallel) with other steps.
In addition, for easy understanding of the invention, the scales of the components in each of the drawings described in the above embodiments may be different from actual ones. Further, the present invention is not limited by the description of the above embodiments, and can be appropriately changed without departing from the gist of the present invention.

Further, at least a part of the functions of the embodiments and the modifications thereof may be combined.
Further, various modifications in which the present embodiment is modified within a range conceivable by those skilled in the art are also included in the present invention.

  The TFT substrate and the display device including the TFT substrate according to the present invention can be widely used for devices such as a television set, a personal computer, a mobile phone, and other various electronic devices having a display panel.

Reference Signs List 1000 organic EL display device 100 organic EL display panel 10 organic EL element 11 TFT substrate 12 interlayer insulating layer 13 pixel electrode 14 partition layer 15 hole injection layer 16 hole transport layer 17 light emitting layer 18 electron transport layer 19 electron injection layer 20 facing Electrode 21 Sealing layer 111 Base material 101 CS lower electrode 102, 103 Lower insulating layer 104 Semiconductor layer 104b Channel region 104a Drain region 104c Source region 104e Connection electrode 104f CS upper electrode 106 Gate insulating layer 107 Gate electrode 105, 108, 109 inorganic Insulating layer 1010 Organic insulating layer 1101 Hard mask 1102sd, 1102g Upper electrode 1014 Intermediate mask

Claims (11)

Board and
A semiconductor layer provided on the substrate and having a channel region and a pair of contact regions sandwiching the channel region;
A gate electrode provided in the channel region via a gate insulating layer;
An insulating layer that covers the semiconductor layer and the gate electrode and is provided with a contact hole;
A hard mask layer provided on the insulating layer and provided with an opening at a position corresponding to the contact hole;
An upper electrode provided on the hard mask layer and electrically connected to one of the contact region and the gate electrode via the contact hole;
The thin film transistor substrate according to claim 1, wherein an inner diameter of the contact hole provided in the insulating layer increases stepwise from the substrate side toward the upper electrode side. The value of the thickness of the upper electrode on the hard mask layer is equal to or greater than the length of the contact hole in which the inner diameter does not change in the thickness direction of the insulating layer. Thin film transistor substrate. The thin film transistor substrate according to claim 1, wherein the insulating layer further includes an intermediate mask layer having an opening at a position corresponding to the contact hole. The insulating layer includes a plurality of intermediate mask layers for one contact hole,
The thin film transistor substrate according to claim 3, wherein an opening of the intermediate mask layer is larger in an intermediate mask layer closer to the upper electrode. A thin film transistor substrate according to any one of claims 1 to 4,
A pixel electrode electrically connected to each of the upper electrodes,
A light-emitting layer provided on each of the pixel electrodes,
And a common electrode provided on the light emitting layer. Prepare the board,
Providing a semiconductor layer on the substrate,
Providing a gate insulating layer and a gate electrode in a first region of the semiconductor layer;
Providing an insulating layer covering the semiconductor layer and the gate electrode;
Providing a hard mask layer on the insulating layer,
An opening is formed in the hard mask layer, and a contact hole is formed in the insulating layer at a position corresponding to the opening of the hard mask layer, the inner diameter of a portion in contact with the semiconductor being smaller than the inner diameter of the opening of the hard mask layer. ,
An upper electrode connected to each of a second region and a third region sandwiching the first region of the semiconductor layer via the contact hole and the gate electrode is provided on the hard mask layer. Substrate manufacturing method. At least an upper region of the insulating layer in contact with the hard mask is made of an organic material,
Etching the hard mask layer using a mask composed of an organic material when opening an opening in the hard mask layer,
7. The method according to claim 6, wherein, when the contact hole is formed, etching of the upper region and the mask and etching of the hard mask layer are alternately repeated a plurality of times. The amount of increase in the length of the contact hole in the thickness direction of the insulating layer per etching of the upper region is equal to or less than the thickness of the upper electrode on the hard mask. The method for manufacturing a thin film transistor substrate according to claim 7, wherein: When the insulating layer is provided, a process of forming an organic insulating layer with an organic material and a process of forming an intermediate mask layer on the organic insulating layer and providing an opening in the intermediate mask layer are alternately repeated one or more times. The method for manufacturing a thin film transistor substrate according to claim 6, wherein: The method according to claim 9, wherein a thickness of the organic insulating layer is equal to or less than a thickness of the upper electrode on the hard mask. A process of forming an organic insulating layer with an organic material and a process of forming the intermediate mask layer and providing an opening in the intermediate mask layer are performed a plurality of times, and a larger opening is opened in the intermediate mask layer farther from the substrate. The method for manufacturing a thin film transistor substrate according to claim 9.

Images