JP2019134581A - Overcurrent protection circuit of vehicle measuring instrument - Google Patents

Abstract

To provide an overcurrent protection circuit of a vehicle measuring instrument capable of suppressing a voltage loss.SOLUTION: An output circuit 30 comprises: a P-channel FET element Q1 that has a drain terminal D connected with a power supply output part Po, a source terminal S connected with a power supply input part Pi, and a gate terminal G connected with ground; a resistor R1 connected between the gate terminal G and the source terminal S of the P-channel FET element Q1; a capacitor C1 connected between the ground and a power line Lv; a PNP transistor Q2 that has a base terminal B and an emitter terminal E connected with the power line Lv, and in a case where an overcurrent Io is generated in the power line Lv, connects the gate terminal G of the P-channel FET element Q1 with the ground by being turned ON on the basis of a change in a potential difference between the base terminal B and the emitter terminal E; a capacitor C2 connected between the ground and the emitter terminal E of the PNP transistor Q2; and a diode D1 provided between the capacitor C2 and the power line Lv.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an overcurrent protection circuit for a vehicle instrument.

  Conventionally, as described in Patent Document 1, for example, a current detection resistor has been used as means for detecting an overcurrent in order to interrupt the overcurrent.

JP 2006-152765 A

  In the configuration of Patent Document 1, voltage loss due to the current detection resistor is a problem.

  This invention is made | formed in view of the said actual condition, and it aims at providing the overcurrent protection circuit of the meter for vehicles which can suppress a voltage loss.

  In order to achieve the above object, an overcurrent protection circuit for a vehicle meter according to the present invention comprises a power input unit connected to a power supply unit, and a power output unit connected to a display unit for displaying vehicle information. An overcurrent protection circuit for a vehicle instrument comprising a power line connected between the power input unit and the power output unit, a drain terminal connected to the power output unit, and a connection to the power input unit A first switching element comprising a P-channel FET, and a resistor connected between the gate terminal and the source terminal of the first switching element; One end is connected to the ground, and the other end is connected to the power line and a first capacitor connected between the first switching element and the power input unit in the power line. The gate terminal of the first switching element has one terminal and a second terminal, and is turned on based on a change in potential difference between the first terminal and the second terminal when an overcurrent occurs in the power line. A second switching element that applies a voltage for turning off the first switching element, a second capacitor having one end connected to the ground and the other end connected to the second terminal of the second switching element, A first diode provided between the second capacitor and the power line so that its cathode terminal faces the second capacitor;

  According to the present invention, voltage loss can be suppressed in an overcurrent protection circuit for a vehicle meter.

It is a circuit diagram of the meter for vehicles concerning one embodiment of the present invention. It is a timing chart which shows the state of each FET element which concerns on one Embodiment of this invention, each transistor, and a PWM signal. It is a circuit diagram of the meter for vehicles concerning the modification of the present invention.

  An embodiment of a vehicle meter equipped with an overcurrent protection circuit according to the present invention will be described with reference to FIGS. 1 and 2. The vehicle meter according to the present embodiment displays vehicle information such as vehicle speed and engine speed.

(Constitution)
As shown in FIG. 1, the vehicular meter 1 includes a power supply unit 10, a meter unit 20 that generates a drive voltage Vd for driving the display unit 50 based on power from the power supply unit 10, and a meter unit 20. And a display unit 50 that operates based on the drive voltage Vd.

The power supply unit 10 includes an in-vehicle battery Bt. The positive electrode of the in-vehicle battery Bt is connected to the power supply terminal Pv of the instrument unit 20, and the negative electrode of the in-vehicle battery Bt is connected to the ground terminal Pg of the instrument unit 20. The in-vehicle battery Bt supplies power to the instrument unit 20.
In addition to the in-vehicle battery Bt, the power supply unit 10 may include an alternator (not shown) that generates power by driving the engine.

  The display unit 50 is a load that displays vehicle information such as the vehicle speed and the engine speed using the drive voltage Vd, which is a PWM signal from the meter unit 20, as an operating power source. The display unit 50 includes, for example, a liquid crystal display element, an LED (Light Emitting Diode) such as a backlight, or a pointer driving motor.

The instrument unit 20 includes an output circuit 30 with an overcurrent protection function, a power supply circuit 40, and a microcomputer (microcomputer) 60.
The output circuit 30 is an example of an overcurrent protection circuit, and outputs to the display unit 50 under the control of the microcomputer 60 in addition to the function of shutting off after detecting the overcurrent Io accompanying the short circuit of the display unit 50 or the like. It also has a function of generating the drive voltage Vd. Specifically, the output circuit 30 includes a P-channel FET (Field Effect Transistor) element Q1, a N-channel FET element Q4, a PNP transistor Q2, an NPN transistor Q3, diodes D1 and D2, and a capacitor. C1, C2, C3, resistors R1, R2, R3, R4, R5, a power input part Pi and a power output part Po, and a power line Lv.

  The power input unit Pi of the output circuit 30 is connected to the power supply unit 10 via the power circuit 40. The power output unit Po of the output circuit 30 is connected to the display unit 50. The power line Lv is an electric line to which power is supplied, and connects between the power input part Pi and the power output part Po.

  The P-channel FET element Q1 is provided on the power line Lv. When the P-channel FET element Q1 is turned on, the P-channel FET element Q1 conducts the power line Lv. Specifically, the drain terminal D of the P-channel FET element Q1 is connected to the power output part Po. The source terminal S of the P-channel FET element Q1 is connected to the power input part Pi. The gate terminal G of the P-channel FET element Q1 is connected to the ground via the N-channel FET element Q4.

  The parasitic diode Df is connected in parallel to the P-channel FET element Q1. The cathode terminal Ct of the parasitic diode Df faces the power input part Pi, and the anode terminal An of the diode D1 faces the power output part Po.

  The source terminal S of the N channel FET element Q4 is connected to the gate terminal G of the P channel FET element Q1. The drain terminal D of the N-channel FET element Q4 is connected to the ground. The gate terminal G of the N channel FET element Q4 is connected to the microcomputer 60 via the resistor R4. The N-channel FET element Q4 switches the P-channel FET element Q1 on or off by controlling the gate voltage VG of the P-channel FET element Q1 under the control of the microcomputer 60.

  One end of the resistor R5 is connected between the resistor R4 and the microcomputer 60, and the other end of the resistor R5 is connected to the ground.

The PNP transistor Q2, the diodes D1 and D2, and the capacitor C2 are provided for detecting the overcurrent Io.
The base terminal B of the PNP transistor Q2 is connected to a position A1 between the P-channel FET element Q1 and the power input part Pi on the power line Lv. The emitter terminal E of the PNP transistor Q2 is connected to the ground via a capacitor C2. Capacitor C2 is provided for setting emitter voltage VE of PNP transistor Q2 by the charged electric charge. The capacitor C2 is, for example, an electrolytic capacitor. The collector terminal C of the PNP transistor Q2 is connected to the ground via a capacitor C3. The capacitor C3 has a function of extending the time from when the PNP transistor Q2 is turned on until the overcurrent Io is cut off by adjusting the capacitance value of the capacitor C3, in addition to the function of suppressing chattering of the PNP transistor Q2. . The capacitor C3 is a ceramic capacitor, for example.

  The diodes D1 and D2 are connected between the emitter terminal E and the base terminal B in the PNP transistor Q2. The diodes D1 and D2 are connected in parallel in different directions. Specifically, the cathode terminal Ct of the diode D1 faces the capacitor C2 and the emitter terminal E of the PNP transistor Q2, and the anode terminal An of the diode D1 faces the power line Lv. The cathode terminal Ct of the diode D2 faces the power line Lv, and the anode terminal An of the diode D2 faces the capacitor C2 and the emitter terminal E of the PNP transistor Q2. The diodes D1, D2 are provided to form a potential difference between the emitter terminal E and the base terminal B in the PNP transistor Q2. Thereby, the PNP transistor Q2 is prevented from being inadvertently switched between on and off due to voltage fluctuations such as noise, and the operation of the PNP transistor Q2 can be stabilized.

  The base terminal B of the NPN transistor Q3 is connected between the capacitor C3 and the collector terminal C of the PNP transistor Q2 via the resistor R2. The resistor R2 is provided for adjusting the current flowing from the capacitor C2 through the PNP transistor Q2 to the base terminal B of the NPN transistor Q3. One end of the resistor R3 is connected between the resistor R2 and the base terminal B of the NPN transistor Q3, and the other end of the resistor R3 is connected to the ground. The resistor R3 is provided in order to stabilize the potential difference between the base and emitter of the NPN transistor Q3 and to suppress malfunction of the NPN transistor Q3 due to voltage fluctuations such as noise. The emitter terminal E of the NPN transistor Q3 is connected to the ground. The collector terminal C of the NPN transistor Q3 is connected between the gate terminal G of the N-channel FET element Q4 and the resistor R4. The NPN transistor Q3 is turned on when the overcurrent Io is cut off to flow the PWM control signal Spwm from the microcomputer 60 to the ground, thereby forcibly turning off the P-channel FET element Q1 and the N-channel FET element Q4. Let

  One end of the capacitor C1 is connected to the position A2 of the power line Lv, and the other end of the capacitor C1 is connected to the ground. The capacitor C1 is provided to stabilize the power supplied to the power line Lv. The capacitor C1 is, for example, an electrolytic capacitor.

  The power supply circuit 40 is a circuit that receives a power supply voltage from the in-vehicle battery Bt. The power supply circuit 40 includes, for example, a noise filter that removes noise included in the power supply voltage, a surge protection circuit that cuts a surge included in the power supply voltage, or a switching regulator circuit such as a DC / DC converter.

  The microcomputer 60 includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The microcomputer 60 generates a PWM control signal Spwm having a predetermined duty ratio, and outputs the PWM control signal Spwm to the gate terminal G of the N-channel FET element Q4. The PWM control signal Spwm repeats Hi and Lo as shown in FIG. When the overcurrent Io is not generated, the microcomputer 60 applies the Hi of the PWM control signal Spwm to the gate terminal G of the N-channel FET element Q4 to turn on the N-channel FET element Q4, and thus the P-channel FET element Q1. By applying Lo of the PWM control signal Spwm to the gate terminal G of the N-channel FET element Q4, the N-channel FET element Q4 and thus the P-channel FET element Q1 are turned off. As a result, the drive voltage Vd corresponding to the PWM control signal Spwm is generated. The microcomputer 60 changes the duty ratio of the PWM control signal Spwm in accordance with vehicle information from an external ECU (Electronic Control Unit).

(Function)
Next, the operation of the normal output circuit 30 in which the normal current In within the normal range is supplied to the power line Lv without causing the overcurrent Io will be described with reference to FIG. Under normal conditions, the normal current In flows into the capacitor C1 and also flows into the capacitor C2 via the diode D1. When the charging of the capacitors C1 and C2 is completed, the capacitor C2 is charged with a charge lower than the capacitor C1 by the voltage drop of the diode D1. Here, a voltage equivalent to the potential of the capacitor C1 is applied to the base terminal B of the PNP transistor Q2, and a voltage equivalent to the potential of the capacitor C2 is applied to the emitter terminal E of the PNP transistor Q2. Therefore, in the PNP transistor Q2, the base voltage VB becomes higher than the emitter voltage VE by the voltage drop of the diode D1, thereby turning off the PNP transistor Q2. When the PNP transistor Q2 is off, the capacitor C3 is not charged, so the NPN transistor Q3 is also turned off.

  In this normal time, when the Lo of the PWM control signal Spwm is output from the microcomputer 60, the gate terminal G of the N-channel FET element Q4 is connected to the ground via the resistors R4 and R5. As a result, the potential difference between the gate and source of the N-channel FET element Q4 becomes equal to or greater than the threshold value, and the N-channel FET element Q4 is turned off. When the N-channel FET element Q4 is turned off, an equivalent voltage is applied to the source terminal S and the gate terminal G of the P-channel FET element Q1 via the resistor R1. As a result, the potential difference between the gate and the source of the P channel FET element Q1 becomes smaller than the threshold value, the P channel FET element Q1 does not satisfy the ON condition, and the P channel FET element Q1 is turned OFF. At this time, the drain voltage VD of the P-channel FET element Q1 is substantially 0V.

  On the other hand, in this normal time, when the Hi of the PWM control signal Spwm is output from the microcomputer 60, the potential difference between the gate and the source of the N channel FET element Q4 becomes smaller than the threshold value, so that the N channel FET element Q4. Turns on. When the N channel FET element Q4 is turned on, the gate terminal G of the P channel FET element Q1 is connected to the ground via the N channel FET element Q4. As a result, the gate voltage VG of the P-channel FET element Q1 becomes 0V. Therefore, when the potential difference between the gate and the source becomes larger than the threshold value, the on condition of the P channel FET element Q1 is satisfied, and the P channel FET element Q1 is turned on. When the P-channel FET element Q1 is turned on, the current input to the source terminal S of the P-channel FET element Q1 flows from the drain terminal D toward the power output part Po.

Next, the operation of the output circuit 30 when the display unit 50 as a load is short-circuited and an overcurrent Io is generated will be described.
When the overcurrent Io is generated, the voltage applied to the power line Lv rapidly decreases. Thereby, the electric charge charged in the capacitor C1 is discharged to the power line Lv and flows so as to pass through the P-channel FET element Q1. When the potential of the capacitor C1 decreases, the charge of the capacitor C2 is released to the power line Lv through the diode D2. As a result, the diode D2 generates an emitter-base potential difference, for example, −0.7 V, necessary to turn on the PNP transistor Q2. At the same time, a current flows out from the base terminal B of the PNP transistor Q2 to the power line Lv. Thus, when an overcurrent occurs, the PNP transistor Q2 is switched from off to on.

  When the PNP transistor Q2 is turned on, the charge charged in the capacitor C2 flows from the collector terminal C of the PNP transistor Q2 to the ground via the capacitor C3. As a result, the capacitor C3 is charged. A predetermined charging time is required to charge the capacitor C3 to the potential required to turn on the NPN transistor Q3. This charging time is set by the capacitance value of the capacitor C3. Therefore, when the charge time has elapsed after the PNP transistor Q2 is turned on, the capacitor C3 is charged with the required potential, and the NPN transistor Q3 is turned on. When the NPN transistor Q3 is turned on, the gate terminal G of the N-channel FET element Q4 is connected to the ground via the NPN transistor Q3. At this time, the PWM control signal Spwm from the microcomputer 60 flows to the ground via the NPN transistor Q3. As a result, the N-channel FET element Q4 and thus the P-channel FET element Q1 are kept off. Therefore, the overcurrent Io can be cut off.

Next, the state of the current I supplied to the P-channel FET element Q1, the PNP transistor Q2, the NPN transistor Q3, the N-channel FET element Q4, the PWM control signal Spwm, and the power line Lv will be described according to the timing chart shown in FIG.
In the normal period T1 in which the overcurrent Io does not occur, the PNP transistor Q2 and the NPN transistor Q3 are kept off as described above, and the P-channel FET element Q1 and the N-channel according to the Hi and Lo of the PWM control signal Spwm. The FET element Q4 switches between on and off.
Immediately after the occurrence of the overcurrent Io at time ta, the PNP transistor Q2 is first switched from off to on. Then, at time tb when the charge time Tch has elapsed since the PNP transistor Q2 was turned on, the NPN transistor Q3 is switched from off to on. Since the NPN transistor Q3 is turned on after time tb, the P-channel FET element Q1 and the N-channel FET element Q4 are kept off regardless of the PWM control signal Spwm. Thereby, the overcurrent Io becomes 0 A, and the power supply circuit 40 can be protected from the overcurrent Io.

  After time tb, during the period when the P-channel FET element Q1 is turned off, the capacitors C1 and C2 are charged. As a result, the PNP transistor Q2 is turned off in the same state as in the normal state. For this reason, the electric charge charged in the capacitor C3 is released, the NPN transistor Q3 cannot be kept on, and the NPN transistor Q3 is turned off. In this case, when Hi of the PWM control signal Spwm is output from the microcomputer 60, the P-channel FET element Q1 and the N-channel FET element Q4 are turned on. At this time, if the short-circuit state has not been eliminated, the output circuit 30 interrupts the overcurrent Io by performing the operation after the time ta again. On the other hand, if the short circuit state is eliminated at this time, the output circuit 30 performs the operation in the normal period T1.

(effect)
As mentioned above, according to one Embodiment described, there exist the following effects.

(1) The output circuit 30 with an overcurrent protection function corresponding to the overcurrent protection circuit of the vehicle meter 1 is connected to a power input unit Pi connected to the power supply unit 10 and a display unit 50 that displays vehicle information. A power output unit Po. The output circuit 30 is provided on the power line Lv connected between the power supply input part Pi and the power supply output part Po, the drain terminal D connected to the power supply output part Po, the source terminal S connected to the power supply input part Pi, And a P-channel FET element Q1 corresponding to the first switching element, a resistor R1 connected between the gate terminal G and the source terminal S of the P-channel FET element Q1, One end is connected to the ground, and the other end is connected to the capacitor C1 corresponding to the first capacitor connected between the P-channel FET element Q1 and the power input portion Pi in the power line Lv, and the first terminal connected to the power line Lv. When an overcurrent Io is generated in the power line Lv, the base terminal B and the emitter terminal E are provided. A PNP transistor Q2 corresponding to a second switching element that applies a voltage for turning off the P-channel FET element Q1 to the gate terminal G of the P-channel FET element Q1 by being turned on based on a change in potential difference between them, and one end connected to the ground The other end is provided between a capacitor C2 corresponding to a second capacitor connected to the emitter terminal E of the PNP transistor Q2, and between the capacitor C2 and the power line Lv such that its own cathode terminal Ct faces the capacitor C2. And a diode D1 corresponding to one diode.
According to this configuration, when an overcurrent Io occurs due to a short circuit, the PNP transistor Q2 is turned on, so that a voltage equivalent to that of the source terminal S is applied to the gate terminal G of the P-channel FET element Q1 via the resistor R1. Is done. As a result, the P-channel FET element Q1 is turned off and the overcurrent Io is cut off. In this configuration, since the current detection resistor having a large voltage loss is not used to detect the overcurrent Io, the voltage loss can be suppressed. Thereby, the voltage close | similar to the power supply voltage from the vehicle-mounted battery Bt can be supplied to the display part 50. FIG.
In addition, in the conventional method using the current detection resistor, it is necessary to set a larger threshold for overcurrent determination as the current supplied to the power line becomes larger. In this case, an error with a smaller resistance value is required. It is necessary to use a low resistance, and such a resistor is generally expensive. In the above configuration, even when the current supplied to the power line Lv is large, the expensive resistor can be used without being expensive.
Furthermore, the potential difference between the base and emitter of the PNP transistor Q2 is controlled by the capacitor C2 and the diode D2 so that the PNP transistor Q2 is turned on when an overcurrent Io is generated and is normally turned off. . This suppresses inadvertent switching of the PNP transistor Q2 between on and off due to voltage fluctuations such as noise, and allows the PNP transistor Q2 and thus the P-channel FET element Q1 to operate stably.

(2) The PNP transistor Q2 includes a base terminal B, an emitter terminal E, and a collector terminal C connected to the ground. The output circuit 30 includes a capacitor C3 corresponding to a third capacitor connected between the collector terminal C of the PNP transistor Q2 and the ground, and a base terminal B connected between the capacitor C3 and the collector terminal C of the PNP transistor Q2. An NPN transistor Q3 corresponding to a third switching element having an emitter terminal E and a collector terminal C connected to the ground, a drain terminal D connected to the ground, and a source connected to the gate terminal G of the P-channel FET element Q1 The microcomputer 60 which transmits the terminal S and PWM control signal Spwm, and the gate terminal G connected to the collector terminal C of the NPN transistor Q3 are provided, and the N channel FET element Q4 equivalent to a 4th switching element is provided.
According to this configuration, when an overcurrent Io occurs due to a short circuit, the PNP transistor Q2 is turned on to start charging the capacitor C3. When the charge time Tch elapses after the PNP transistor Q2 is turned on, the NPN transistor Q3 is turned on by the charge charged in the capacitor C3. Thereby, the gate terminal G of the N channel FET element Q4 is connected to the ground. Therefore, the P-channel FET element Q1 and the N-channel FET element Q4 are kept off regardless of the PWM control signal Spwm from the microcomputer 60. The overcurrent Io is cut off by turning off the channel FET element Q1.
In the above configuration, during normal times when no overcurrent Io is generated, the microcomputer 60 outputs the PWM control signal Spwm to the gate terminal G of the N-channel FET element Q4, thereby turning the channel FET element Q1 on and off. Switch with. Thereby, the output circuit 30 can generate the drive voltage Vd. As described above, the P-channel FET element Q1 and the N-channel FET element Q4 are used to generate the drive voltage Vd during normal times, and are used to cut off the overcurrent Io when an overcurrent occurs. Therefore, it is not necessary to provide a new FET for overcurrent protection, and a simpler configuration can be realized.
In the above configuration, the PNP transistor Q2 and the NPN transistor Q3 are kept off during normal times when the overcurrent Io is not generated, and no current flows to the ground. For this reason, electric power required in order to monitor the presence or absence of overcurrent can be reduced.
Further, since the output circuit 30 is composed of a combination of FETs, transistors, and diodes, which are general electric components, it can be configured at a lower cost than in the past.
Conventionally, for example, it is conceivable that the microcomputer detects a voltage value applied to the power line and determines whether or not an overcurrent has occurred based on a comparison between the detected voltage value and an overcurrent determination threshold. However, in this conventional configuration, it is necessary to set a plurality of overcurrent determination thresholds in accordance with a change in the duty ratio of the PWM control signal. In addition, when the duty ratio of the PWM control signal is small, the average value of the detected voltage values approaches 0 V, so that it is difficult to distinguish from a voltage drop when an overcurrent occurs. In the configuration of the present embodiment, the output circuit 30 can block the overcurrent Io regardless of the change in the duty ratio of the PWM control signal Spwm. For this reason, the configuration of the present embodiment does not cause a problem as in the conventional configuration.

(3) The output circuit 30 includes a diode D2 corresponding to a second diode provided in parallel with the diode D1 between the capacitor C2 and the power line Lv so that its cathode terminal Ct faces the power line Lv.
According to this configuration, the potential difference between the base and the emitter of the PNP transistor Q2 is controlled by the diode D2. Thereby, it is possible to suppress the PNP transistor Q2 from being erroneously turned on due to voltage fluctuations such as noise during normal times, and to stabilize the operation of the PNP transistor Q2.

(Modification)
In addition, the said embodiment can be implemented with the following forms which changed this suitably.

In the above embodiment, the output circuit 30 includes one diode D1 and one diode D2, but may include a plurality of diodes. For example, as shown in FIG. 3, the plurality of diodes D1a to D1n are connected in series, and the plurality of diodes D2a to D2n are connected in series. “N” is an arbitrary natural number. The diodes D2a to D2n connected in series with the diodes D1a to D1n connected in series are connected in parallel to each other. According to this configuration, the voltage difference between the diodes D1a to D1n and D2a to D2n can easily set a large potential difference between the emitter and the base of the PNP transistor Q2. Thereby, the operation of the PNP transistor Q2 can be stabilized.
Further, as shown in FIG. 3, the output circuit 30 may include a resistor R6 connected in parallel with the capacitor C2. The forward voltage of the diodes D1a to D1n can be brought close to the saturation voltage by the resistor R6.

  Further, the collector terminal C of the NPN transistor Q3 may be connected to the microcomputer 60 as shown in FIG. In this case, when the microcomputer 60 detects that the NPN transistor Q3 is turned on when an overcurrent is generated, the microcomputer 60 outputs Lo to the gate terminal G of the N-channel FET element Q4.

  You may implement | achieve by the other circuit structure which substitutes for the microcomputer 60 of the output circuit 30 shown in FIG. 1 in the said embodiment.

  In the above embodiment, the output circuit 30 may include a surge absorber such as a Zener diode on the upstream side (drain terminal D side) of the P-channel FET element Q1.

  In the above embodiment, the capacitors C1 and C2 are electrolytic capacitors, but are not limited to electrolytic capacitors, and may be ceramic capacitors or tantalum capacitors. Similarly, the capacitor C3 is a ceramic capacitor, but is not limited to a ceramic capacitor, and may be an electrolytic capacitor or a tantalum capacitor.

  The transistors Q2 and Q3 in the above embodiment may be FETs. In this case, the ON condition of the FET is set so as to exhibit the same operation and effect as in the above embodiment.

DESCRIPTION OF SYMBOLS 1 Vehicle instrument 10 Power supply part 20 Instrument unit 30 Output circuit 40 Power supply circuit 50 Display part 60 Microcomputer 130 Overcurrent protection circuit C1, C2, C3 Capacitor D1, D2, D1a-D1n, D2a-D2n Diode Q1 P channel FET element Q2 PNP transistor Q3 NPN transistor Q4 N-channel FET elements R1, R2, R3, R4, R5, R6 Resistor Bt Car battery Lv Power line Spwm PWM control signal

Claims (3)

An overcurrent protection circuit for a vehicle meter comprising a power input unit connected to a power supply unit and a power output unit connected to a display unit for displaying vehicle information,
A drain terminal connected to the power output unit, a source terminal connected to the power input unit, and a gate terminal connected to the ground, provided on a power line connected between the power input unit and the power output unit A first switching element comprising a P-channel FET,
A resistor connected between the gate terminal and the source terminal of the first switching element;
A first capacitor having one end connected to the ground and the other end connected between the first switching element in the power line and the power input unit;
A first terminal and a second terminal connected to the power line, respectively, and when an overcurrent occurs in the power line, the power line is turned on based on a change in potential difference between the first terminal and the second terminal; A second switching element that applies a voltage for turning off the first switching element to the gate terminal of the first switching element;
A second capacitor having one end connected to the ground and the other end connected to the second terminal of the second switching element;
A first diode provided between the second capacitor and the power line so that its cathode terminal faces the second capacitor;
Overcurrent protection circuit for vehicle meters. The second switching element comprises a PNP transistor comprising a base terminal as the first terminal, an emitter terminal as the second terminal, and a collector terminal connected to the ground,
The overcurrent protection circuit is
A third capacitor connected between the collector terminal of the second switching element and the ground;
A third switching element comprising an NPN transistor comprising a base terminal connected between the third capacitor and the collector terminal of the second switching element, an emitter terminal connected to the ground, and a collector terminal;
A drain terminal connected to the ground, a source terminal connected to the gate terminal of the first switching element, a microcomputer transmitting a PWM control signal, and a gate terminal connected to the collector terminal of the third switching element. And a fourth switching element made of an N-channel FET.
The overcurrent protection circuit of the vehicle meter according to claim 1. A second diode provided between the second capacitor and the power line in parallel with the first diode so that its cathode terminal faces the power line;
The overcurrent protection circuit for the vehicle meter according to claim 1 or 2.

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