JP2019188456A - はんだ合金、ソルダペースト、成形はんだ、及びはんだ合金を用いた半導体装置 - Google Patents
はんだ合金、ソルダペースト、成形はんだ、及びはんだ合金を用いた半導体装置 Download PDFInfo
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- JP2019188456A JP2019188456A JP2018087111A JP2018087111A JP2019188456A JP 2019188456 A JP2019188456 A JP 2019188456A JP 2018087111 A JP2018087111 A JP 2018087111A JP 2018087111 A JP2018087111 A JP 2018087111A JP 2019188456 A JP2019188456 A JP 2019188456A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
Description
本実施の形態1のはんだ合金は、融点が、例えば、260℃以上の高温はんだ合金に属するものである。本実施の形態1のはんだ合金は、全体の質量%のうち、質量%が0.03質量%〜0.09質量%のNi(ニッケル)と、全体からNi及び不可避不純物を除いた残部であるBiとを有する。本実施の形態1では、例えば、Niの質量%が0.03質量%〜0.09質量%である場合、Bi−0.03%〜0.09%Ni合金と表記する。
本実施の形態1のはんだ合金として、Bi−0.03%〜0.09%Ni合金の製造方法を説明する。Bi及びNiの各原料は純度が99.9%以上のものを使用することが好ましい。Bi−0.03%〜0.09%Ni合金は、Bi及びNiと、不可避不純物とからなる。不可避不純物とは、主として、Cu(銅)、Ni、Zn(亜鉛)、Fe(鉄)、Al(アルミニウム)、As(ヒ素)、Cd(カドミウム)、Ag、Au(金)、In(インジウム)、P(リン)、Pb及びSnなどである。本実施の形態1では、Niを除いた不可避不純物の合計の質量%は、はんだ合金全体のうち、0.01%未満である。特に、Snについて、本実施の形態1のはんだ合金は、不可避不純物としての質量%しか含んでいない。Bi−Sn共晶組成がはんだ合金の融点を低下させることを防ぐためである。
本実施の形態1のはんだ合金の基本特性として、Bi−Ni系合金の二元系状態図について説明する。図1は、Bi−Ni系合金の二元系状態図である。図1の横軸はBiへのNiの添加量[質量%]であり、縦軸は温度である。図1では、Niの添加量が0〜0.4%の範囲の状態図を示し、温度については、272℃以上の状態図の表示を省略している。
本実施の形態1のはんだ合金は、BiにNiを添加したBi基合金に相当するが、Niを0.03質量%〜0.09質量%含有するものである。本実施の形態1のはんだ合金のうち、Niを0.05質量%〜0.07質量%含有する場合、延性がより大きくなり、塑性加工性の観点からより優れている。ここでは、Bi−0.07%Ni合金について圧延評価の結果を説明する。
本実施の形態1のはんだ合金について、濡れ性を評価した。濡れ性評価では、比較例としてBi単体を用いた。濡れ性の評価には、濡れ広がり試験における濡れ広がり率を用いた。評価に用いた濡れ広がり率の定義を、図7を参照して説明する。図7は、はんだの濡れ広がり率の定義を説明するための模式図である。
Bi単体は、融点が高い点では、Pbフリー高温はんだの候補の1つとなり得るが、電気抵抗が従来のPbフリー高温はんだに比べて大きい。図9は、BiへのNi添加量と電気抵抗との関係を示すグラフである。
実施の形態1で説明したはんだ合金の使用形態の一例として、はんだ合金の粉末とフラックスとを混錬したソルダペーストが考えられる。本実施の形態2は、実施の形態1で説明したはんだ合金をソルダペーストに適用したものである。
実施の形態1で説明したBi−0.05%〜0.07%Ni合金は、延性がより大きく、圧延可能であることから、はんだの使用形態として、実施の形態2で説明したソルダペーストだけでなく、成形はんだとすることができる。本実施の形態3は、実施の形態1で説明したはんだ合金を、成形はんだに適用したものである。
Claims (7)
- 全体の質量%のうち、0.03質量%〜0.09質量%のニッケルと、
全体から前記ニッケル及び不可避不純物を除いた残部であるビスマスと、
からなるはんだ合金。 - 前記ニッケルを0.05質量%〜0.07質量%含有する、請求項1に記載のはんだ合金。
- 請求項1又は2に記載のはんだ合金の粉末と、
フラックスと、
を有するソルダペースト。 - 請求項1又は2に記載のはんだ合金が一定の形状に成形された成形はんだ。
- 半導体チップと、
前記半導体チップを支持するダイパッドと、
前記半導体チップと前記ダイパッドとの間に設けられた、請求項1又は2に記載のはんだ合金と、
前記半導体チップ及び前記ダイパッドを覆う樹脂と、
を有する半導体装置。 - 半導体チップと、
前記半導体チップを支持する絶縁基板と、
前記絶縁基板と前記半導体チップとの間に設けられた、請求項1又は2に記載のはんだ合金と、
を有する半導体装置。 - 半導体チップを支持する絶縁基板と、
前記半導体チップから発生する熱を放出する放熱板と、
前記絶縁基板と前記放熱板との間に設けられた、請求項1又は2に記載のはんだ合金と、
を有する半導体装置。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2021153447A1 (ja) * | 2020-01-30 | 2021-08-05 | ローム株式会社 | 半導体装置 |
WO2024048887A1 (ko) * | 2022-09-01 | 2024-03-07 | 서울과학기술대학교 산학협력단 | 소결 접합용 필름의 제조 방법과 전력 반도체 패키지의 제조 방법 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2021153447A1 (ja) * | 2020-01-30 | 2021-08-05 | ローム株式会社 | 半導体装置 |
WO2024048887A1 (ko) * | 2022-09-01 | 2024-03-07 | 서울과학기술대학교 산학협력단 | 소결 접합용 필름의 제조 방법과 전력 반도체 패키지의 제조 방법 |
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