JP2019179447A - Electronic apparatus, control method for electronic apparatus, and program - Google Patents

Abstract

To quickly activate the entire device.SOLUTION: The present invention is an electronic apparatus comprising a sub-unit including a sub-controller, and a main unit including a main controller for controlling the sub-controller and connected to the sub-controller by a prescribed communication scheme. The main controller determines whether communication of the main controller with the sub-controller has been enabled, and the sub-controller further includes storage means, connected to the sub-controller, for storing a program that includes a master task needed for enabling communication of the main controller with the sub-controller and a slave task needed for activating electronic apparatuses other than the master task. When a power supply shutoff state in the sub-controller is released, the master task is executed preferentially over the slave task, and the slave task is executed in parallel with a process of determining whether communication in the main controller is enabled.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an electronic device, a control method for the electronic device, and a program.

  2. Description of the Related Art Conventionally, electronic devices (apparatuses) mounted with a plurality of integrated circuit chips, for example, recording apparatuses, which are recording apparatuses that share the overall control of the recording apparatus, image processing, mechanical control, and the like, have been commercialized. .

  Here, for example, Patent Document 1 discloses an information processing apparatus that starts a sub controller by transferring a start program from a main controller to a sub controller in a configuration in which a plurality of integrated circuit chips are connected in cascade. Yes.

  Specifically, in the information processing apparatus disclosed in Patent Document 1, first, the activation program is transferred from the main controller to the first sub-controller, and after the activation program is transferred, the main controller executes the first sub-controller. Release the reset. Next, when the reset is released, the first sub controller activates the first sub controller. Similarly, the second sub controller is activated by transferring the activation program from the main controller to the second sub controller connected to the first sub controller via the first sub controller.

JP, 2006-218976, A

  However, in the information processing apparatus of Patent Document 1, when the sub-controller receives the transfer of the start-up program, before connecting (establishing) the link with the main controller or another sub-controller, the sub-controller Running. Therefore, there is a problem that it takes time to start up the entire apparatus (that is, to make it usable).

  Accordingly, the present invention has been made in view of the above-described conventional problems, and an object thereof is to start up the entire apparatus at high speed.

  The present invention is an electronic device comprising a sub-unit having a sub-controller, and a main unit having a main controller that is connected to the sub-controller by a predetermined communication method and controls the sub-controller. Determining whether communication between the main controller and the sub-controller is enabled, and the sub-controller is connected to the sub-controller, and is necessary for enabling communication between the main controller and the sub-controller. A storage means for storing a program including a parent task to be executed and a child task necessary for starting the electronic device other than the parent task, and when the power-off state in the sub-controller is released, Execute the parent task in preference to the child task, and In parallel with the process of determining whether the communication is enabled in the emission controller, and executes a child task.

  According to the present invention, the entire apparatus can be activated at high speed.

It is an internal block diagram of an inkjet recording device. It is a control block diagram of an inkjet recording device. It is a reset block diagram of an inkjet recording device. It is a flowchart which shows the starting process of an inkjet recording device.

  Hereinafter, a recording apparatus according to an embodiment of the present invention will be described with reference to the drawings. The following embodiments do not limit the present invention, and all combinations of features described in the present embodiment are not necessarily essential to the solution means of the present invention.

  FIG. 1 is an internal configuration diagram of an ink jet recording apparatus 1 (hereinafter, recording apparatus 1). In the figure, the x direction indicates the horizontal direction, the y direction (perpendicular to the paper surface) indicates the direction in which the ejection openings are arranged in the recording head 8 described later, and the z direction indicates the vertical direction.

  The recording apparatus 1 is a multifunction machine including a printing unit 2 and a scanner unit 3, and can perform various processes relating to a recording operation and a reading operation individually or in conjunction with the printing unit 2 and the scanner unit 3. The scanner unit 3 includes an ADF (automatic document feeder) and an FBS (flatbed scanner), and reads a document automatically fed by the ADF and reads a document placed on a document table of the FBS by a user (scanning). )It can be performed. In this example, the MFP has both the print unit 2 and the scanner unit 3, but the scanner unit 3 may be omitted. Further, FIG. 1 shows a state in which the recording apparatus 1 is in a standby state in which neither recording operation nor reading operation is performed.

  In the print unit 2, a first cassette 5 </ b> A and a second cassette 5 </ b> B for accommodating a recording medium (cut sheet) S are detachably installed on the bottom of the casing 4 in the vertical direction. A relatively small recording medium up to A4 size is accommodated in the first cassette 5A, and a relatively large recording medium up to A3 size is accommodated in the second cassette 5B. Near the first cassette 5A, a first feeding unit 6A for separating and feeding the stored recording media one by one is provided. Similarly, a second feeding unit 6B is provided in the vicinity of the second cassette 5B. When a recording operation is performed, the recording medium S is selectively fed from one of the cassettes.

  The transport roller 7, the discharge roller 12, the pinch roller 7a, the spur 7b, the guide 18, the inner guide 19 and the flapper 11 are transport mechanisms for guiding the recording medium S in a predetermined direction. The conveyance roller 7 is a driving roller that is arranged on the upstream side and the downstream side of the recording head 8 and is driven by a conveyance motor (not shown). The pinch roller 7 a is a driven roller that rotates while nipping the recording medium S together with the conveying roller 7. The discharge roller 12 is a drive roller that is disposed on the downstream side of the transport roller 7 and is driven by a transport motor (not shown). The spur 7 b sandwiches and transports the recording medium S together with the transport roller 7 and the discharge roller 12 disposed on the downstream side of the recording head 8.

  The guide 18 is provided in the conveyance path of the recording medium S and guides the recording medium S in a predetermined direction. The inner guide 19 has a side surface curved by a member extending in the y direction, and guides the recording medium S along the side surface. The flapper 11 is a member for switching the direction in which the recording medium S is conveyed during the double-side recording operation. The discharge tray 13 is a tray for stacking and holding the recording medium S discharged by the discharge roller 12 after the recording operation is completed.

  The recording head 8 is a line head type color inkjet recording head, and a plurality of ejection openings for ejecting ink according to the recording data are arranged along the y direction in FIG. 1 corresponding to the width of the recording medium S. Yes. When the recording head 8 is in the standby position, the ejection port surface 8a of the recording head 8 is capped by the cap unit 10 as shown in FIG. When the recording operation is performed, the orientation of the recording head 8 is changed by a print engine unit 940 described later so that the discharge port surface 8 a faces the platen 9. The platen 9 is constituted by a flat plate extending in the y direction, and supports the recording medium S on which the recording operation is performed by the recording head 8 from the back side.

  The ink tank unit 14 stores the four colors of ink supplied to the recording head 8. The ink supply unit 15 is provided in the middle of the flow path connecting the ink tank unit 14 and the recording head 8, and adjusts the pressure and flow rate of the ink in the recording head 8 to an appropriate range. The recording apparatus 1 has a circulation type ink supply system, and the ink supply unit 15 adjusts the pressure of ink supplied to the recording head 8 and the flow rate of ink recovered from the recording head 8 to an appropriate range. The maintenance unit 16 includes a cap unit 10 and a wiping unit 17 and operates them at a predetermined timing to perform a maintenance operation on the recording head 8.

  Next, the control configuration of the recording apparatus 1 will be described. The recording apparatus 1 mainly includes a print engine unit 940 that controls the printing unit 2, a scanner engine unit 300 that controls the scanner unit 3, and a controller unit 900 that controls the entire recording apparatus 1. The print engine unit 940 controls various mechanisms in accordance with instructions from the controller unit 900 (main controller ASIC 1001). The print engine unit 940 includes a plurality of image processing controllers and a recording control controller, divides the image data generated by the controller unit, and executes image processing in parallel by each of the plurality of image processing controllers. Hereinafter, the control configuration of the recording apparatus 1 will be described with reference to FIG.

  FIG. 2 is a block diagram illustrating a control configuration of the recording apparatus 1. The recording apparatus 1 includes a controller unit 900 and a print engine unit 940 including a first image processing controller unit 910, a second image processing controller unit 920, and a recording control controller unit 930. That is, the recording apparatus 1 includes four controller units.

  The controller unit 900 functions as a main unit that generates image data to be subjected to image processing by the first image processing controller unit 910 and the second image processing controller unit 920. On the other hand, the first image processing controller unit 910 and the second image processing controller unit 920 function as subunits for the controller unit 900. Hereinafter, supplementary explanations will be given regarding these units.

  As described above, the controller unit 900 generates image data to be image processed by the first image processing controller unit 910 and the second image processing controller unit 920 based on the input print job.

  A CPU (Central Processing Unit) 901 of the controller unit 900 is an arithmetic device that controls the entire controller unit in accordance with a program or the like stored in the ROM 907. The renderer processing unit 902 generates image data for one page based on page description language (hereinafter, PDL) data transmitted from the host device 400 via the host IF control unit 904. The scanner image processing unit 903 generates image data for one page based on the scan data transmitted from the scanner engine unit 300 via the scanner IF control unit 905.

  Image data generated by the renderer processing unit 902 or the scanner image processing unit 903 is temporarily stored in the RAM 908 of the controller unit 900 and transmitted to the first image processing controller unit 910 or the second image processing controller unit 920. Hereinafter, a RAM area in which image data to be transmitted is stored is referred to as a transmission buffer area.

  The image data stored in the transmission buffer area is transmitted to the first image processing controller unit 910 via the inter-ASIC IF control unit 906 and stored in the RAM 918 of the first image processing controller unit 910. Hereinafter, a RAM area in which received image data is stored is referred to as a reception buffer area. In this embodiment, a PCI Express standard (registered trademark) communication method (that is, a serial communication method) is used as the inter-ASIC IF. Further, protocol processing and DMA control in PCI Express (hereinafter, PCIe) are executed by the inter-ASIC IF control unit 906 (913).

  The CPU 911 of the first image processing controller unit 910 determines whether the image data stored in the reception buffer area of the RAM 918 is image data to be processed in the first image processing controller unit 910. That is, the CPU 911 of the first image processing controller unit 910 determines whether the image data is the target of the recording data generation process in the first image processing controller unit 910.

  As a result of the determination, when it is determined that the image data is image data to be subjected to recording data generation processing, the CPU 911, based on the image data stored in the reception buffer area of the RAM 918, the image processing unit 912. To generate record data.

  The image processing unit 912 generates recording data based on the image data stored in the reception buffer area of the RAM 918 in accordance with the instruction from the CPU 911 described above, and stores the generated recording data in the RAM 918. Hereinafter, the RAM area in which the recording data is stored is referred to as a print buffer area.

  The recording data stored in the print buffer area of the RAM 918 is transmitted to the second image processing controller unit 920 via the inter-ASIC IF control unit 914 and stored in the print buffer area of the RAM 928.

  On the other hand, if it is determined that the image data is not the image data to be recorded, the image data stored in the reception buffer area of the RAM 918 is transferred to the second image via the inter-ASIC IF control unit 914. Transfer to the processing controller unit 920. The transferred image data is stored in the reception buffer area of the RAM 928 of the second image processing controller unit 920.

  The image processing unit 922 of the second image processing controller unit 920 generates recording data based on the image data stored in the reception buffer area of the RAM 928. The recording data generated by the image processing unit 922 is stored in the print buffer area of the RAM 928. Note that since the print data generated by the first image processing controller unit 910 is also stored in the print buffer area of the RAM 928, finally, print data for one page is generated in the print buffer area of the RAM 928. It will be.

  When generation of recording data for one page is completed in the print buffer area of the RAM 928, the CPU 921 notifies the recording control controller unit 930 of a recording start notification based on the recording data for one page. After this recording start notification, the CPU 921 transmits the recording data stored in the print buffer area of the RAM 928 to the recording control controller unit 930 via the inter-ASIC IF control unit 924. The transmitted recording data is stored in the RAM 938 of the recording controller unit 930.

  When the recording start notification is notified from the second image processing controller unit 920, the recording control controller unit 930 receives the recording data and stores the received recording data in the RAM 938. Thereafter, the HV processing unit 931 performs HV conversion processing on the recording data stored in the RAM 938. The HV processing unit 931 stores the recording data rearranged by the HV conversion processing in the RAM 938 again. The recording control unit 934 controls the recording operation of recording an image on a recording medium such as paper by transmitting the recording data after the HV conversion processing stored in the RAM 938 to the recording head 8.

  FIG. 3 is a reset configuration diagram of the recording apparatus 1. Hereinafter, the reset configuration of the controller unit 900, the first image processing controller unit 910, the second image processing controller unit 920, and the recording control controller unit 930 will be described in detail with reference to FIG. 3, the same reference numerals are given to the same components as the components (blocks) illustrated in FIG. 2, and the description of the components is omitted here.

  The main controller ASIC 1001 is an ASIC in which the CPU 901, the renderer processing unit 902, the scanner image processing unit 903, the host IF control unit 904, the scanner IF control unit 905, and the inter-ASIC IF control unit 906 shown in FIG. A ROM 907 and a RAM 908 are connected to the main controller ASIC 1001, and the main controller ASIC 1001 controls various operations by reading an operation program stored in the ROM 907.

  The main controller ASIC 1001 includes a P01 terminal and a P02 terminal as programmable control terminals. The P01 terminal drives a P_PW_ON signal and the P02 terminal drives a P_RST_L signal (reset control signal). In addition, these signals are wired to the print engine unit 940.

  As other terminals, the main controller ASIC 1001 (more specifically, the inter-ASIC IF control unit 906) includes a TX terminal and an RX terminal as PCIe terminals. The signal SG_DW_1 output from the TX terminal of the main controller ASIC 1001 is connected to the RX1 terminal of the first image processing controller ASIC 1011. The signal SG_UP_1 output from the TX1 terminal of the first image processing controller ASIC 1011 is connected to the RX terminal of the main controller ASIC 1001.

  As a supplement, the PCIe TX signal and RX signal are standardized as differential signals. For each ASIC shown in FIG. 3, the positive polarity signal TX_P and the negative polarity signal TX_N that is an inverted signal thereof are similarly RX_P and RX_N. Are combined to form a differential signal. In the following description, the notation as a differential signal is omitted in order to simplify the notation.

  The first image processing controller ASIC 1011 is an ASIC in which the CPU 911, the image processing unit 912, the inter-ASIC IF control unit 913, and the inter-ASIC IF control unit 914 shown in FIG. A ROM 917 and a RAM 918 are connected to the first image processing controller ASIC 1011, and the first image processing controller ASIC 1011 controls various operations by reading an operation program stored in the ROM 917.

  In the first image processing controller, the inter-ASIC IF control unit 913 includes the TX1 terminal and the RX1 terminal as the PCIe terminals, and the PCIe signal controlled by the inter-ASIC IF control unit 913 is a set of the TX signal and the RX signal. It has become. The connection with the main controller ASIC 1001 is as described above.

  The inter-ASIC IF control unit 914 includes a TX2 terminal and an RX2 terminal as PCIe terminals, and the PCIe signal controlled by the inter-ASIC IF control unit 914 is a set of a TX signal and an RX signal. The signal SG_DW_2 output from the TX2 terminal of the first image processing controller ASIC 1011 is connected to the RX1 terminal of the second image processing controller ASIC1021. A signal SG_UP_2 output from the TX1 terminal of the second image processing controller ASIC1021 is connected to the RX2 terminal of the first image processing controller ASIC1011.

  The second image processing controller ASIC 1021 is an ASIC in which the CPU 921, the image processing unit 922, the inter-ASIC IF control unit 923, and the inter-ASIC IF control unit 924 shown in FIG. A ROM 927 and a RAM 928 are connected to the second image processing controller ASIC 1021, and the second image processing controller ASIC 1021 controls various operations by reading an operation program stored in the ROM 927.

  The second image processing controller ASIC 1021 includes P20, P21, and P22 terminals as programmable control terminals. The P20 terminal drives the H_VH_ON signal, the P21 terminal drives the H_PW_ON signal, and the P22 terminal drives the H_RST_L signal. In addition, the H_VH_ON signal is connected to the FET 1043, the H_PW_ON signal is connected to the FET 1042, and the H_RST_L signal is connected to the open drain buffer 1033.

  As other terminals, the second image processing controller unit 920 (more specifically, the inter-ASIC IF control unit 923 and the inter-ASIC IF control unit 924) includes a PCIe terminal. In the second image processing controller, the inter-ASIC IF control unit 923 includes a TX1 terminal and an RX1 terminal as PCIe terminals, and the PCIe signal controlled by the inter-ASIC IF control unit 923 is a combination of the TX signal and the RX signal. Yes. The connection with the first image processing controller ASIC 1011 is as described above.

  The inter-ASIC IF control unit 924 includes a TX2 terminal and an RX2 terminal as PCIe terminals, and the PCIe signal controlled by the inter-ASIC IF control unit 924 is a set of a TX signal and an RX signal. A signal SG_DW_3 output from the TX2 terminal of the second image processing controller ASIC1021 is connected to the RX terminal of the recording control controller ASIC1031. The signal SG_UP_3 output from the TX terminal of the recording controller ASIC 1031 is connected to the RX2 terminal of the second image processing controller ASIC 1021.

  The recording control controller ASIC 1031 is an ASIC in which the HV processing unit 931, the inter-ASIC IF control unit 933, and the recording control unit 934 shown in FIG. A ROM 937 and a RAM 938 are connected to the recording controller ASIC 1031, and the recording controller ASIC 1031 controls various operations by reading an operation program stored in the ROM 937.

  In the recording controller ASIC 1031, the inter-ASIC IF control unit 933 includes a TX terminal and an RX terminal as PCIe terminals, and the PCIe signal controlled by the inter-ASIC IF control unit 933 is a set of the TX signal and the RX signal. . The connection with the second image processing controller ASIC 1011 is as described above. The recording controller ASIC 1031 outputs a recording signal to the recording head 8.

  Next, a power supply system that operates the first image processing controller ASIC 1011 and the second image processing controller ASIC 1021 and a reset signal system that controls the initialization operation will be described.

  The power supply unit 1051 supplies power supplied from a commercial power supply (not shown) as an operation power supply for the recording apparatus 1. Specifically, as shown in FIG. 3, the power supply unit 1051 supplies power by three systems of power supplies VC, VM, and VH.

  The power source VC is an all-night power source and is output while power is supplied from a commercial power source. The power supply VC is used as an operation power supply for the main controller ASIC 1001. The main controller ASIC 1001 operates in an energized state in all the operation modes of the recording apparatus 1, and resets to release the power supply state and the power supply cutoff state of the print engine unit 940 when shifting to the power saving mode and returning from the power saving mode To control.

  The power VM is supplied to the print engine unit, and the power VH is supplied to the recording head 8. Regarding the power supply VM, the power supply VM_SW is supplied to the first image processing controller and the second image processing controller, and the power supply VM_SW1 is supplied to the recording control controller.

  Hereinafter, first, a description will be supplemented regarding the power supply VM_SW. The main controller ASIC 1001 controls on / off of the power supply VM_SW supplied to the first and second image processing controllers by switching the FET 1041 with the P_PW_ON signal. Specifically, the main controller ASIC 1001 turns on the power supply VM_SW by controlling the P_PW_ON signal to High level, and turns off the power supply VM_SW by controlling it to Low level.

  The first power supply unit 1012 converts the supplied power VM_SW into the first image processing controller ASIC 1011, ROM 917, RAM 918, open drain buffer 1013, and other power supply VDD1 for electric circuits related to these not shown. The first power supply unit 1012 has a reset terminal RST1_O_L. After the VDD1 power supply voltage exceeds a predetermined threshold, a time constant period determined by a passive component such as a resistor or a capacitor (not shown) elapses. , A reset signal that becomes a low level is output. When reset is released, low level driving is stopped and a high impedance state is entered.

  The open drain buffer 1013 outputs the P_RST_L signal input from the P02 terminal of the main controller ASIC 1001 to the reset terminal RST_L of the first image processing controller ASIC 1011 as the RST1_L signal.

  Note that the RST1_L signal is connected to the reset terminal RST1_O_L of the first power supply unit 1012 described above, and is further connected to VDD1 via a pull-up resistor (not shown).

  With such a configuration, the RST1_L signal is a logical product (AND) of the P_RST_L signal and the signal output from the RST1_O_L terminal. That is, when either the P_RST_L signal or the signal output from the RST1_O_L terminal is at the low level, the RST1_L signal is at the low level. Further, when the P_RST_L signal is at a high level and the signal output from the RST1_O_L terminal is in a high impedance state, the RST1_L signal is at a high level by the pull-up resistor described above. In the meantime, when both the P_RST_L signal and the signal output from the RST1_O_L terminal do not drive the Low level, the configuration of the logical product functions as a reset release signal output means, and the reset release signal is output.

  The second power supply unit 1022 converts the supplied power VM_SW into the second image processing controller ASIC 1021, ROM 927, RAM 928, open drain buffer 1023, and other operation circuit power supply VDD2 (not shown). The second power supply unit 1022 has a reset terminal RST2_O_L. After the VDD2 power supply voltage exceeds a predetermined threshold, a time constant period determined by a passive component such as a resistor or a capacitor (not shown) elapses. , A reset signal that becomes a low level is output. When reset is released, low level driving is stopped and a high impedance state is entered.

  The open drain buffer 1023 outputs the P_RST_L signal input from the P02 terminal of the main controller ASIC 1001 to the reset terminal RST_L of the second image processing controller ASIC 1021 as the RST2_L signal.

  Note that the RST2_L signal is connected to the reset terminal RST2_O_L of the second power supply unit 1022 described above, and is further connected to VDD2 via a pull-up resistor (not shown).

  With such a configuration, the RST2_L signal is a logical product (AND) of the P_RST_L signal and the signal output from the RST2_O_L terminal. That is, when either the P_RST_L signal or the signal output from the RST2_O_L terminal is at the low level, the RST2_L signal is at the low level. Further, when both the P_RST_L signal and the signal output from the RST2_O_L terminal do not drive the low level, the signal is set to the high level by the pull-up resistor described above.

  Since the RST1_L signal and the RST2_L signal are configured as described above, the main controller ASIC 1001 simultaneously resets both of the two image processing controllers ASIC in the event of any error state. be able to. That is, the main controller ASIC 1001 can stop the operations of the first image processing controller unit 910 and the second image processing controller unit 920 by driving the P_RST_L signal of the P02 terminal to the low level.

  Further, when the main controller ASIC 1001 shifts the recording apparatus 1 to the power saving mode or the power-off state, the main controller ASIC 1001 instructs the print engine unit 940 to end processing, and receives the notification that preparation for completion is completed, uses the P_RST_L signal. To reset. After the first image processing controller ASIC 1011 and the second image processing controller ASIC 1021 are in the reset state, the power supply VM_SW is shut off using the P_PW_ON signal. In this way, by turning off the power supply after the reset state, it is possible to prevent an abnormal state from occurring even in a transient state where the power supply is lowered.

  Next, a supplementary explanation will be given regarding the power source VM_SW_1. The second image processing controller ASIC 1021 controls on / off of the power supply VM_SW_1 supplied to the inside of the recording control controller by performing switching control of the FET 1042 with the H_PW_ON signal. Specifically, the second image processing controller ASIC 1021 turns on the power supply VM_SW_1 by controlling the H_PW_ON signal to a high level and turns off the power supply VM_SW_1 by controlling it to a low level.

  The third power supply unit 1032 converts the supplied power VM_SW_1 into a recording controller ASIC 1031, a ROM 937, a RAM 938, an open drain buffer 1033, and other power supply VDD3 for operating electric circuits related to these not shown. The third power supply unit 1032 has a reset terminal RST3_O_L and outputs a reset signal until a predetermined condition is satisfied. Specifically, for example, after the VDD3 power supply voltage exceeds a predetermined threshold value, a reset signal that goes to a low level is output until a time constant period determined by a passive component such as a resistor or a capacitor (not shown) elapses. To do. When reset is released, low level driving is stopped and a high impedance state is entered.

  The open drain buffer 1033 outputs the H_RST_L signal input from the P22 terminal of the second image processing controller ASIC 1021 to the reset terminal RST_L of the recording controller ASIC 1031 as the RST3_L signal.

  Note that the RST3_L signal is connected to the reset terminal RST3_O_L of the third power supply unit 1032 described above, and is further connected to VDD3 via a pull-up resistor (not shown).

  With such a configuration, the RST3_L signal is a logical product (AND) of the signal output from the H_RST_L signal and the RST3_O_L terminal. That is, when either the H_RST_L signal or the signal output from the RST3_O_L terminal is at the low level, the RST3_L signal is at the low level. Further, when both the H_RST_L signal and the signal output from the RST3_O_L terminal do not drive the low level, the high level is set by the above-described pull-up resistor.

  Note that the configuration of the RST3_L signal as described above allows the second image processing controller ASIC 1021 to reset the recording control controller ASIC 1031 when the error occurs. That is, the second image processing controller ASIC 1021 can stop the operation of the recording control controller unit 930 by driving the H_RST_L signal of the P22 terminal to the Low level.

  The power supply VH is supplied to the recording head 8 as the power supply VH_SW. Hereinafter, a supplementary explanation will be given regarding the power supply VH_SW. The second image processing controller ASIC 1021 controls the on / off of the power supply VH_SW supplied to the inside of the recording head 8 by performing switching control of the FET 1043 with the H_VH_ON signal output from the P20 terminal. Specifically, the second image processing controller unit 920 turns on the power supply VH_SW by controlling the H_VH_ON signal to a high level and turns off the power supply VH_SW by controlling it to a low level.

  In addition, the description of the open drain buffer is supplemented. In the first power supply unit 1012 or the second power supply unit 1022, when a state such as a temporary decrease in power supply voltage occurs, the reset signal (RST1_L signal or RST2_L signal) is driven to a low level. When the reset signal is driven to a low level, the image processing controller ASIC is reset. On the other hand, since the open drain buffers 1013 and 1023 are incorporated as reset configurations, the state of the reset signal driven by the power supply unit does not propagate to the other image processing controller ASIC. That is, in this case, only the image processing controller ASIC in which some abnormality has occurred in the power supply is reset, and the image processing controller ASIC in the normal power supply state can continue the operation. In addition, the image processing controller ASIC that can continue operation in a normal power supply state can execute appropriate error processing such as acquiring an error log when a power supply abnormality occurs in the other controller ASIC.

  FIG. 4 is a flowchart illustrating a processing procedure when the controller unit 900, the first image processing controller unit 910, the second image processing controller unit 920, and the recording control controller unit 930 are activated. Hereinafter, the processing procedure will be described in detail.

  The main controller ASIC 1001 of the controller unit 900 starts activation when the power of the recording apparatus 1 is turned on, reads a program from the ROM 907, and executes initialization processing (S401).

  Next, the main controller ASIC 1001 switches the output level of the signal (P_PW_ON signal) output from the P01 terminal from the Low level to the High level, and controls to turn on a part of the power supply of the print engine unit 940 (S402).

  That is, the main controller ASIC 1001 performs switching control of the FET 1041 by the P_PW_ON signal, and supplies the power VM to the first image processing controller unit 910 and the second image processing controller unit 920 as the power VM_SW.

  When the power VM_SW is supplied to the first image processing controller unit 910, the first power supply unit 1012 supplies the power VDD1 to the first image processing controller ASIC 1011 (S403). That is, the power supply of the first image processing controller ASIC 1011 is turned on (S403). Similarly, when the power VM_SW is supplied to the second image processing controller unit 920, the second power supply unit 1022 supplies the power VDD2 to the second image processing controller ASIC 1021 (S404). Further, when the power supply VDD2 is supplied to the second image processing controller ASIC 1021, the second image processing controller ASIC 1021 performs switching control of the FET 1042. As a result, the power supply VM_SW_1 is supplied to the recording control controller unit 930, and the third power supply unit 1032 supplies the power supply VDD3 to the recording control controller ASIC 1031 (S405).

  When each of the main controllers ASIC 1001 supplies power, the main controller ASIC 1001 switches the output level of the signal (P_RST_L) output from the P02 terminal from the low level to the high level, and executes a reset release process for each controller (S406).

  As described above, the P_RST_L signal is input to the RST_L terminal of the first image processing controller ASIC 1011 as a logical product (AND) with the signal output from the reset terminal RST1_O_L of the first power supply unit 1012. Therefore, when the signal output from the RST1_O_L is in a high impedance state with the P_RST_L signal switched to the high level, the high level signal is input to the RST_L terminal. That is, in this case, the first image processing controller ASIC 1011 cancels the reset. Further, regarding the reset release, the second image processing controller ASIC 1021 and the recording control controller ASIC 1031 perform the same processing. However, the reset control signal (H_RST_L) input to the recording controller ASIC 1031 when the reset of the recording controller ASIC 1031 is canceled is controlled by the second image processing controller ASIC 1021.

  When the reset is released, each controller sequentially executes a boot process (S407), a main firmware load process (S408), an OS activation, and a parent task activation (S409) independently of the other controllers. Thereafter, each controller executes initialization processing of peripheral power sources (for example, a head power source and a motor driver power source not shown) connected to the controller (S410). Here, the parent task is a task required for enabling communication with another controller.

  When the main controller ASIC 1001 executes the initialization process of the controller (S411), the main controller ASIC 1001 executes a process related to link establishment of PCIe (here, referred to as PCIe1) which is a communication path with the first image processing controller ASIC 1011 (S41). In this case, the master-slave relationship is established in PCIe1, the main controller ASIC 1001 is set as RC (main), and the first image processing controller ASIC 1011 is set as EP (slave).

  Further, regarding link establishment, the inter-ASIC IF control unit 906 executes communication negotiation by link training for exchanging communication conditions operating at the hardware level with the opposing chip.

  Specifically, the inter-ASIC IF control unit 906 first transmits a negotiation condition to the first image processing controller ASIC 1011 using the SG_DW_1 signal. Next, the inter-ASIC IF control unit 906 receives the negotiation condition from the first image processing controller ASIC 1011 using the SG_UP_1 signal. Then, the inter-ASIC IF control unit 906 issues an interrupt signal when the negotiation condition matches and the connection is completed. Further, when the CPU 901 of the main controller ASIC 1001 receives this interrupt signal, the link establishment of PCIe1 is completed (S414 Yes).

  In addition, regarding the PCIe1 connection, it is determined whether or not the time taken to complete the connection is within a predetermined time set in advance. If the connection is not completed, a timeout occurs and it is determined that there is a connection error (No in S414). .

  When the link establishment of PCIe1 is completed, the main controller ASIC 1001 executes various initialization processes of PCIe1. For example, initial setting for arranging the opposing ASIC in the memory map is performed.

  Next, the description will be supplemented from the processing related to the link establishment of PCIe in the first image processing controller ASIC 1011 which is the EP side of PCIe1. When the first image processing controller ASIC 1011 executes the initialization processing of the peripheral power supply, it executes communication negotiation with the inter-ASIC IF control unit 906 of the main controller ASIC 1001, thereby executing processing related to the link establishment of PCIe1 (S414).

  As shown in FIG. 4, the first image processing controller ASIC 1011 performs processing related to link establishment of PCIe (here, referred to as PCIe 2) that is a communication path with the second image processing controller ASIC 1021 before S 414. Execute (S413). However, regarding (S413) and (S414), the processing order is not questioned. The first image processing controller ASIC 1011 executes configuration setting processing when a link is established for PCIe1 and PCIe2 (S417).

  Note that the link establishment process in the communication path (here, referred to as PCIe 3) between the second image processing controller ASIC 1021 and the recording control controller ASIC 1031 is executed in the same manner (S412). Further, after the link establishment process, the configuration setting process is similarly executed (S416).

  Next, the recording controller ASIC 1031 validates the PCIe3 communication enable flag (S418). Specifically, when a link is established for PCIe3 (S412) and the configuration setting process is executed (S415), the recording controller ASIC 1031 can read and write a partial memory of the second image processing controller. The recording controller ASIC 1031 writes a PCIe3 communicable flag to the second image processing controller ASIC using this readable / writable memory. As a result, it is proved that the inter-chip communication via the PCIe 3 is possible (that is, the PCIe 3 communicable flag is validated).

  When the PCIe 3 communicable flag is written, the recording controller ASIC 1031 starts a child task (that is, a task other than the parent task that can be executed even after communication (communication flag) is enabled) ( S419). When the recording control controller ASIC 1031 starts the child task, the recording control controller ASIC 1031 waits for synchronization of information regarding all controllers to be started.

  When the PCIe3 communicable flag is written in the second image processing controller ASIC 1021 within a predetermined time (Yes in S420), the second image processing controller ASIC 1021 validates the PCIe2 communicable flag in the same manner as PCIe3 (S421). Then, when the PCIe2 communicable flag is validated, the second image processing controller ASIC 1021 activates a child task (S422), and waits for synchronization of information regarding all controllers to be started. If the PCIe3 communicable flag is not written within the predetermined time (No in S420), the second image processing controller ASIC 1021 determines that a timeout has occurred (ie, an error).

  Similarly, in the first image processing controller ASIC 1011, the PCIe1 communicable flag is validated (S424), and then the child task is activated (S425) to start synchronization of information on all the controllers. stand by.

  When the main controller ASIC 1001 executes processing related to the link establishment of PCIe1 (S414), the first controller ASIC 1011 determines whether or not the PCIe1 communicable flag is written within a predetermined time (S426). That is, it is determined whether or not the communicable flag is written in all PCIe within a predetermined time.

  When the communicable flag is written in all PCIe (when a part of the memory information can be read and written in each controller), the main controller ASIC 1001 executes synchronization of the firmware version information (S427).

  As described above, the sub-controller (that is, the first and second image processing controllers ASIC and the recording control controller ASIC) can immediately start the child task when the PCIe communication enable flag is validated. Therefore, in the recording apparatus 1, for example, the activation of the child task in the first image processing controller ASIC 1011 and the process of confirming (determining) the validity of the PCIe1 communicable flag in the main controller ASIC 1001 can be executed in parallel. Thereby, in the recording apparatus 1, time until it can be used (namely, starting time) can be shortened as a whole.

  Further, in this embodiment, a communicable flag is written from the downstream side to the upstream side memory, the upstream controller confirms the communicable flag, and this is repeated, so that the main controller ASIC 1001 can communicate between chips. It was confirmed that However, the method for confirming that the main controller ASIC 1001 can communicate between chips is not necessarily limited to this. Therefore, it is confirmed that the main controller ASIC 1001 can perform communication between chips by mounting a memory that can be written from each of all the controller ASICs and stores a communication enable flag for each communication path. May be. Specifically, when a link related to communication with another controller is established, each controller ASIC validates the flag of the communication path established with the link, and the main controller ASIC 1001 confirms that all communication enable flags are validated. Confirm whether or not. The memory storing the communicable flag corresponds to the flag storage unit.

  Next, the main controller ASIC 1001 determines whether the firmware version information is inconsistent (S428). If the main controller ASIC 1001 determines that the firmware version information is consistent (S428 Yes), the main controller ASIC 1001 executes activation factor, time setting, and operation model information synchronization for each controller (S429).

  Here, the activation factor indicates a factor such as normal activation by power-on including the main controller ASIC 1001 or return (activation) from the power saving state except for the main controller ASIC 1001. The time setting indicates the time setting managed by the main controller ASIC 1001, and the operation model information indicates information regarding functions that are enabled / disabled due to the presence / absence of connection of an optional device and the hardware configuration.

  When there is inconsistency (that is, when the firmware version information of each controller is different from the combination of versions incorporated in the program in advance) (S428: No), the main controller ASIC 1001 determines that there is an inconsistency error and starts the process. Interrupt. As described above, when the main controller ASIC 1001 becomes in a communicable state, the firmware information written in the ROM connected to each controller is assumed to be a combination by checking the consistency of the firmware version information. Determine whether.

  When the main controller ASIC 1001 synchronizes the activation factor, time setting, and behavior model information for each controller, the main controller ASIC 1001 synchronizes information necessary for user interface (hereinafter, UI) display in the recording apparatus 1 to each controller. (S430). Here, the information necessary for UI display is, for example, information related to the remaining amount of ink, paper, and the like.

  Next, the main controller ASIC 1001 instructs the print engine unit 940 to perform mechanical initialization (S431). Further, when each controller of the print engine unit 940 receives an instruction regarding mechanical initialization from the main controller ASIC 1001, the controller executes necessary mechanical initialization processing based on the above-described activation factor and operation model information (S432).

  Thus, by completing the process up to mechanical initialization, the recording apparatus 1 is ready for printing (that is, by executing the process according to the procedure of the flowchart shown in FIG. , The printer is ready to print).

  As described above, the ROM is connected to each of the first image processing controller ASIC 1011 and the second image processing controller ASIC 1021, and it is not necessary to start up and initialize after transferring the operation program. Startup processing is possible. That is, since boot processing, main firmware loading processing, OS activation, and the like can be performed in parallel, it can be activated at a higher speed. For this reason, the print engine unit 940 can shorten the time until the printer engine 940 recovers from the power-off state or the power saving state while reducing the power consumption.

  In addition, as described above, the task is divided into a task (parent task) required to activate communication and a task other than that (child task) to activate the recording device, and the parent task has priority. As a result, the entire recording apparatus can be activated at high speed.

  Furthermore, since it is possible to start in the reset period determined by the hardware operation (because it can be started by hardware control), no software wait is required, and it is possible to start with an optimal start time.

  In addition, the main controller ASIC 1001, the first image processing controller ASIC 1011 and the second image processing controller ASIC 1021 are separate power sources and can be individually controlled as described above. That is, the power supply to the first power processing unit 910 and the second image processing controller unit 920 can be individually controlled by adopting a configuration capable of individually controlling the power supplied to the first power supply unit 1012 and the second power supply unit 1022. can do. Specifically, an FET is incorporated in the previous stage of the second power supply unit 1022, and switching control (control of power supply) in the FET is performed by either the main controller ASIC 1001 or the first image processing controller ASIC. Can be controlled.

(Other embodiments)
In the above-described embodiment, the configuration in which two image processing controllers are mounted has been described. However, in the present embodiment, a configuration in which one image processing controller is mounted is used. The specific processing is the same as the processing performed by the main controller ASIC 1001 and the first image processing controller ASIC 1011 in the above-described embodiment.

  Therefore, even in the case of a single image processing controller, it is not necessary to start up after transferring the operation program of the image processing controller ASIC at the time of start-up, as in the above-described embodiment. Is possible. That is, since boot processing, main firmware loading processing, OS activation, and the like can be performed in parallel, it can be activated at a higher speed.

  In addition, as described above, the task is divided into a task (parent task) required to activate communication and a task other than that (child task) to activate the recording device, and the parent task has priority. As a result, the entire recording apparatus can be activated at high speed.

  Furthermore, since it is possible to start in the reset period determined by the hardware operation (because it can be started by hardware control), no software wait is required, and it is possible to start with an optimal start time. In addition, the manufacturing cost can be reduced by configuring a single image processing controller to be mounted.

  In addition, in the above description, the case where the number of image processing controllers ASIC is two and one has been described as an example, but the number of image processing controllers ASIC is not necessarily limited thereto, and may be three or more. Further, as the number of image processing controllers ASIC increases, the startup time can be further shortened.

  In the above-described embodiment, the ASIC connected to the main controller ASIC has been described as the image processing controller ASIC. However, the image processing controller ASIC is not necessarily required (that is, the function of image processing is not essential). Therefore, the same effect can be obtained even if other functions such as a mechatronics controller ASIC that performs motor control are used. That is, in the above-described embodiment, the recording apparatus has been described as an example. However, the present invention can be applied to any device (electronic device) having at least the above-described power supply control configuration and reset control configuration.

  The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized.

900 Controller unit 910 First image processing controller unit 920 Second image processing controller unit

Claims (12)

An electronic device comprising a sub-unit having a sub-controller, and a main unit having a main controller connected to the sub-controller by a predetermined communication method and controlling the sub-controller,
The main controller determines whether communication between the main controller and the sub-controller is enabled,
The sub-controller
A program that is connected to the sub-controller and includes a parent task required for enabling communication between the main controller and the sub-controller and a child task required for starting the electronic device other than the parent task And further storing means for storing
When the power-off state in the sub-controller is released, the parent task is executed in preference to the child task,
An electronic apparatus, wherein the child task is executed in parallel with a process of determining whether the communication in the main controller is enabled.   The electronic apparatus according to claim 1, wherein when determining that the communication is enabled, the main controller performs synchronization of firmware version information with the sub-controller.   The electronic device according to claim 2, wherein when the main controller determines that the firmware version information of the sub-controller is not consistent, the electronic device interrupts activation of the electronic device.   3. The electronic apparatus according to claim 2, wherein when the main controller determines that the firmware version information of the sub-controller is consistent, the electronic apparatus performs synchronization of information necessary for displaying a user interface. . The subunit includes first and second subunits;
The first subunit has a first sub-controller;
The second subunit has a second sub-controller;
The main controller, the first sub-controller, and the second sub-controller are connected in cascade with each other by the predetermined communication method,
The second sub controller writes the first communicable flag to the memory of the first sub controller, so that the first sub controller, the second sub controller, Informing you that your communication has been activated,
When the first sub-controller determines that communication with the second sub-controller has been enabled, the first sub-controller writes a second communicable flag in the memory of the main controller, so that the main controller 5. The electronic apparatus according to claim 1, wherein communication between the first sub controller and the first sub controller is notified. The subunit includes first and second subunits;
The first subunit has a first sub-controller;
The second subunit has a second sub-controller;
The main controller, the first sub-controller, and the second sub-controller are connected in cascade with each other by the predetermined communication method,
A flag indicating that communication between the main controller and the first sub-controller is enabled; a flag indicating that communication between the first sub-controller and the second sub-controller is enabled; A flag storage means for storing each communication path;
When a link related to communication between the main controller and the first sub-controller and a link related to communication between the first sub-controller and the second sub-controller are established, the link is established in the flag storage means. The electronic device according to any one of claims 1 to 4, wherein the flag of the communication channel is validated.   The electronic device according to claim 1, wherein the predetermined communication method is a serial communication method.   The electronic device according to claim 7, wherein the serial communication method is a communication method conforming to a PCI Express standard (registered trademark).   The electronic device according to claim 1, wherein the child task is a task that can be executed even after the communication is validated.   The electronic apparatus according to claim 1, wherein the electronic apparatus is a recording apparatus that records an image by driving a recording head.   The program for functioning a computer as each means of the electronic device of any one of Claim 1 to 10. A main unit having a main controller for controlling the sub-controller;
The sub-controller and a child connected to the sub-controller and required to activate communication between the main controller and the sub-controller and an electronic device other than the parent task A control method of an electronic device comprising a subunit having storage means storing a program including a task,
When the sub-controller releases the power-off state in the sub-controller, a first execution step of executing the parent task with priority over the child task;
A determination step of determining whether communication between the main controller and the sub-controller is enabled by the main controller;
And a second execution step of executing the child task in parallel with the determination step by the sub-controller.

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