JP2019021871A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

To make it difficult to generate leakage current while achieving downsizing of a semiconductor device.SOLUTION: A semiconductor device comprises: a semiconductor substrate 10 having a drift layer 12, a channel layer 13 formed on the drift layer 12, a first impurity region 15 formed in a surface layer part of the channel layer 13 and a second impurity region 11 formed opposite to the channel layer 13 across the drift layer 12; a trench gate structure where a gate electrode 18 is arranged in a trench 16 via an insulation film 17; and a gate liner 19 electrically connected to the gate electrode 18. The gate liner 19 extends in a direction crossing a longer direction of the trench 16 when viewed from a normal direction with respect to a planar direction of the semiconductor substrate 10 in a state of crossing the trench 16; the channel layer 13 is formed in a region different from a region located below the gate liner 19; and a resurf layer 14 leading to the channel layer 13 is formed in a region located on the drift layer 12 and below the gate liner 19.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device having a trench gate structure and a manufacturing method thereof.

Conventionally, there has been proposed a semiconductor device in which a MOSFET (that is, metal oxide semiconductor field effect transistor) element having a trench gate structure is formed (see, for example, Patent Document 1). Specifically, this semiconductor device is configured using a semiconductor substrate in which a P-type channel layer is formed on an N ⁻ -type drift layer and an N ⁺ -type source layer is formed on the surface layer portion of the channel layer. ing. In the semiconductor substrate, a plurality of trenches are formed from one side so as to penetrate the source layer and the channel layer. Each trench is filled with a gate insulating film formed on the wall surface and a gate electrode formed on the gate insulating film. A gate liner electrically connected to the gate electrode is formed on one surface of the semiconductor substrate at a portion different from the portion where the trench is formed. In other words, the gate liner is formed on one surface of the semiconductor substrate so as not to cross the trench.

  Furthermore, a first electrode that is electrically connected to the source layer and the channel layer is disposed on one surface of the semiconductor substrate. A second electrode that is electrically connected to the drain layer is disposed on the other surface opposite to the one surface of the semiconductor substrate.

  Such a semiconductor device is manufactured as follows. That is, first, a trench is formed in a semiconductor substrate, and a gate insulating film is formed on the wall surface of the trench by thermal oxidation or the like. Next, a poly-Si film is formed by CVD (ie, chemical vapor deposition) or the like so as to fill the trench, thereby forming a gate electrode. Subsequently, Poly-Si formed on the semiconductor substrate is patterned to form a gate liner. Then, a channel layer and a source layer are formed by ion implantation of P-type impurities and N-type impurities and heat treatment. Thereafter, the semiconductor device is manufactured by appropriately forming the first electrode, the second electrode, and the like.

JP 2017-45827 A

  In recent years, it has been desired to reduce the size of semiconductor devices. For this reason, the present inventors have studied to reduce the size of the semiconductor device by forming the gate liner so as to intersect the trench. However, when a semiconductor device having a gate liner intersecting with a trench is manufactured by the above manufacturing method, a channel layer is formed by ion implantation of impurities after the gate liner is formed. A channel layer is not formed in the region below the liner. That is, the drift layer directly reaches one surface of the semiconductor substrate below the gate liner. For this reason, when a semiconductor device is manufactured by the manufacturing method as described above, a high electric field is easily concentrated in a region below the gate liner, and a leak current is likely to be generated.

  The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device and a method for manufacturing the same that can make it difficult to generate a leakage current while reducing the size of the semiconductor device.

  According to a first aspect of the present invention, there is provided a semiconductor device having a trench gate structure, the first conductivity type drift layer (12) and a second conductivity type channel layer (on the drift layer) 13), a first impurity region (15) of the first conductivity type formed in the surface layer portion of the channel layer, and formed on the opposite side of the channel layer across the drift layer, and having a higher impurity concentration than the drift layer. A semiconductor substrate (10) having a second impurity region (11) of the first conductivity type or the second conductivity type, and the first impurity region and the channel layer to reach the drift layer, and a predetermined direction is a longitudinal direction. A trench gate structure in which a gate electrode (18) to which a predetermined gate voltage is applied via a gate insulating film (17) is disposed in a trench (16) is formed on a semiconductor substrate. In A gate liner (19) connected to the semiconductor substrate, the gate liner extending in a direction intersecting with the longitudinal direction of the trench when viewed from the normal direction to the surface direction of the semiconductor substrate and intersecting the trench The channel layer is formed in a region different from the region located below the gate liner, and the first conductive layer connected to the channel layer is formed on the drift layer and below the gate liner. A mold RESURF layer (14) is formed.

  According to this, the gate liner is formed so as to intersect the trench when viewed from the normal direction to the surface direction of the semiconductor substrate. For this reason, the semiconductor device can be reduced in size as compared with the case where the gate liner is formed so as not to intersect the trench.

  A RESURF layer is formed below the gate liner. For this reason, compared with the case where the RESURF layer is not formed, it can suppress that the high electric field extended from the drain layer side reaches the area | region below a gate liner, and can suppress that a leak current generate | occur | produces.

  According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a trench gate structure, comprising: preparing a semiconductor substrate (10) having a first conductivity type drift layer (12); A trench gate structure is formed by forming a trench (16) having a longitudinal direction as a longitudinal direction and a gate electrode (18) to which a predetermined gate voltage is applied through a gate insulating film (17) in the trench. And forming a gate liner (19) electrically connected to the gate electrode on the semiconductor substrate; and after forming the gate liner, the impurity is ion-implanted and heat-treated to thereby form the gate layer on the drift layer. Forming a second conductivity type channel layer (13) and forming a first conductivity type first impurity region (15) in a surface layer portion of the channel layer; In forming the liner, when viewed from the normal direction to the surface direction of the semiconductor substrate, the gate liner is formed so as to extend in a direction intersecting with the longitudinal direction of the trench and intersect with the trench, thereby forming the trench. Before performing, the second conductivity type RESURF layer (14) is formed in the region below the gate liner, and the channel layer is formed by forming the channel layer connected to the RESURF layer. I have to.

  According to this, the RESURF layer is formed before the gate liner is formed. For this reason, the semiconductor device in which the RESURF layer is formed below the gate liner can be manufactured.

  In addition, the code | symbol in the bracket | parenthesis in the said and the claim shows the correspondence of the term described in the claim, and the concrete thing etc. which illustrate the said term described in embodiment mentioned later. .

It is a plane layout view of a semiconductor device. It is sectional drawing along the II-II line | wire in FIG. It is sectional drawing along the III-III line in FIG. It is sectional drawing along the IV-IV line in FIG. FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 2. FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG. 3. FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 4. It is sectional drawing of the semiconductor device in 2nd Embodiment. It is sectional drawing of the semiconductor device different from FIG. 8 in 2nd Embodiment. It is a plane layout figure of the semiconductor device in a 2nd embodiment. FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 9. It is a plane layout figure of the semiconductor device in a 3rd embodiment. It is a plane layout figure of the semiconductor device in a 4th embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described. First, the configuration of the semiconductor device of this embodiment will be described. As shown in FIG. 1, the semiconductor device of the present embodiment has a cell region 1 and an outer peripheral region 2 surrounding the cell region. The cell region 1 has a main region 1a and a connection region 1b. FIG. 1 is a plan layout view showing the positional relationship between a gate electrode 18, a gate liner 19 and a RESURF layer 14 which will be described later, and is not a cross-sectional view. 19 is hatched. Further, the cell region 1 of the present embodiment is a portion in which a gate electrode 18 to be described later is disposed, and functions mainly as an element for flowing current. The connection region 1b is a region in the cell region 1 where a later-described gate liner 19 is disposed, and the main region 1a is a region different from the connection region 1b in the cell region 1.

2 to 4, the semiconductor device includes an N ⁺ type drain layer 11 and an N ⁻ type drift formed on the surface of the drain layer 11 and having an impurity concentration lower than that of the drain layer 11. A semiconductor substrate 10 having a layer 12 is included. The drain layer 11 is composed of an N ⁺ type silicon substrate having a high impurity concentration. In the present embodiment, the drain layer 11 corresponds to the second impurity region.

  On the drift layer 12 (that is, on the side of the one surface 10a of the semiconductor substrate 10), as shown in FIGS. 2 and 4, in the main region 1a, a P-type channel layer 13 having a relatively low impurity concentration is formed. Is formed. Further, as shown in FIGS. 3 and 4, a P-type RESURF layer 14 having an impurity concentration substantially equal to that of the channel layer 13 is formed on the drift layer 12 in the connection region 1 b. In the present embodiment, the RESURF layer 14 is formed to substantially the same depth as the channel layer 13. The RESURF layer 14 is formed along the extending direction of the gate liner 19 described later, and is formed in the entire region below the gate liner 19. That is, the RESURF layer 14 is formed such that a gate liner 19 described later is positioned in the RESURF layer 14 when viewed from the normal direction to the one surface 10 a of the semiconductor substrate 10 (that is, the normal direction to the surface direction). ing.

As shown in FIGS. 2 and 4, an N ⁺ type source layer 15 having a higher impurity concentration than the drift layer 12 is formed on the channel layer 13. That is, in the main region 1a, the channel layer 13 and the source layer 15 are formed on the drift layer 12 in this order from the drift layer 12 side. In the present embodiment, the source layer 15 corresponds to the first impurity region.

  Further, as shown in FIGS. 2 and 3, a plurality of trenches 16 reaching the drift layer 12 from the one surface 10 a side are formed in the semiconductor substrate 10. In the present embodiment, the plurality of trenches 16 are formed in stripes at regular intervals along a predetermined direction of the surface direction of the one surface 10a of the semiconductor substrate 10, and are formed in the main region 1a and the connection region 1b.

  Specifically, the trench 16 is formed to penetrate the source layer 15 and the channel layer 13 to reach the drift layer 12 in the main region 1a, and to penetrate the resurf layer 14 in the connection region 1b. Is formed to reach.

  Each trench 16 is embedded with a gate insulating film 17 formed so as to cover the wall surface of each trench 16 and a gate electrode 18 formed on the gate insulating film 17. Thereby, a trench gate structure is configured. In the present embodiment, the gate insulating film 17 is made of an oxide film or the like, and the gate electrode 18 is made of Poly-Si or the like.

  In the connection region 1b, as shown in FIGS. 1, 3, and 4, a gate liner 19 made of Poly-Si or the like is formed on one surface 10a of the semiconductor substrate 10. Specifically, the gate liner 19 extends in a direction intersecting with the extending direction of the trench 16 (that is, the gate electrode 18) when viewed from the normal direction to the one surface 10a of the semiconductor substrate 10. It is formed so as to intersect with each trench 16. The gate liner 19 is electrically connected to each gate electrode 18 on the opening of each trench 16.

  In the present embodiment, the gate liner 19 is formed so as to be positioned in the RESURF layer 14 when viewed from the normal direction to the one surface 10 a of the semiconductor substrate 10. In other words, the RESURF layer 14 is formed in the entire region below the gate liner 19.

  Further, as shown in FIGS. 2 to 4, an interlayer insulating film 20 made of an oxide film or the like is formed on one surface 10 a of the semiconductor substrate 10 so as to cover the gate electrode 18 and the gate liner 19. Yes. In the interlayer insulating film 20, a first contact hole 21 exposing the source layer 15 and the channel layer 13 is formed in the main region 1a. In the interlayer insulating film 20, a second contact hole 22 exposing the gate liner 19 is formed in the connection region 1b.

  Specifically, a plurality of first contact holes 21 are formed, and are formed so as to penetrate the source layer 15 and reach the channel layer 13 between the adjacent trenches 16. Thereby, the source layer 15 is exposed from the side surface of the first contact hole 21, and the channel layer 13 is exposed from the side surface and bottom surface of the first contact hole 21.

  A plurality of second contact holes 22 are formed so as to expose the gate liner 19. The second contact hole 22 only needs to have a configuration in which at least a part of the gate liner 19 is exposed. That is, a plurality of second contact holes 22 may be formed, or only one may be formed, for example.

  A source electrode layer 23 that is electrically connected to the source layer 15 and the channel layer 13 through the first contact hole 21 is formed on the interlayer insulating film 20. On the interlayer insulating film 20, a gate electrode layer 24 connected to the gate liner 19 through the second contact hole 22 and electrically connected to the gate electrode 18 through the gate liner 19 is formed.

  In the present embodiment, the source electrode layer 23 is disposed on the interlayer insulating film 20 and electrically connected to the first embedded electrode portion 23 a embedded in the first contact hole 21. The first upper layer electrode portion 23b is configured. Similarly, the gate electrode layer 24 is disposed on the interlayer insulating film 20 and is electrically connected to the second embedded electrode portion 24a embedded in the second contact hole 22 and the second embedded electrode portion 24a. The second upper electrode portion 24b is included. In the present embodiment, the first and second embedded electrode portions 23a and 24a are made of W (that is, tungsten). That is, the first and second embedded electrode portions 23a and 24a are so-called W plugs. The first and second upper electrode portions 23b and 24b are made of Al (that is, aluminum) or the like.

  A drain electrode 25 electrically connected to the drain layer 11 is formed on the opposite side of the drift layer 12 with the drain layer 11 interposed therebetween. That is, the drain electrode 25 that is electrically connected to the drain layer 11 is formed on the other surface 10 b of the semiconductor substrate 10.

  Although not specifically shown, the outer peripheral region 2 is appropriately formed with a guard ring for improving a withstand voltage, an outer peripheral electrode electrically connected to the guard ring, and the like.

The above is the configuration of the semiconductor device in this embodiment. In this embodiment, N ⁺ type, N type, and N ⁻ type correspond to the first conductivity type, and P type and P ⁺ type correspond to the second conductivity type. Further, as described above, the semiconductor substrate 10 of this embodiment includes the drain layer 11, the drift layer 12, the channel layer 13, and the source layer 15.

  In such a semiconductor device, a P-type RESURF layer 14 is also formed below the gate liner 19 in the cell region 1. For this reason, compared with the case where the RESURF layer 14 is not formed under the gate liner 19, it can suppress that a high electric field concentrates under the gate liner 19. FIG. Accordingly, it is possible to suppress the occurrence of a leak current in a portion below the gate liner 19.

  Next, the manufacturing process of the semiconductor device will be described with reference to FIGS. 5 is a cross-sectional view corresponding to FIG. 2, FIG. 6 is a cross-sectional view corresponding to FIG. 3, and FIG. 7 is a cross-sectional view corresponding to FIG. Moreover, (a)-(d) of each figure has shown the state of the same process, respectively.

  First, as shown in FIG. 5A, FIG. 6A, and FIG. 7A, a semiconductor substrate 10 in which a drift layer 12 is stacked on a drain layer 11 is prepared. Here, an example of preparing the semiconductor substrate 10 in which the drift layer 12 is stacked on the drain layer 11 will be described. However, after performing the following steps, ion implantation and heat treatment are performed to perform other steps of the semiconductor substrate 10. The drain layer 11 may be formed on the surface 10b side.

  Next, as shown in FIGS. 6A and 7A, a mask (not shown) is arranged on one surface 10a of the semiconductor substrate 10, and P-type impurities are introduced into the lower region where the gate liner 19 is formed. The RESURF layer 14 is formed by ion implantation as appropriate and thermal diffusion. Thereafter, the mask is removed.

  Then, as shown in FIG. 5B, FIG. 6B, and FIG. 7B, a mask (not shown) is disposed, and the trench 16 is formed by performing dry etching or the like. Thereafter, thermal oxidation or the like is performed to form a gate insulating film 17 on the wall surface of the trench 16. In this step, an insulating film is also formed on one surface 10a of the semiconductor substrate 10.

  Subsequently, as shown in FIGS. 5C, 6C, and 7C, a poly-Si film is formed by CVD or the like so that each trench 16 is embedded. As a result, each trench 16 has a trench gate structure in which the gate electrode 18 is disposed via the gate insulating film 17. Then, a mask (not shown) is disposed and dry etching or the like is performed, and poly-Si formed on the one surface 10a of the semiconductor substrate 10 is appropriately patterned to form the gate liner 19. At this time, as described above, the gate liner 19 is formed so as to intersect with each trench 16 and to have the RESURF layer 14 located below when viewed from the normal direction to the one surface 10a of the semiconductor substrate 10. Is done. Thereafter, the mask is removed.

  In the step of forming the RESURF layer 14 and the step of forming the gate liner 19, the RESURF layer 14 is positioned so that the gate liner 19 is positioned in the RESURF layer 14 when viewed from the normal direction to the one surface 10 a of the semiconductor substrate 10. And the gate liner 19 is formed.

  Next, as shown in FIGS. 5D, 6D, and 7D, the channel layer 13 and the source layer are formed by ion implantation of P-type impurities and N-type impurities and thermal diffusion. 15 is formed. At this time, impurities are not implanted below the gate liner 19 using the gate liner 19 as a mask. However, in the present embodiment, the RESURF layer 14 is already formed below the gate liner 19. Therefore, in this step, the channel layer 13 is formed so that the channel layer 13 and the RESURF layer 14 are connected. As a result, the cell region 1 has a configuration in which the channel layer 13 or the RESURF layer 14 is formed on the drift layer 12.

  Thereafter, although not particularly shown, an interlayer insulating film 20 is formed by CVD or the like so as to cover the gate electrode 18 and the gate liner 19. Then, a photoresist or the like is disposed on the interlayer insulating film 20, and the first contact hole 21 and the second contact hole 22 are formed in the interlayer insulating film 20 using the photoresist as a mask.

  Subsequently, a source electrode layer 23 electrically connected to the channel layer 13 and the source layer 15 is formed, and a gate electrode layer 24 connected to the gate liner 19 is formed. When forming the source electrode layer 23 and the gate electrode layer 24, for example, first, W is buried in the first contact hole 21 and the second contact hole 22 by a CVD method or the like, and the first and second buried electrode portions. 23a and 24a are formed. Next, the W film stacked on the interlayer insulating film 20 is removed. Thereafter, a metal film such as Al is formed on the interlayer insulating film 20 by CVD or the like, and the formed metal film is patterned, whereby the first upper layer electrically connected to the first embedded electrode portion 23a. The electrode portion 23b is formed, and the second upper electrode portion 24b that is electrically connected to the second embedded electrode portion 24a is formed. As described above, the semiconductor device of this embodiment is manufactured.

  As described above, in this embodiment, the gate liner 19 is formed so as to intersect with the trench 16 when viewed from the normal direction to the one surface 10 a of the semiconductor substrate 10. For this reason, the semiconductor device can be reduced in size as compared with the case where the gate liner 19 is formed so as not to intersect the trench 16.

  A RESURF layer 14 is formed below the gate liner 19. For this reason, compared with the case where the RESURF layer 14 is not formed, it can suppress that the high electric field extended from the drain layer 11 side reaches the area | region under the gate liner 19, and can suppress that a leak current generate | occur | produces.

  Further, the gate liner 19 is formed so as to be positioned in the RESURF layer 14 when viewed from the normal direction to the one surface 10 a of the semiconductor substrate 10. That is, the cell region 1 is in a state where the channel layer 13 or the RESURF layer 14 is formed on the drift layer 12. For this reason, generation | occurrence | production of leak current can be suppressed further.

  The RESURF layer 14 is formed before the gate liner 19 is formed. Therefore, a semiconductor device in which the RESURF layer 14 is disposed below the gate liner 19 can be easily manufactured.

  The channel layer 13 and the source layer 15 are formed after forming the trench gate structure. For this reason, for example, conditions such as ion implantation and heat treatment in forming the channel layer 13 and the source layer 15 can be changed based on a slight change in the quality of the trench 16, and a highly reliable semiconductor device can be manufactured.

(Second Embodiment)
A second embodiment will be described. In the present embodiment, the trench gate structure is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment, and thus the description thereof is omitted here.

  In the present embodiment, as shown in FIGS. 8 and 9, the trench gate structure is a so-called split gate structure. Specifically, in each trench 16, a shield electrode 26 is disposed on the bottom side, and a gate electrode 18 is disposed on the opening side. In other words, the shield electrode 26 and the gate electrode 18 are stacked in each trench 16. An upper gate structure is constituted by the gate electrode 18 arranged on the upper stage side of the trench 16, and a lower gate structure is constituted by the shield electrode 26 arranged on the bottom side of the trench 16.

  Note that the gate insulating film 17 is disposed between the shield electrode 26 and the gate electrode 18. The gate electrode 18 is formed from the one surface 10 a side of the semiconductor substrate 10 to a position deeper than the bottom of the channel layer 13. That is, the gate electrode 18 is disposed on the opening side of the trench 16, but is disposed so that a channel connecting the source layer 15 and the drift layer 12 is formed in the channel layer 13 when a gate voltage is applied. ing. Each gate electrode 18 is electrically connected to the gate liner 19 as in the first embodiment.

  Each trench 16 extends from the cell region 1 to the outer peripheral region 2 as shown in FIG. In the present embodiment, the trench 16 is formed so that one end in the extending direction is located in the outer peripheral region 2. As shown in FIGS. 9 and 10, each shield electrode 26 is drawn to the opening of the trench 16 at a portion located in the outer peripheral region 2 of the trench 16, and the shield formed in the outer peripheral region 2. It is electrically connected to the liner 27.

  In the present embodiment, the shield liner 27 is electrically connected to the source electrode layer 23 through an Al wiring or the like and has the same potential as the source electrode layer 23 in a cross section different from FIG. That is, the shield electrode 26 is maintained at the potential of the source electrode layer 23. In addition, the shield liner 27 extends in a direction orthogonal to the extending direction of the trench 16 on one end side in the extending direction of the trench 16 and has a shape having an end.

  In the outer peripheral region 2, as shown in FIGS. 9 and 10, a P-type outer peripheral resurf layer 28 is formed below the shield liner 27. Further, in the outer peripheral region 2, a P-type layer 29 connected to the outer peripheral resurf layer 28 is formed in a region different from the lower part of the shield liner 27. In the present embodiment, the outer peripheral RESURF layer 28 and the P-type layer 29 are connected to form a guard ring 30 that surrounds the cell region 1. In the present embodiment, the P-type layer 29 corresponds to the third impurity region.

  The above is the configuration of the semiconductor device in this embodiment. Next, the manufacturing process of the semiconductor device will be described with reference to FIGS. 11 is a cross-sectional view corresponding to FIG. 9, and FIG. 12 is a cross-sectional view corresponding to FIG.

  First, as shown in FIGS. 11A and 12A, a mask (not shown) is arranged on one surface 10a of the semiconductor substrate 10, and a P type is formed at a position including a lower region where the shield liner 27 is formed. An outer peripheral resurf layer 28 is formed by ion implantation of impurities as appropriate and thermal diffusion. Thereafter, the mask is removed. Note that this step is performed simultaneously with the step of forming the RESURF layer 14 although not particularly illustrated.

  Next, as shown in FIGS. 11B and 12B, after the trench 16 is formed, the above-described split gate structure is formed by appropriately performing thermal oxidation, CVD, or the like. At this time, the trench 16 is extended to the outer peripheral region 2. Further, when the shield electrode 26 is formed, the shield electrode 26 is drawn to the opening of the trench 16 at a portion located in the outer peripheral region 2 of the trench 16. Then, Poly-Si formed on the one surface 10 a of the semiconductor substrate 10 is appropriately patterned to form a shield liner 27 that is electrically connected to the shield electrode 26.

  Subsequently, as shown in FIGS. 11C and 12C, a channel layer 13 and a source layer 15 are formed by ion implantation of P-type impurities and N-type impurities and thermal diffusion. In this step, impurities are not implanted below the shield liner 27 using the shield liner 27 as a mask. For this reason, the guard ring 30 is formed in the outer peripheral region 2 by forming the P-type layer 29 so as to be connected to the outer peripheral resurf layer 28 in a cross section different from FIG.

  Thereafter, although not particularly shown, the semiconductor device is manufactured by forming the source electrode layer 23, the gate electrode layer 24, and the like, as in the first embodiment.

  Thus, a semiconductor device having a split gate structure may be used. In addition, by arranging the shield electrode 26 on the bottom side of the trench 16, it is possible to suppress the occurrence of electric field concentration at the bottom portion of the trench 16 and to improve the breakdown voltage.

(Third embodiment)
A third embodiment will be described. In the present embodiment, the configuration of the shield liner 27 is changed with respect to the second embodiment, and the other aspects are the same as those of the second embodiment, and thus the description thereof is omitted here.

  In the present embodiment, as shown in FIG. 13, shield liners 27 are formed in the outer peripheral region 2 at both end portions in the extending direction of the trench 16. Although not shown in particular, the trench 16 extends to the outer peripheral region 2 at both ends in the extending direction. The shield electrode 26 is drawn to the opening at both ends in the extending direction of the trench 16 and is electrically connected to each shield liner 27 formed in the outer peripheral region 2.

  Further, in the outer peripheral region 2, a P-type outer peripheral resurf layer 28 is formed below each shield liner 27. A P-type layer 29 that is connected to each outer peripheral resurf layer 28 and constitutes a guard ring 30 together with each outer peripheral resurf layer 28 is formed in a region different from the lower side of the shield liner 27.

  As described above, in the present embodiment, each shield electrode 26 is drawn from both end sides in the extending direction of the trench 16 and is electrically connected to each shield electrode 26. For this reason, the electric potential in the shield electrode 26 can be made substantially equal.

  Such a semiconductor device is manufactured as follows although not particularly shown. That is, in the steps of FIG. 11A and FIG. 12A, the outer peripheral RESURF layer 28 is formed at a position including a lower region where each shield liner 27 is formed. 11B and FIG. 12B, trenches 16 are formed so that both ends in the extending direction are located in the outer peripheral region 2, and shield electrodes are formed at both ends located in the outer peripheral region 2. 26 and the shield liner 27 are manufactured by being electrically connected.

(Fourth embodiment)
A fourth embodiment will be described. In the present embodiment, the configuration of the shield liner 27 is changed with respect to the third embodiment, and the other aspects are the same as those of the third embodiment, and thus the description thereof is omitted here.

  In the present embodiment, as shown in FIG. 14, the shield liner 27 is formed so as to surround the cell region 1. That is, the shield liner 27 is formed in a frame shape and does not have an end. An outer peripheral resurf layer 28 is formed below the shield liner 27 so as to surround the cell region 1. That is, in the present embodiment, the guard ring 30 is configured only by the outer peripheral resurf layer 28, and the P-type layer 29 is not formed.

  As described above, in this embodiment, the shield liner 27 is formed so as to surround the cell region. Therefore, the electric field strength can be reduced in the entire region on the cell region 1 side in the outer peripheral region 2.

  Such a semiconductor device is manufactured as follows although not particularly shown. That is, in the steps of FIGS. 11A and 12A, the outer peripheral resurf layer 28 is formed so as to surround the cell region 1, and in the steps of FIGS. 11B and 12B, the cell region 1 is formed. It is manufactured by forming a shield liner 27 so as to surround.

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

  For example, in each of the above embodiments, the case where the first conductivity type is the N type and the second conductivity type is the P type has been described. However, the semiconductor device in which the first conductivity type is the P type and the second conductivity type is the N type. It is good. That is, it is good also as a structure which reversed the conductivity type of each part demonstrated by each said embodiment.

  In each of the above embodiments, the RESURF layer 14 may have a higher impurity concentration than the channel layer 13. In each of the above embodiments, the RESURF layer 14 may be deeper than the channel layer 13. According to these, it is possible to further suppress the concentration of a high electric field below the gate liner 19 and further suppress the occurrence of a leak current.

  Further, in each of the above embodiments, the RESURF layer 14 may have a lower impurity concentration than the channel layer 13. In each of the embodiments described above, the RESURF layer 14 may be formed shallower than the channel layer 13. Also in such a semiconductor device, the formation of the RESURF layer 14 can suppress the concentration of a high electric field below the gate liner 19.

  In each of the above embodiments, the RESURF layer 14 may be formed in a part of the region below the gate liner 19. Even in such a semiconductor device, the concentration of a high electric field under the gate liner 19 can be suppressed as compared with the case where the RESURF layer 14 is not formed.

  Furthermore, in each said embodiment, the gate electrode 18 and the gate liner 19 may be formed with a different material, for example, the gate liner 19 may be comprised with aluminum etc. Similarly, in the second to fourth embodiments, the shield electrode 26 and the shield liner 27 may be made of different materials. For example, the shield liner 27 may be made of aluminum or the like.

  In each of the above embodiments, a P-type collector layer may be provided instead of the drain layer 11. That is, an IGBT (that is, an insulated gate bipolar transistor) element may be formed on the semiconductor substrate 10. In such a configuration, the collector layer corresponds to the second impurity region. Alternatively, a semiconductor device having a super junction structure in which an N-type column region and a P-type column region are arranged on the drain layer 11 may be used.

  Furthermore, in each of the above embodiments, the drain layer 11 may be formed in the surface layer portion of the drift layer 12, and a horizontal semiconductor device that allows current to flow in the plane direction of the semiconductor substrate 10 may be used.

  Further, in each of the above embodiments, a barrier metal made of Ti (ie, titanium) or TiN (ie, titanium nitride) is formed on the wall surfaces of the first contact hole 21 and the second contact hole 22. Also good. Such a barrier metal is formed by sputtering or the like before the first and second embedded electrode portions 23a and 24a are formed, for example.

  In each of the above embodiments, the first source electrode layer 23 may be configured by using the same material for the first embedded electrode portion 23a and the first upper electrode portion 23b, for example, aluminum. It may be. Similarly, in the second gate electrode layer 24, the second embedded electrode portion 24a and the second upper layer electrode portion 24b may be made of the same material, and may be made of aluminum, for example.

  Further, in each of the above embodiments, the source layer 15 may be selectively formed on the surface layer portion of the channel layer 13. That is, the one surface 10 a of the semiconductor substrate 10 may have the channel layer 13 and the source layer 15. In this case, the first contact hole 21 need not be formed deeper than the one surface 10a of the semiconductor substrate 10 as long as the channel layer 13 and the source layer 15 are exposed. That is, the first contact hole 21 may be formed so that the channel layer 13 and the source layer 15 are exposed from the one surface 10 a of the semiconductor substrate 10.

11 Drain layer (second impurity region)
12 Drift layer 13 Channel layer 14 RESURF layer 15 Source layer (first impurity region)
16 trench 17 gate insulating film 18 gate electrode 19 gate liner

Claims (8)

A semiconductor device having a trench gate structure,
A first conductivity type drift layer (12);
A second conductivity type channel layer (13) formed on the drift layer;
A first impurity region (15) of a first conductivity type formed in a surface layer portion of the channel layer;
A semiconductor substrate having a first impurity type or second conductivity type second impurity region (11) formed on the opposite side of the channel layer across the drift layer and having a higher impurity concentration than the drift layer. (10) and
A gate that passes through the first impurity region and the channel layer, reaches the drift layer, and is applied with a predetermined gate voltage through a gate insulating film (17) in a trench (16) having a predetermined direction as a longitudinal direction. The trench gate structure in which the electrode (18) is disposed;
A gate liner (19) formed on the semiconductor substrate and electrically connected to the gate electrode;
The gate liner is formed so as to extend in a direction intersecting the longitudinal direction of the trench when viewed from a normal direction with respect to the surface direction of the semiconductor substrate, and to intersect the trench,
The channel layer is formed in a region different from a region located below the gate liner;
A semiconductor device in which a second conductivity type RESURF layer (14) connected to the channel layer is formed in a region on the drift layer and below the gate liner.   The semiconductor device according to claim 1, wherein the gate liner is located in the RESURF layer when viewed from a normal direction with respect to a surface direction of the semiconductor substrate.   The semiconductor device according to claim 1, wherein the RESURF layer has a higher impurity concentration than the channel layer.   The semiconductor device according to claim 1, wherein the RESURF layer is formed deeper than the channel layer. In the trench, a shield electrode (26) maintained at a predetermined potential is disposed on the bottom side of the trench through the gate insulating film, and the gate electrode is disposed on the opening side of the trench. ,
When the region where the gate electrode is disposed is a cell region (1) and the region surrounding the cell region is an outer peripheral region (2),
The trench has an end in the longitudinal direction extending to the outer peripheral region,
The shield electrode is drawn to the opening of the trench at a portion located in the outer peripheral region of the trench,
A shield liner (27) electrically connected to the shield electrode at the opening of the trench is formed on the semiconductor substrate,
In the region on the drift layer and below the shield liner, an outer peripheral resurf layer (28) of the second conductivity type is formed,
The semiconductor device according to any one of claims 1 to 4, wherein a guard ring (30) including the outer peripheral resurf layer is formed in the outer peripheral region. A method of manufacturing a semiconductor device having a trench gate structure,
Providing a semiconductor substrate (10) having a drift layer (12) of a first conductivity type;
Forming a trench (16) in the semiconductor substrate having a predetermined direction as a longitudinal direction;
Forming the trench gate structure by forming a gate electrode (18) to which a predetermined gate voltage is applied via a gate insulating film (17) in the trench;
Forming a gate liner (19) electrically connected to the gate electrode on the semiconductor substrate;
After the gate liner is formed, impurities are ion-implanted and heat-treated to form a second conductivity type channel layer (13) on the drift layer, and the first conductive layer is formed on the surface layer of the channel layer. Forming a first impurity region (15) of the mold;
In forming the gate liner, the gate liner extends in a direction intersecting with the longitudinal direction of the trench when viewed from the normal direction to the surface direction of the semiconductor substrate, and the gate liner is intersected with the trench. Forming,
Before forming the trench, forming a second conductivity type RESURF layer (14) in a region below the gate liner;
A method of manufacturing a semiconductor device, wherein forming the channel layer includes forming the channel layer connected to the RESURF layer. In preparing the semiconductor substrate, the semiconductor substrate having a cell region (1) in which the gate electrode is disposed and an outer peripheral region (2) surrounding the cell region is prepared,
In forming the trench, the trench extending from the cell region to the outer peripheral region is formed,
In forming the trench gate structure, forming a shield electrode (26) maintained at a predetermined potential on the bottom side of the trench, forming the gate electrode on the opening side of the trench, And
In the formation of the shield electrode, the shield electrode drawn to the opening of the trench is formed at a portion located in the outer peripheral region of the trench,
Forming a shield liner (27) electrically connected to the shield electrode in the outer peripheral region;
Before forming the trench, an outer peripheral resurf layer (28) of a second conductivity type including at least a part of a guard ring (30) surrounding the cell region, including a region below the shield liner. The method for manufacturing a semiconductor device according to claim 6, wherein the forming is performed. In forming the shield liner, the shield liner having an end is formed,
In the formation of the channel layer and the first impurity region, the ion implantation and the heat treatment are performed so that the channel layer and the first impurity region are connected to the outer peripheral resurf layer and form the guard ring together with the outer peripheral resurf layer. The method of manufacturing a semiconductor device according to claim 7, wherein the third impurity region (29) is formed.

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