JP2019095516A - Optical semiconductor element and manufacturing method of the same - Google Patents

Abstract

To provide an optical semiconductor element capable of suppressing deterioration of a core layer and forming a high-resistance region, and a manufacturing method of the optical semiconductor element.SOLUTION: The optical semiconductor element comprises: an optical waveguide including a core layer and a first clad layer provided on the core layer and doped with a first element; and a plurality of modulation electrodes provided on the optical waveguide and separated from each other in an extending direction of the optical waveguide. The optical waveguide includes a modulation part positioned under the modulation electrode, and a separation part positioned between the plurality of modulation electrodes and doped with a second element to have higher resistance than the modulation part. The separation part includes a first separation part and a second separation part. Density of the second element in the second separation part in depth direction is lower than that in the first separation part.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an optical semiconductor device and a method of manufacturing the same.

  As an optical modulator of an optical communication system, an element that modulates continuous light using an electrical signal is used. There is a Mach-Zehnder type optical modulator as a modulator having a high modulation speed and a long transmission distance. A plurality of modulation electrodes are provided to adjust the modulation speed. By forming a layer of high resistance in the region between the modulation electrodes of the optical waveguide, the modulation electrodes are electrically separated (for example, Patent Document 1).

Unexamined-Japanese-Patent No. 2004-102160

  A highly resistive region can be formed by ion implantation into the semiconductor layer of the optical waveguide. However, when the ions reach the core layer, the crystallinity of the core layer is degraded.

  Therefore, it is an object of the present invention to provide an optical semiconductor device capable of suppressing deterioration of a core layer and forming a high-resistance region, and a method of manufacturing the same.

  An optical semiconductor device according to the present invention comprises an optical waveguide including a core layer and a first cladding layer provided on the core layer and doped with the first element, and provided on the optical waveguide, A plurality of modulation electrodes spaced apart from one another in an extending direction, wherein the optical waveguide is located between a modulation section located below the modulation electrode and the plurality of modulation electrodes, and is doped with a second element The separation unit includes a separation unit having a higher resistance than the modulation unit, the separation unit includes a first separation unit and a second separation unit, and the concentration of the second element of the second separation unit in the depth direction is It is lower than the first separation part.

  In the method of manufacturing an optical semiconductor device according to the present invention, a step of growing a core layer, a step of forming a cladding layer doped with a dopant on the core layer, and a plurality of openings on the cladding layer Forming the first mask, forming the second mask on the first mask and between the plurality of openings, and forming the second mask; By implanting ions into the layer, a first separation portion is formed in a portion of the cladding layer in the opening of the first mask, and a portion covered by the first mask and not covered by the second mask is formed. And forming a modulation electrode on the portion of the cladding layer covered by the second mask after removing the first mask and the second mask.

  According to the above invention, it is possible to suppress the deterioration of the core layer and to form a high resistance region.

FIG. 1 is a plan view illustrating an optical semiconductor device according to the first embodiment. FIG. 2A to FIG. 2C are cross-sectional views illustrating the optical semiconductor device. FIG. 3A is a plan view illustrating the method for manufacturing the optical semiconductor device. 3 (b) to 3 (d) are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 4A is a plan view illustrating the method for manufacturing the optical semiconductor device. FIG. 4B to FIG. 4D are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 5A to FIG. 5C are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. 6 (a) to 6 (c) are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 7A is a plan view illustrating the method for manufacturing the optical semiconductor device. 7 (b) to 7 (d) are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 8A is a plan view illustrating the method for manufacturing the optical semiconductor device. 8 (b) to 8 (d) are cross-sectional views illustrating a method for manufacturing an optical semiconductor device. FIG. 9A to FIG. 9C are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 10A is a plan view illustrating the method for manufacturing the optical semiconductor device. 10 (b) to 10 (d) are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIGS. 11A and 11B show the results of simulation of the density of ions. FIG. 12A is a plan view illustrating an optical semiconductor device according to the second embodiment. FIG. 12B is a cross-sectional view illustrating an optical semiconductor device. FIG. 13A is a plan view illustrating the method for manufacturing the optical semiconductor device. FIG. 13B is a cross-sectional view illustrating the method for manufacturing the optical semiconductor device. FIG. 14A is a plan view illustrating the method for manufacturing the optical semiconductor device. FIG. 14B and FIG. 14C are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 15 is a plan view illustrating an optical semiconductor device according to the third embodiment. 16 (a) to 16 (c) are cross-sectional views illustrating an optical semiconductor device. FIG. 17A to FIG. 17C are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 18A is a plan view illustrating the method for manufacturing the optical semiconductor device. 18 (b) to 18 (d) are cross-sectional views illustrating the method for manufacturing the optical semiconductor device. FIG. 19 is a plan view illustrating an optical semiconductor device according to a fourth embodiment.

Description of an embodiment of the present invention
First, the contents of the embodiment of the present invention will be listed and described.

According to one aspect of the present invention, there is provided an optical waveguide including: (1) a core layer, and an optical waveguide including a first cladding layer provided on the core layer and doped with the first element, and the optical waveguide, And a plurality of modulation electrodes spaced apart from each other in the extending direction of the optical waveguide, wherein the optical waveguide is located between the modulation section located below the modulation electrode and the plurality of modulation electrodes, and the second element is doped The separation portion includes a first separation portion and a second separation portion, and the concentration of the second element of the second separation portion in the depth direction is The optical semiconductor device may be lower than the first separation unit. The separation part is a high resistance area, and in particular, the first separation part is a high resistance area than the second separation part. Therefore, the plurality of modulation units are electrically separated. Since the second element hardly penetrates into the core layer in the second separation portion, the deterioration of the crystallinity of the core layer is suppressed.
(2) In the extending direction of the optical waveguide, the first separation unit may be adjacent to the modulation unit, and the second separation unit may be positioned between the plurality of first separation units adjacent to the modulation unit. Good. The first separation portion has high resistance and is not susceptible to an electric field leaking out from the modulation electrode. Therefore, the loss of the modulation signal, the deterioration of the characteristics and the like are suppressed.
(3) In the extending direction of the optical waveguide, the second separation unit is adjacent to the modulation unit, and another second separation unit is positioned between the plurality of second separation units adjacent to the modulation unit. The first separation unit may be located between a second separation unit adjacent to the modulation unit and the another second separation unit. The highly crystalline portion of the core layer is located near the modulator. Therefore, the influence of the electric field in the vicinity of the modulation electrode on the core layer is suppressed, and the deterioration of the characteristics is suppressed.
(4) In the extension direction of the optical waveguide, the second separation portion may be longer than the first separation portion. Thereby, the deterioration of the crystallinity of the core layer can be suppressed.
(5) The first element may be zinc, and the second element may be at least one of hydrogen, boron, oxygen, sulfur, selenium, iron, chromium and ruthenium. Thereby, the separation part can be formed.
(6) The first element may be silicon, and the second element may be at least one of beryllium, magnesium, zinc and cadmium. Thereby, the separation part can be formed.
(7) The first cladding layer may be formed of indium phosphorus. A separation portion can be formed by doping indium phosphorus with a second element.
(8) An undoped second cladding layer may be provided between the core layer and the first cladding layer. Thereby, light loss can be suppressed.
(9) A step of growing a core layer, a step of forming a cladding layer doped with a dopant on the core layer, and a step of forming a first mask having a plurality of openings on the cladding layer And implanting ions into the cladding layer after the step of forming a second mask between the plurality of openings above the first mask and the step of forming the second mask, Forming a first separation portion in a portion of the cladding layer in the opening of the first mask, and forming a second separation portion in a portion covered by the first mask and not covered by the second mask; Forming a modulation electrode on the portion of the cladding layer covered by the second mask after removing the first mask and the second mask. As a result, deterioration of the core layer can be suppressed, and a region of high resistance can be formed.

[Details of the Embodiment of the Present Invention]
Specific examples of an optical semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to these exemplifications, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

(Optical semiconductor device)
FIG. 1 is a plan view illustrating an optical semiconductor device 100 according to a first embodiment. As shown in FIG. 1, the optical semiconductor element 100 is a Mach-Zehnder type optical modulator including an incident waveguide 1, optical waveguides 2 a and 2 b, and an outgoing waveguide 3.

  The two optical waveguides 2a and 2b are arm waveguides extending in the Z direction in FIG. 1 and are connected to the incident waveguide 1 via the branch waveguide 4 and to the output waveguide 3 via the branch waveguide 5 It is done. The optical waveguides 2a and 2b are separated from each other in the X direction.

  A plurality of modulation electrodes 26 are disposed on the optical waveguides 2 a and 2 b, respectively, and the plurality of modulation electrodes 26 are separated from each other and electrically connected by the wiring 28. The two wires 28 are connected to the high frequency power supply 6 and the resistor 7. The high frequency power supply 6 and the resistor 7 may be provided outside the optical semiconductor device 100 or may be provided inside.

  The continuous light is incident on the incident waveguide 1 and is inputted to the optical waveguides 2 a and 2 b by the branching waveguide 4. A high frequency voltage of, for example, about 2 V input from the high frequency power supply 6 is applied to the optical waveguides 2 a and 2 b through the wiring 28 and the modulation electrode 26. The high frequency voltage modulates the light passing through the optical waveguides 2a and 2b. The modulated light is multiplexed by the branch waveguide 5 and output from the emission waveguide 3 to the outside of the optical semiconductor device 100. The speed at which the modulation signal propagates through the wiring 28 is faster than the speed at which light propagates through the optical waveguide. Since the plurality of modulation electrodes 26 have a capacity, the propagation speed of the modulation signal is reduced to match the propagation speed of light.

  The optical waveguides 2a and 2b have a separating unit that has a higher resistance than the modulating unit R3 and the modulating unit R3. Specifically, the optical waveguides 2a and 2b include a first separation portion R1, a second separation portion R2 and a modulation portion R3, and these regions are aligned in the extension direction (Z direction) of the optical waveguide. The modulation unit R3 is a region in which the modulation electrode 26 is provided. The second separation unit R2 is a region having a higher electrical resistance than the modulation unit R3, and the first separation unit R1 is a region having a higher electrical resistance than the second separation unit R2. The width in the Z direction of the first separation portion R1 is 5 μm, for example. The width of the second separation part R2 is larger than that of the first separation part R1.

  2 (a) to 2 (c) are cross-sectional views illustrating the optical semiconductor device 100, and FIG. 2 (a) illustrates a cross section taken along line A-A of FIG. Corresponds to FIG. 2B illustrates a cross section along line B-B, which corresponds to the second separation portion R2. FIG. 2C illustrates a cross section taken along line C-C, which corresponds to a region from the first separation unit R1 to the modulation unit R3.

  As shown in FIG. 2A, the substrate 10, the buffer layer 12, the lower cladding layers 14 and 16, the core layer 18, the upper cladding layers 20 and 22, and the contact layer 24 are sequentially stacked in the Y direction. The optical waveguides 2a and 2b are waveguide mesas having the same configuration and including the lower cladding layer 16, the core layer 18, the upper cladding layers 20 and 22, and the contact layer 24, respectively. The optical waveguides 2a and 2b are embedded with a resin 30 such as BCB (benzocyclobutene). The upper surface of the contact layer 24 and the upper surface of the resin 30 form the same plane, and the modulation electrode 26 is in contact with these upper surfaces. A wire 28 connected to the modulation electrode 26 is disposed on the top surface of the resin 30. Isolation trenches 9 are formed in the buffer layer 12 and the lower cladding layer 14.

  As shown in FIG. 2B and FIG. 2C, the high resistance layer 34 is formed in the second separation portion R2. As described later, the high resistance layer 34 is formed by ion implantation into a part of the upper cladding layer 22. Upper cladding layers 20 and 22 are located under high resistance layer 34.

  As shown in FIG. 2C, the high resistance layer 32 is formed in the first separation portion R1. As described later, the high resistance layer 32 is formed by implanting ions into the upper cladding layers 20 and 22 and a part of the core layer 18. The high resistance layer 32 traverses the upper cladding layers 20 and 22 in the Y direction.

  The substrate 10 is, for example, a semiconductor substrate formed of semi-insulating indium phosphide (InP) or the like. The buffer layer 12 is formed of, for example, semi-insulating InP having a thickness of 200 nm. The lower cladding layers 14 and 16 are each formed of, for example, n-type InP with a thickness of 500 nm, and are doped with, for example, silicon (Si) as an n-type dopant. The core layer 18 is, for example, a 500 nm thick multiple quantum well layer (MQW: Multi Quantum Well), which is a stacked layer of undoped aluminum gallium indium arsenide (AlGaInAs) well layers and aluminum indium arsenide (AlInAs) barrier layers. It is.

  The upper cladding layer 20 (second cladding layer) is formed of, for example, undoped InP with a thickness of 200 nm or less. Although the light loss due to the p-type carrier can be suppressed by the undoped upper cladding layer 20, a voltage drop occurs. In order to suppress the voltage drop, the thickness is preferably 200 nm or less. The upper cladding layer 22 (first cladding layer) is formed of, for example, p-type InP with a thickness of 1200 nm. The contact layer 24 is formed of, for example, p-type GaInAs having a thickness of 300 nm. The p-type dopant (first element) is, for example, zinc (Zn).

  The high resistance layer 32 and the high resistance layer 34 are formed by implanting hydrogen ions (proton, second element) into the upper cladding layers 20 and 22, and have higher electric resistance than the upper cladding layer 22. Injection of protons causes crystal defects in the semiconductor. Crystal defects form donor-type levels, capture holes in p-type InP, and compensate for acceptors. Therefore, when the proton concentration becomes large enough to compensate for the acceptor concentration, the p-type InP is made high in resistance. The electrical resistance of the high resistance layer 32 and the ion concentration in the depth direction (Y direction) are higher than that of the high resistance layer 34. Since protons reach a part of the core layer 18 in the first separation portion R 1, the high resistance layer 32 is formed of the upper cladding layers 20 and 22 and the core layer 18. The thickness of the high resistance layer 32 is, for example, about 1400 nm, and the thickness of the high resistance layer 34 is, for example, about 1000 nm.

  The wiring 28 and the modulation electrode 26 are, for example, integral and formed of a metal such as titanium (Ti), platinum (Pt) and gold (Au).

(Production method)
FIG. 3A, FIG. 4A, FIG. 7A, FIG. 8A, and FIG. 10A are plan views illustrating the method for manufacturing the optical semiconductor device 100. FIG. 3 (b) to 3 (d), 4 (b) to 4 (d), 5 (a) to 6 (c), 7 (b) to 7 (d), 8 (B) to FIG. 8 (d), FIG. 9 (a) to FIG. 9 (c), and FIG. 10 (b) to FIG. 10 (d) are cross-sectional views illustrating the method of manufacturing the optical semiconductor device 100. The cross section along line A-A, line B-B and line C-C of the corresponding plan view is illustrated.

  As shown in FIGS. 3 (b) to 3 (d), buffer layer 12, lower cladding layers 14 and 16, and substrate 10 are formed on substrate 10 by metal organic vapor phase epitaxy (MOVPE) or the like, for example. The core layer 18, the upper cladding layers 20 and 22, and the contact layer 24 are epitaxially grown. The dopant diffuses during the growth of the layer or under a high temperature environment. After the growth, Zn may diffuse from the upper cladding layer 22 to the upper cladding layer 20, and the p-type InP may become thick. Therefore, the thickness of the upper cladding layer 20 in epitaxial growth is made larger than the desired thickness so that the upper cladding layers 20 and 22 have the desired thickness after Zn diffusion, and the thickness of the upper cladding layer 22 is larger than the desired thickness. It may be set small.

After that, as shown in FIGS. 3A to 3D, an insulating film 40 (first mask) of silicon oxide (SiO ₂ ) having a thickness of 400 nm, for example, is formed on the entire surface of the wafer, and photolithography and wet etching A plurality of openings 40a are formed in the insulating film 40 by means of, for example. As shown in FIGS. 3A and 3D, the contact layer 24 is exposed from the opening 40a.

  As shown in FIGS. 4A, 4B and 4D, a resist mask 42 (second mask) is formed on a portion of the surface of the insulating film 40 corresponding to the modulation portion R3. The resist mask 42 is formed of, for example, a resin having a thickness of 3 μm. The end of the resist mask 42 coincides with the end of the opening 40 a. As shown in FIGS. 4A and 4D, the resist mask 42 is not formed on the first separation portion R1 and the second separation portion R2.

  In the steps shown in FIGS. 5A to 5C, protons are injected from above the insulating film 40 and the resist mask 42. The penetration depth of protons depends on the acceleration voltage. The acceleration voltage is, for example, 40 to 200 keV, and multiple injections are performed. For example, ion implantation for 300 seconds is performed at each acceleration voltage while increasing the acceleration voltage by 20 keV in the range of 40 to 200 keV. Also, in order to average the direction of incidence of protons, protons are incident while the wafer is tilted and rotated with respect to the proton beam.

  As shown in FIGS. 5A and 5C, protons do not pass through the resist mask 42, and protons are not injected under the resist mask 42. As shown in FIGS. 5 (b) and 5 (c), protons are injected into the portion where the resist mask 42 is not provided. Since protons passing through the opening 40a have high energy, the implantation depth is increased. The protons passing through the opening 40 a are injected into the contact layer 24, the upper cladding layer 22, the upper cladding layer 20 and part of the core layer 18 to form the high resistance layer 32 shown in FIG. 5 (c).

  On the other hand, protons pass through the insulating film 40, but the energy is attenuated by the insulating film 40. For this reason, the depth which the proton which permeate | transmits the insulating film 40 can reach becomes small. Protons are injected into part of the contact layer 24, the upper cladding layer 22, and the upper cladding layer 20 to form the high resistance layer 34 shown in FIGS. 5 (b) and 5 (c). The high resistance layer 32 reaches a position deeper than the upper cladding layers 20 and 22, and the high resistance layer 34 does not easily reach the core layer 18.

  As shown in FIGS. 6A to 6C, the insulating film 40 and the resist mask 42 are removed. As shown in FIGS. 7A to 7C, a mesa is formed by photolithography and dry etching. As shown in FIG. 7D, the high resistance layers 32 and 34 are aligned in the extension direction of the optical waveguides 2a and 2b. As shown in FIGS. 8A to 8D, portions of the buffer layer 12 and the lower cladding layer 14 are removed by photolithography and wet etching to form an isolation trench 9. Thereby, the plurality of optical semiconductor devices in the wafer are electrically separated. An n-type electrode (not shown) may be formed on the lower cladding layer 14.

The resin 30 is formed as shown in FIGS. 9 (a) to 9 (c). As shown in FIGS. 9B and 9C, a part of the high resistance layers 32 and 34 (approximately the same thickness as the contact layer 24) is removed by etching or the like, and then the resin 30 is removed. Form The high resistance layers 32 and 34 are embedded in the resin 30. As shown in FIGS. 9A and 9B, the resin 30 and the contact layer 24 form the same plane, and the contact layer 24 is exposed from the resin 30. A protective film of an insulator such as silicon nitride (SiN) and SiO ₂ may be provided on the wafer before the formation of the resin 30.

  As shown in FIGS. 10A to 10D, the wiring 28 and the modulation electrode 26 are formed by a vapor deposition method or a plating method. A pad or the like for connection to the high frequency power supply 6 shown in FIG. 1 may be formed. Thus, the optical semiconductor element 100 is formed.

  As described above, according to the first embodiment, ion implantation is performed using the insulating film 40 and the resist mask 42 as a mask. Thus, a first separation portion R1 having the high resistance layer 32 and a second separation portion R2 having the high resistance layer 34 are formed between the plurality of modulation portions R3.

  FIGS. 11A and 11B show the results of simulation of the density of ions. In the simulation, for example, protons are implanted for 300 seconds at each acceleration voltage while increasing the acceleration voltage by 20 keV in the range of 40 to 200 keV, for example, to manufacture the optical semiconductor device 100 described above. The horizontal axis is the depth based on the surface of the contact layer 24, and the vertical axis is the normalized implantation density of protons. The normalized injection density is one in which the maximum density of protons is 1 and the density of protons is normalized.

  FIG. 11A is a simulation result in the first separation unit R1. As shown in FIG. 11A, protons are injected from the contact layer 24 to the core layer 18. As shown in FIG. 5C, since the first separation portion R1 is not covered by the insulating film 40 and the resist mask 42, protons have high energy and are deeply implanted. That is, the density in the depth direction is increased. As a result, the high resistance layer 32 is formed.

  FIG. 11B is a simulation result in the second separation unit R2. As shown in FIG. 11 (b), protons are injected from the contact layer 24 to the upper cladding layer 20, and the peak of proton density is located in the contact layer 24. On the other hand, the proton density in the core layer 18 is approximately zero. As shown in FIG. 5C, the second separation portion R2 is not covered by the resist mask 42, but is covered by the insulating film 40. The proton loses energy when passing through the insulating film 40, and the implantation depth becomes shallower than the first separation portion R1. That is, the density in the depth direction becomes lower. As a result, the high resistance layer 34 is formed.

  The first separation unit R1 and the second separation unit R2 can electrically separate the adjacent modulation units R3. In particular, since the high resistance layer 32 of the first separation portion R1 has a higher resistance than the high resistance layer 34, electrical separation is effectively performed. As shown in FIG. 11A, since protons are injected into the core layer 18 in the first separation portion R1, the crystallinity of the core layer 18 may be degraded. On the other hand, as shown in FIG. 11B, the injection of protons into the core layer 18 is suppressed in the second separation part R2. Therefore, the deterioration of the crystallinity of the core layer 18 can be suppressed. That is, it is possible to suppress the deterioration of the core layer 18 and to form a high resistance region.

The proton concentration of the high resistance layers 32 and 34 is such that the upper cladding layer 22 has a high resistance or an n-type. In order to maintain the crystallinity of the core layer 18 high, the high resistance layer 34 is preferably formed of a portion on the + Y side of the upper cladding layer 22 and not formed on the core layer 18. The proton concentration of the high resistance layer 34 is lower than that of the high resistance layer 32. For example, the proton concentration reaching the core layer 18 is preferably about 1 × 10 ¹⁶ cm ⁻³ . The high resistance layer 32 preferably cuts the conductive upper cladding layer 22 longitudinally in the Y direction, and the proton concentration preferably exceeds the Zn concentration of the upper cladding layer 22, for example, 1 × 10 ¹⁸ cm ⁻³ or more. The high resistance layer 34 alone may cause insufficient electrical separation between the modulation portions R3. However, the high resistance layer 32 having high resistance sufficiently performs electrical separation.

  In order to insulate between the two modulation parts R3, the width of the first separation part R1 (the width of the high resistance layer 32) in the Z direction is preferably, for example, 3 μm or more. However, when the first separation portion R1 is long, the low crystallinity portion in the core layer 18 is long, and the reliability is lowered. Therefore, the width of the first separation portion R1 is, for example, 10 μm or less, and the second separation portion R2 is preferably longer than the first separation portion R1, and is, for example, about 90 μm. It is preferable that, for example, 90% or more of the region between the two modulation portions R3 is the second separation portion R2, and the remaining approximately 10% is the first separation portion R1. Thereby, the reliability of the optical semiconductor device 100 is improved.

  The first separation portion R1 is adjacent to the modulation portion R3 in the extending direction (Z direction) of the optical waveguides 2a and 2b. Since the high resistance layer 32 has high resistance, it is unlikely to be affected by the electric field leaking out of the modulation electrode 26. Therefore, the loss of the modulation signal, the deterioration of the characteristics of the optical semiconductor device 100 and the like are suppressed. In particular, it is preferable that the first separation unit R1 be adjacent to each of the plurality of modulation units R3 and the first separation unit R1 be disposed on both sides of one modulation unit R3.

  The optical semiconductor device 100 includes, for example, a compound semiconductor containing at least one of gallium (Ga), arsenic (As), antimony (Sb), aluminum (Al), indium (In), phosphorus (P), and nitrogen (N). Can be used. Alternatively, a silicon-based semiconductor may be used. As shown in FIG. 2A to FIG. 2C, the optical waveguides 2a and 2b have a pin structure.

  The upper cladding layer 22 can be InP or the like to which a p-type dopant (for example, Zn or the like) is added. Crystal defects are formed in the upper cladding layer 22 by implanting protons or boron (B) ions or the like into the p-type upper cladding layer 22, and the crystal defects compensate for the p-type carriers. Thereby, high resistance layers 32 and 34 are formed. In addition, when the p-type carrier concentration is lowered, light absorption by the p-type carrier is suppressed. At least one ion of oxygen (O), sulfur (S), selenium (Se), iron (Fe), chromium (Cr) and ruthenium (Ru) may be implanted. The ions of O, S, and Se form donor-type levels and trap p-type carriers. Ions of transition metals such as Fe, Cr, and Ru form deep levels and trap p-type carriers. Thereby, high resistance layers 32 and 34 may be formed. Alternatively, silicon (Si) ions may be used.

  The upper cladding layer 22 may be doped with Si or the like to be n-type. For example, the resistance is increased by implanting at least one ion of beryllium (Be), magnesium (Mg), zinc (Zn), cadmium (Cd), carbon (C) and the like into the n-type upper cladding layer 22. These ions trap n-type carriers by forming acceptor levels. The conductivity type of the high resistance layers 32 and 34 can be opposite to that of the upper cladding layer 22.

  In order to uniformly implant the ions, it is preferable to perform the ion implantation while rotating the wafer. Further, the acceleration voltage of ions, the number of times of implantation, and the like can be determined according to the thickness of the layer, the desired implantation depth, and the like.

  In order to make the ion implantation depths different and to form the first separation part R1, the second separation part R2 and the modulation part R3, masks having different thicknesses may be used. In the example of FIG. 4A to FIG. 4D, a mask is formed of the insulating film 40 and the resist mask 42. Instead of the insulating film 40, for example, a resin film such as polyimide, an epitaxial semiconductor layer of InP, or the like may be used. Alternatively, for example, a single layer mask may be provided and part of the mask may be thinned by etching. As a result, a difference occurs in the ion implantation depth, and the first separation unit R1, the second separation unit R2, and the modulation unit R3 can be formed. However, it is difficult to control the thickness of the mask and to form it by etching. Therefore, it is preferable to use a plurality of films formed of different materials and having an etching selectivity, such as the resist mask 42 and the insulating film 40.

(Optical semiconductor device)
FIG. 12A is a plan view illustrating the optical semiconductor device 200 according to the second embodiment. FIG. 12B is a cross-sectional view illustrating the optical semiconductor device 200, and illustrates a cross-sectional view along the line C-C in FIG. The description of the same configuration as that of the first embodiment is omitted.

  As shown in FIGS. 12A and 12B, two first separation parts R1 and three second separation parts R2 (R2a and R2b) are formed between two modulation parts R3. . The second separation unit R2a is adjacent to the modulation unit R3 and the second separation unit R2b is separated from the modulation unit R3. The first separation part R1 is located between the second separation parts R2a and R2b. That is, the second separation unit R2a, the first separation unit R1, the second separation unit R2b, the first separation unit R1, and the second separation unit R2a are arranged from one modulation unit R3 to the next modulation unit R3. The width of the first separation portion R1 and the second separation portion R2a is, for example, 5 μm and 3 μm or more. The second separation part R2b is larger than the first separation part R1 and the second separation part R2a.

(Production method)
FIG. 13A and FIG. 14A are plan views illustrating the method of manufacturing the optical semiconductor device 200. 13 (b), 14 (b) and 14 (c) are cross-sectional views illustrating the method for manufacturing the optical semiconductor device 200, and illustrate cross-sections along line C-C of the corresponding plan views.

  As shown in FIGS. 13A and 13B, the insulating film 40 is formed on the contact layer 24. The distance between the two openings 40 a in the second embodiment is smaller than the distance in the first embodiment.

  As shown in FIGS. 14A and 14B, a resist mask 42 is formed on the insulating film 40. As shown in FIG. 14C, the high resistance layers 32 and 34 are formed by injecting protons. The subsequent steps are the same as in Example 1.

  According to the second embodiment, as in the first embodiment, the modulation units R3 adjacent to each other can be electrically separated by the first separation unit R1. In addition, since the injection of protons into the core layer 18 is suppressed in the second separation portions R2a and R2b, the deterioration of the crystallinity of the core layer 18 can be suppressed.

  The second separation unit R2a is adjacent to the modulation unit R3, and the first separation unit R1 is located farther from the modulation unit R3 than the second separation unit R2a. Therefore, in the core layer 18, the portion with high crystallinity is located near the modulation portion R3, and the portion with reduced crystallinity is located far from the modulation portion R3. Therefore, the influence of the electric field in the vicinity of the modulation electrode 26 on the core layer 18 is suppressed, and the deterioration of the characteristics of the optical semiconductor element 200 is suppressed.

(Optical semiconductor device)
FIG. 15 is a plan view illustrating an optical semiconductor device 300 according to the third embodiment. 16A to 16C are cross-sectional views illustrating the optical semiconductor device 300. As shown in FIGS. 15 to 16B, the opening 30a is formed in the resin 30, and the lower cladding layer 14 is exposed from the opening 30a. A ground electrode 50 is provided inside the opening 30 a and on the upper surface of the lower cladding layer 14. Thus, the optical semiconductor device 300 has a traveling wave type electrode structure.

  The ground electrode 50 is separated from the wiring 28 and the modulation electrode 26, extends in the Z direction, and is grounded. The two wires 28 are connected to each other via the resistors 7a and 7b. One end of each of the resistors 7a and 7b is grounded via a DC power supply. For example, differential signals are input to the pair of wires 28. Further, as shown in FIG. 16C, a first separation part R1 and a second separation part R2 are formed.

(Production method)
FIGS. 17A to 17C and FIGS. 18B to 18D are cross-sectional views illustrating the method for manufacturing the optical semiconductor device 300. FIGS. FIG. 18A is a plan view illustrating the method for manufacturing the optical semiconductor device 300.

  As shown in FIGS. 17A and 17B, the opening 30a is formed in the resin 30 by photolithography and dry etching. As shown in FIG. 17C, no opening is formed in the resin 30 covering the high resistance layers 32 and 34.

  As shown in FIGS. 18A to 18C, the ground electrode 50 is formed on the upper surface of the lower cladding layer 14 by, for example, a vapor deposition method. Further, as shown in FIG. 18A to FIG. 18D, the wiring 28 and the modulation electrode 26 are formed. The subsequent steps are the same as in Example 1.

  According to the third embodiment, as in the first embodiment, the adjacent modulation units R3 can be electrically separated by the first separation unit R1. In addition, since the injection of protons into the core layer 18 is suppressed in the second separation portion R2, the deterioration of the crystallinity of the core layer 18 can be suppressed.

  In the example of FIG. 15, the wiring 28 and the modulation electrode 26 face each other in the X direction, and the ground electrode 50 is located therebetween. For example, the ground electrode 50 may be provided on the outside of each of the wires 28, or the ground electrode 50 may be provided on the outside of the wires 28 and between the modulation electrodes 26.

  FIG. 19 is a plan view illustrating an optical semiconductor device 400 according to the fourth embodiment. As shown in FIG. 19, an optical semiconductor device 400 is an IQ modulator in which two optical semiconductor devices 100 are connected. The two optical semiconductor devices 100 are connected to a high frequency power source (not shown in FIG. 19). One optical semiconductor device 100 generates modulated light of an I (In-phase) channel, and the other optical semiconductor device 100 generates modulated light of a Q (Quadrature-phase) channel. An adjustment electrode or the like for adjusting the phase of each optical semiconductor element 100 may be provided.

  Continuous light is incident through the incident waveguide 52 and the branching waveguide 54. The light modulated by the two optical semiconductor devices 100 is emitted through the branch waveguide 56 and the emission waveguide 58. Multi-level modulation is possible in which light obtained by phase-modulating and amplitude-modulating I and Q channels is orthogonally multiplexed.

  According to the fourth embodiment, as in the first embodiment, the modulation portions R3 can be electrically separated and the deterioration of the crystallinity of the core layer 18 can be suppressed. Although two photo semiconductor devices 100 are used in the example of FIG. 19, any one of the photo semiconductor devices 100, 200 and 300 may be combined. Further, for example, two optical semiconductor devices 400 may be used to constitute a DP-IQ modulator.

Reference Signs List 1, 52 incident waveguide 2a, 2b optical waveguide 3, 58 exit waveguide 4, 5, 54, 56 branch waveguide 6 high frequency power supply 7, 7a, 7b resistance 9 isolation trench 10 substrate 12 buffer layer 14, 16 lower cladding Layer 18 Core layer 20, 22 Upper clad layer 26 Modulated electrode 28 Wiring 30 Resin 30a, 40a Opening 32, 34 High resistance layer 40 Insulating film 42 Resist mask 100, 200, 300, 400 Photo semiconductor element R1 First separation part R2 , R2a, R2b second separation unit R3 modulation unit

Claims (9)

An optical waveguide including a core layer and a first cladding layer provided on the core layer and doped with a first element;
A plurality of modulation electrodes provided on the optical waveguide and spaced apart from each other in the extending direction of the optical waveguide;
The optical waveguide includes a modulation unit positioned below the modulation electrode, and a separation unit positioned between the plurality of modulation electrodes and doped with a second element and having a higher resistance than the modulation unit.
The separation unit includes a first separation unit and a second separation unit,
The concentration of the said 2nd element of the said 2nd isolation | separation part in a depth direction is a photosemiconductor element lower than the said 1st isolation | separation part. In the extending direction of the optical waveguide, the first separation unit is adjacent to the modulation unit,
The optical semiconductor device according to claim 1, wherein the second separation unit is positioned between the plurality of first separation units adjacent to the modulation unit. In the extension direction of the optical waveguide, the second separation unit is adjacent to the modulation unit,
Another second separation unit is located between the plurality of second separation units adjacent to the modulation unit;
The optical semiconductor device according to claim 1, wherein the first separation unit is positioned between a second separation unit adjacent to the modulation unit and the another second separation unit.   The optical semiconductor device according to any one of claims 1 to 3, wherein the second separation portion is longer than the first separation portion in the extension direction of the optical waveguide. The first element is zinc,
The optical semiconductor device according to any one of claims 1 to 4, wherein the second element is at least one of hydrogen, boron, oxygen, sulfur, selenium, iron, chromium and ruthenium. The first element is silicon,
The optical semiconductor device according to any one of claims 1 to 4, wherein the second element is at least one of beryllium, magnesium, zinc and cadmium.   The optical semiconductor device according to any one of claims 1 to 6, wherein the first cladding layer is formed of indium phosphorus.   The optical semiconductor device according to any one of claims 1 to 7, further comprising an undoped second cladding layer provided between the core layer and the first cladding layer. Growing the core layer;
Forming a cladding layer doped with a dopant on the core layer;
Forming a first mask having a plurality of openings on the cladding layer;
Forming a second mask on the first mask and between the plurality of openings;
After the step of forming the second mask, ions are implanted into the cladding layer to form a first separation portion in a portion of the opening of the first mask in the cladding layer, and the first mask is formed on the first mask. Forming a second separation portion in a portion covered and not covered by the second mask;
Forming a modulation electrode on a portion of the cladding layer covered by the second mask after removing the first mask and the second mask.

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