JP2019054568A - Synchronization control method of inverter system, and inverter system - Google Patents

Abstract

To reduce useless overhead and improve synchronization accuracy in a transmission path of small scale data applied to a carrier synchronization system.SOLUTION: A master circuit of a unit 1 that is a master synchronizes with a first carrier synchronization signal. A slave circuit of a unit 2 that is an inverter unit at a slave side of a synchronization code creates serial data including a predictive lag time of receiving the synchronization code and a carrier-period command. The unit 2 outputs serial data including the synchronization code and a second differential time between a second carrier synchronization signal and a first reception timing signal on the basis of the first reception timing signal created at the time of completing the reception of the serial data, the carrier-period command, and the predictive lag time. The master circuit of the unit 1 corrects the predictive lag time on the basis of the second differential time and a first differential time based on a time difference between the first carrier synchronization signal and a second reception timing signal created at the time of completing the reception of the serial data.SELECTED DRAWING: Figure 12

Description

  The present invention relates to a multi-unit operation of an inverter using pulse width modulation, and more particularly to a technique for establishing a common synchronization timing using a serial transmission line.

   “IEEE 1588: 2008” is known as a method (high precision time protocol) for realizing synchronization between two masters / slave units using serial communication. This synchronization method has a reference timer individually, measures transmission time and reception time, and performs measurement by transmitting the time information to each other by communication. Assuming that the delay times of the two-way transmission paths are equal, the delay times of the serial transmission paths are calculated and corrected so that the synchronization timings of the two transmission paths are matched exactly (Patent Document 1).

  Furthermore, EtherCAT (registered trademark) is known as a synchronization method in a large number of devices. This starts transmission of serial communication data from the master, transmits a plurality of slaves in order, returns them at the end slave, and returns them to the master via the plurality of slaves. And the time of bidirectional | two-way (transmission and reception) communication between each slave is measured, and the synchronous timing between many units | sets is matched by transmitting the time information in order.

   In general serial communication such as RS-232C, techniques such as asynchronous communication and asynchronous detection are used.

  In recent years, 8B10B encoding and clock data recovery (CDR) circuits have been used as transmission methods such as USB3 and PCI-Expree.

  The 8B10B code converts 8bit data (1 byte) into 10bit data and transmits it as serial data. Using redundancy increased by 2 bits, byte data (256 types) and about 10 special codes are transmitted. Appropriately select 10-bit data, and for byte data, select “1” or “0” up to 4 bits.

  As a result, since 10-bit data always includes several state changes, it is possible to restore the transmission clock (clock recovery) from serial data. Since the frequency [bps] of the transmission signal is known to each other, the sample timing can be generated by adjusting the sample time (corresponding to the phase of the PLL) by applying PLL control using the data change time as a synchronization reference.

  Asynchronous detection or the like determines the sample timing based on the edge of the start bit, and therefore erroneous packet data may be received if large jitter or noise is mixed.

  On the other hand, when sample timing is generated by PLL control from continuous transmission signals, timing information of many bits is statistically processed, so it is not easily affected by jitter and even if a single noise occurs. The data only becomes abnormal and does not affect the next sample of received data.

  In other words, from the viewpoint of synchronization timing, there is a feature that accurate time detection with statistical processing is possible even on a transmission line with jitter, and it does not drag the influence of noise. Recovery to synchronization can be performed at high speed.

  As for the special code, a code in which “1” or “0” continues for 5 bits can be limited to only the special code (K28.5, com). Then, instead of asynchronous communication (transmitting data intermittently across pauses), cyclic communication (always transmitting data) is used to divide continuous transmission data into equally spaced blocks and insert a COM code between them To do. In this way, if a code in which “1” or “0” is 5 bits in succession is detected, the COM code can be reliably separated, which not only replaces the start bit and stop bit of asynchronous communication, but also has a constant period. Even if COM is erroneously detected due to noise, it can be easily identified as abnormal using the consistency of the time of occurrence. This makes it possible to identify code breaks and block data breaks in units of 10 bits, and data recovery (data recovery) can be performed by separating continuous serial data.

  The method of performing sample timing and data separation using the information embedded in the serial data as described above is called "clock data recovery (CDR)" and has already been studied and put into practical use. .

JP 2007-295647 A

  “IEEE1588: 2008”, “EtherCAT”, and the like employ high-speed communication standards such as Ethernet (registered trademark) network technology 100BASE-TX, which have the following problems. In order to realize a communication speed of 100 Mbps, a dedicated circuit such as PHY (physical layer of communication system circuit) is required. In addition, because the communication protocol is compliant with Ethernet, the bucket configuration is complex and the amount of transmitted data per packet is large, so it cannot be used effectively for a small-scale transmission system with a small amount of data. There is a lot of wasted overhead.

  In view of the above circumstances, an object of the present invention is to reduce wasteful overhead and improve synchronization accuracy in a small-scale data transmission path applied to a carrier synchronization system.

Therefore, one aspect of the present invention is a synchronous control method for an inverter system having at least two or more inverter units,
The master circuit of one inverter unit that is the master is synchronized with the first carrier synchronization signal until the slave circuit of the other inverter unit that is the slave receives and detects the synchronization code indicating the synchronization timing. Serial data including the predicted delay time and the carrier cycle command to the slave circuit of the other inverter unit,
The slave circuit of the other inverter unit generates a first reception timing signal of the synchronization code at a time when the synchronization code of the serial data is normally received or at a time when reception of the entire block data including this is completed, Next, a second carrier synchronization signal is generated based on the first reception timing signal, the carrier cycle command, and the predicted delay time, and a second time based on a timing difference between the first reception timing signal and the second carrier synchronization signal. Measure the difference time, and then, in synchronization with the second carrier synchronization signal, send the serial data including the synchronization code and the second difference time as a return data to the master circuit of the one inverter unit,
The master circuit of the one inverter unit generates the second reception timing signal of the synchronization code at the time when the reception of the synchronization code of the reply data is completed normally or when the entire block data including the reception data is completed, Then, the first difference time based on the time difference between the second reception timing signal and the first carrier synchronization signal is measured, and the prediction delay time is corrected based on the first difference time and the second difference time,
The comparator for carrier generation of the one inverter unit performs pulse width modulation based on the first carrier signal synchronized with the first carrier synchronization signal,
The carrier generating comparator of the other inverter unit performs pulse width modulation based on the second carrier signal synchronized with the second carrier synchronization signal.

  In one aspect of the present invention, the slave circuit of the other inverter unit performs synchronous control to match the second difference time and the predicted delay time, and the master circuit of the one inverter unit Synchronous control for matching the time with the second differential time is performed.

  In one aspect of the present invention, the master circuit of the one inverter unit includes a synchronization control for matching the first difference time and the second difference time, and a synchronization control for matching the second difference time and the predicted delay time. Instead of correcting the predicted delay time based on the first differential time and the second differential time and storing it in the reply data, the second differential time and the predicted delay time are matched. The value of the output signal of the synchronous control to be stored is stored in the reply data, and the slave circuit of the other inverter unit is configured to receive the first reception timing signal, the carrier cycle command, the second difference time, and the predicted delay time. The second carrier synchronization signal is generated on the basis of the value of the output signal of the synchronization control for matching the two.

  In one aspect of the present invention, the master circuit of the one inverter unit includes a first frequency dividing circuit that divides a reference clock, and the first carrier synchronization signal is based on an output signal of the first frequency dividing circuit. And the slave circuit of the other inverter unit has a second divider circuit that divides the reference clock, and based on the output signal of the second divider circuit, the second carrier circuit generates the first carrier signal. A carrier synchronization signal and the second carrier signal are generated.

  One embodiment of the present invention is an inverter system in which the one inverter unit and the other inverter unit are connected in parallel.

  One aspect of the present invention is an inverter system having a plurality of inverter units that function as masters or slaves, the first unit having a master circuit of the inverter unit that functions as the master, and the above that functions as the slave. A second unit having a slave circuit of the inverter unit, wherein the number of the second units is two or more, and the first unit corresponds to the number of the second units. Are provided in parallel.

  One embodiment of the present invention is an inverter system including a plurality of inverter units that function as masters or slaves, the first unit including the inverter unit master circuit that functions as the master, and the master of the first unit. A second unit having the slave circuit connected in series with the circuit and functioning as a slave; and the master circuit connected in series with the slave circuit and functioning as a master; and a master circuit of the second unit And at least a third unit having the above-described slave circuit functioning as a slave.

  According to one aspect of the present invention, in the inverter system, a plurality of the second units are connected in series.

  According to the present invention described above, it is possible to reduce wasteful overhead and improve synchronization accuracy in a small-scale data transmission path applied to a carrier synchronization system.

The application example of the inverter system of this invention. The application example of the inverter system of this invention. The application example of the inverter system of this invention. The signal waveform diagram explaining the various signals regarding the pulse width modulation of this invention. The block diagram of the inverter system of Embodiment 1 of this invention. FIG. 3 is a circuit configuration diagram of a transmission circuit according to the first embodiment. FIG. 3 is a circuit configuration diagram of a receiving circuit according to the first embodiment. FIG. 2 is a circuit configuration diagram of a clock restoration circuit according to the first embodiment. The block diagram of the inverter system of Embodiment 2 of this invention. The block diagram of the inverter system of Embodiment 3 of this invention. The block diagram of the inverter system of Embodiment 4 of this invention. 4 is a time chart of synchronization control according to the first embodiment. 4 is a time chart of synchronization control on the master side and the slave side according to the first embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1]
The inverter system according to the first embodiment is an inverter system including the two inverter units illustrated in FIGS. 1 and 2, and the outputs of the two inverter units are connected in parallel to increase the output current by about twice. It can be configured.

  In the inverter system of the present embodiment, as shown in FIG. 5, one inverter unit 1 (hereinafter referred to as unit 1) functions as a master, and the other inverter unit 2 (hereinafter referred to as unit 2) serves as a slave. Function. Then, the second carrier signal Cry2 of the slave unit 2 follows the first carrier signal Cry1 of the master unit 1, thereby realizing time synchronization of the inverter system of the present embodiment.

  In the waveform diagram of the signal shown in FIG. 4, various signals (symbols) relating to general pulse width modulation (PWM) are defined.

  The triangular wave carrier signal is Cry, and the synchronization signal synchronized with the apex at the carrier cycle (Tc) is Scry. (In other words, Cry and Scry are synchronized.) Here, the synchronization timing is selected at the upper vertex of the triangular wave, but it may be at the lower vertex or at the middle level, and any location may be defined. .

  The principle of generation of the output voltage of pulse width modulation (PWM) is that a digital value of “1/0” is generated by comparing the magnitude of the carrier signal Cry and the voltage command Vref, and an inverter is generated based on this digital value. Drives the internal semiconductor switch and outputs a square-wave voltage pulse (PWM waveform) whose amplitude is the voltage vdc of the DC power supply.

  In the inverter system shown in FIG. 5, the carrier oscillation can be continued even if the synchronization control is stagnated due to a transmission abnormality. That is, one unit 1 mounts the carrier generation unit CryGen1 and continuously generates the synchronization signal Scry1. The other unit 2 is equipped with a carrier generation unit CryGen2, and continuously generates the synchronization signal Scry2.

  In the figure, numbers are added to the end of the symbols so that the master and the slave can be easily distinguished from each other, such as Scry on the master side and Scry2 on the slave side. For the transmission path, the master-to-slave direction is represented as “12”, and the reverse direction is represented as “21”. The voltage command Vref is data having a common value on both the transmission side and the reception side although there is a difference in transmission delay. Therefore, common symbols are given without particular distinction.

  This figure also shows the configuration of full-duplex mutual communication (Cmd_line and Ack_line), and this mutual transmission information is synchronized with the synchronization signal Scry1 by performing synchronization control (PLL1 and PLL2). Feedback control is performed so that the signal Scry2 is synchronized. An example of this operation is the time chart shown in FIGS. The same circuit is applied to the master and slave transmission circuits (Cmd_line and Ack_line) and the delay time (Tdly1 and Tdly2) to detect the synchronization error. Only the contents of transmission data have different functions.

  The common and different components of the units 1 and 2 in FIG. 5 will be described.

  First, aspects of the components common to the units 1 and 2 will be described.

(1) Reference clock: Clk1, Clk2
It is a reference clock signal of a digital circuit, and a crystal oscillator is applied to these, and it is assumed that a frequency error is minute. The reference clock is counted as each time (t1, t2).

  Since the reference clocks (Clk1, Clk2) are also used for transmission waveform samples, a frequency several times higher than the serial transmission frequency [bps] is usually used. Select the timing at which stable data can be sampled. Yes.

(2) Transmission circuit: TX12, TX21
The transmission circuit transmits and receives data between the units. Mutual transmission data is set in the data buffers TxBuf12 and TxBuf21, and the buffer data is sequentially selected and transmitted from the transmission circuit TX12 or the transmission circuit TX21. A configuration example of this transmission unit is shown in FIG.

  Although details of FIG. 6 will be described later, serial transmission signals are generated by performing data selection, blocking, COM code embedding, encoding (8B10B code conversion), serialization, and the like. In particular, transmission of synchronization timing information is started simultaneously with the generation of the synchronization signals Scry1 and Scry2. For example, the synchronization timing information is embedded in the serial data by transmitting a special synchronization code or a data block including it. Data for synchronization timing is transmitted to each other. The master side (unit 1 side) also transmits information such as a carrier cycle command Tc_ref, a transmission delay time prediction time Td_ref, and voltage information Vref (current command if current control). On the other hand, the slave side (unit 2 side) transmits data including time information Tdly2 obtained by measuring the time difference from the slave carrier synchronization timing (Ack_line transmission start timing) Scry2 to the reception timing Trx_12t.

  As described above, although the data contents of transmission and reception are different between the master and the slave, the amount of data to be transmitted and the packet configuration are made equal, and the transmission and reception circuits are made to have the same configuration, so that the transmission and operation delays are made equal.

(3) Serial transmission path: Cmd_line, Ack_line
The serial transmission path is a transmission path for transmitting signals Tx12_data and Tx21_data output from the transmission units of the units 1 and 2 to the other unit, and corresponds to a transmission / reception module for optical transmission, an optical fiber, or the like.

(4) Receiver circuit: RX12, RX21
The receiving circuit is a circuit that receives the data of units 1 and 2, and FIG. 7 shows a detailed example of RX12. The receiving circuits RX12 and RX21 of the unit 1 will be described in detail later, but a shifter (Deserializer) that converts serial data into 10-bit parallel data, a decoder (Decoder) that performs inverse conversion of 8B10B code, and clock components and A CDR circuit (CDR) for restoring data components is provided. This received data is stored in the buffer RxBuf12 by the selector (Sel). This buffer RxBuf12 is read from an external control unit. In addition, since the data for synchronization timing is transmitted by the trigger of Scry2 or Scry1, Srx21 or Srx12 is received at the time when reception of the synchronization code is completed normally on the receiving side or when the entire block data including it is received. The signal is output. In the subsequent stage, using this reception completion signal, the time t is latched and the reception time T_rx necessary for the synchronization control is measured.

  As for the details of the CDR circuit, FIG. 8 shows functional blocks that can explain the operations and operations necessary for the description of the synchronization control. Details thereof will be described later.

(5) Time measuring circuit: T_cry1, T_cry2, T_rx21, T_rx12 latch circuit
The latch circuit for T_cry1 latches the time t1 and outputs the transmission start time T_cry1 by the transmission start signal Scry1 on the master side.

  The latch circuit for T_rx21 latches the time t1 and outputs the reception completion time T_rx21 based on the reception completion signal Srx21 on the master side.

  The latch circuit for T_cry2 latches the time t2 and outputs the transmission start time T_cry2 by the transmission start signal Scry2 on the slave side.

  The latch circuit for T_rx12 latches the time t2 and outputs the reception completion time T_rx12 by the reception completion signal Srx12 on the slave side.

(6) Time difference: Tdly1 and Tdly2 differencer The Tdly1 differencer on the master side sets the difference time from the transmission start time T_cry1 to the reception completion time T_rx21 as Tdly1.

  In the Tdly2 difference unit on the slave side, the difference time from the transmission start time T_cry2 to the reception completion time T_rx12 is set as Tdly2.

  Here, the mode of FIG. 5 calculates the difference time after latching the time of each timing, but the purpose is finally to obtain two delay times Tdly1 and Tdly2. It may be replaced with a delay time measurement counter.

(7) Carrier generation comparator: PWMcomp
As shown in FIG. 4, the carrier generation comparator PWMcomp compares the first carrier signal Cry1 or the second carrier signal Cry2 with the voltage command (Vref, common to master / slave) and outputs an output signal of pulse width modulation PWM. Is generated. Here, the output voltage command from the current control of each unit may be used instead of the common voltage command, but a common voltage command is transmitted as a representative example thereof.

(8) Inverter main circuit: INV1, INV2
Since a signal equivalent to the output voltage of pulse width modulation PWM is output from the carrier generation comparator PWMcomp, the pulse width that actually drives the load in the main circuit INV1, INV2 configured using a power semiconductor switch, etc. Generates PWM voltage for modulation PWM1 and PWM2.

   Next, aspects of the different constituent elements in the units 1 and 2 will be described.

(9) Carrier generator: CryGen1, CryGen2
The carrier generation unit CryGen1 of the master (unit 1) generates a first carrier signal Cry1 having a fixed period set by a carrier cycle command Tc_ref set from the outside, and outputs a timing signal Scry1 synchronized with the first carrier signal Cry1.

  Normally, Clk1 is handled as a digital value, and the first carrier signal Cry1 is counted up and down.

  The carrier generation unit CryGen2 of the slave (unit 2) uses the carrier cycle command Tc_ref2 transmitted from the master (unit 2) as a reference, and the cycle is output by the cycle correction output signal Tcomp2 output from the circuit of the synchronization control unit PLL2. The period obtained by increasing / decreasing is input as a command value, and the second carrier signal Cry2 having the corrected period is generated. Further, the cycle of the second carrier signal Cry2 slightly changes, but the signal Scry2 is output at a timing synchronized with the vertex of the second carrier signal Cry2.

  Although this aspect will be described later, Cry1 is always set to a constant frequency, and carrier synchronization control (fine adjustment of the cycle) is applied only to Cry2 on the slave side.

(10) Synchronization control unit on the slave (unit 2) side: PLL2
The synchronization control unit PLL2 receives the estimated transmission delay time Td_ref transmitted from the master (unit 1) and the time difference Tdly2 between the slave carrier synchronization timing (Ack_line transmission start timing) Tcry2 and the reception timing Trx_12. . When the delay time is longer than expected (Tdly2> Td_ref), a correction value is output so that the phase of the second carrier signal Cry2 advances from the output signal Tcomp2, and conversely, when the delay time is short (Tdly2 <Td_ref), the output signal Tcomp2 A correction value is output so that the phase of the second carrier signal Cry2 is delayed. The feedback loop of the PLL2 correction command and the carrier generation unit CryGen2 period correction finally converges so that signal Tdly2 = signal Td_ref.

  Thereby, on the slave side, it is assumed that the time that is traced back in the past by the predicted transmission delay time Td_ref with respect to the reception time Srx12 is the synchronization timing that should follow, and the second carrier signal and the transmission start timing are synchronized with this.

(11) Master (unit 1) side synchronization controller: PLL1
The master-side synchronization control unit PLL1 does not correct the carrier period like the slave (unit 2), but corrects the predicted transmission delay time Td_ref to detect and correct the transmission delay time shift component. . As described above, the slave side synchronizes the carrier with respect to the reception time Srx12 on the basis of a time that is traced back by the predicted transmission delay time Td_ref, but the predicted delay amount Td_ref is the actual transmission path delay time. On the other hand, if there is an error, it is not in an accurate synchronization state. This appears as an error between the predicted delay amount Td_ref and the master-side delay time Tdly1, and includes a slave synchronization shift time and a component of a predicted shift in transmission delay from the slave. Assuming that the actual two-way transmission delay is equal, if the predicted delay amount Td_ref sent to the slave and the delay time Tdly1 on the master side match, the signal Scry1 and the signal Scry2, that is, the transmission start timing of each other are synchronized . Therefore, in PLL1, the value of Td_ref transmitted to the slave is corrected so as to slowly approach the value of measured value Tdly1. If this converges and finally Tdly1 = Tdly2 = Td_ref is established, carrier synchronization between the signal Scry1 and the signal Scry2 is completed.

  In other words, the synchronization control unit PLL1 detects and corrects variations in transmission delay and changes with time. As described above, there are PLL controls for two different components, master and slave. To make these controls operate stably, set the response characteristic of the PLL control gain high so that PLL2 converges first. In addition, it is necessary to consider that the response of PLL1 is set lower than that, or all responses are set considerably lower.

  In FIG. 5, a circuit configuration having a master function in the unit 1 (a portion surrounded by a one-dot chain line in the unit 1 in FIG. 5) is referred to as a master circuit MST. Similarly, a circuit configuration having a slave function in the unit 2 (a portion surrounded by an alternate long and short dash line in the unit 2 in FIG. 5) is referred to as a slave circuit SLB.

  The operation and operation example of the first embodiment will be described with reference to FIGS.

  FIG. 6, FIG. 7 and FIG. 8 show detailed configuration examples in order to explain the function and operation of each part in FIG. As for the time relationship, FIG. 12 shows the relationship between the transmission timing of the carrier synchronization signal and the transmission / reception data, and FIG. 13 shows the operation from the start of synchronization to the convergence by showing the operation for a longer time. .

   FIG. 6 is a block diagram illustrating an example of functions of the transmission circuit TX12.

Here, an example in which the 8B10B code is applied is shown. The block, Dbus writing transmit data (wr), the reference clock Clk1 signal Scry and transmission circuit is a transmission start timing, and outputs a serial data TX _0. Txbuf (0) to Txbuf (N-1) is a buffer for storing transmission data, and selector Sel is a selector for selecting transmission data in order from Txbuf (0) to Txbuf (N-1). 8B10B in the encoder Encoder Convert 8bit (1byte) data to 10bit serial transmission data using code conversion table.

  Then, the serializer that outputs the final serial signal converts the encoded 10-bit data into serial data while sequentially shifting the data one bit at a time. The operation sequence of these functions is controlled by TxSeq. The trigger signal of the signal Scry and the reference clock Clk1 are input. The selection signal n of the data buffer, the timing Sconv for encoding the selected data, and the input data of the serializer The latch timing Ld, shift operation timing clksft, and the like are output.

   FIG. 7 is a block diagram showing functions of the receiving circuit.

  The serial data Rxi is converted into multi-bit data Dsft by a deserializer such as a shift circuit, and then it is restored to 8 bits (1 byte) by inverse conversion of 8B10B encoding by a code restoration unit Decoder. Then, the selector Sel stores (writes) in the reception buffer RxBuf corresponding to the address of the transmission buffer.

  The CDR circuit restores various timings from serial data, and outputs serial data sampling timing clksft (deserializer shift operation timing) and timing LD that latches and converts Dsft for inverse code conversion (Decoder) Yes. Further, since the received data is updated by the LD signal, it is sequentially written in the buffer RxBuf (n) by the storage buffer control RxDataSel and the selector Sel.

  The CDR circuit also has a function of outputting a synchronization timing signal Srx when detecting synchronization data (a special code for a synchronization signal) embedded in the serial data Rxi. This timing signal Srx is used to latch the value of the timer counter t and measure the reception time t_rx.

  FIG. 8 shows a configuration example of the CDR circuit. The components and functions are as follows. The received serial data Rxi is received by the shifter operating with the reference clock Clk2. Assume that the 1-bit width of the transmission data is 8 samples of the reference clock. The number of samples for one code (10 bits) of 8B10B encoding is (8 × 10) bits, and a shifter sequence capable of storing them is prepared. When the shifter data string matches the pattern of the delimiter (K28.5, com) of the 8B10B code, SyncCodeDetecter outputs a detection signal of Scom_rx. Strictly speaking, the COM detection has a time width of several samples. However, processing such as detecting an intermediate time between rising and falling is performed inside the PLLControl to recognize it as the timing of Scom_rx. Then, sample timing LD of received data is generated by PLL calculation using this Scom_rx as a reference input. This method of recovering the clock (sample timing) using the COM detection and PLL function is less susceptible to jitter than methods based on edge detection of the start bit such as RS232C asynchronous detection. Timing can be obtained. Since this “method of detecting the COM code and generating the timing of Scom_rx” has already been put into practical use, description thereof is omitted here.

  In the example of FIG. 8, the reference clock is divided by a variable division counter ClkDriver that uses a division ratio based on Ndiv from PLLControl to generate a sample timing clksft, which is divided by 10 bits corresponding to 1 code, Further, the frequency is divided by the COM insertion period to generate a Scom_PLL corresponding to a self-oscillation signal of a general PLL configuration. Then, the generation time of Scom_PLL is finely adjusted by correcting the counter width of ClkDriver to Ndiv ± 1 so that the generation times of Scom_rx and Scom_PLL are synchronized. If this PLL is properly converged, a stable sample timing clksft and timing LD that latches 1 code (10 bits) of data can be generated even if some jitter is superimposed on the serial signal waveform. .

   The above is the description of the detailed circuit example for supplementing the first embodiment (FIG. 5).

  The operation of the time charts of FIGS. 12 and 13 will be described using the signals defined above.

  FIG. 12 shows the relationship between the carrier synchronization timing and other signals by limiting the carrier period to a short time width of about twice. FIG. 13 shows the process of starting carrier oscillation and establishing mutual carrier synchronization by showing the operation for a longer time. In the following description, only the convergence operation of the synchronization timing will be described with reference to FIG.

   In FIG. 12, the data from the top two stages and the bottom two stages correspond to the master side signal and the middle part corresponds to the slave side signal. Each signal will be described below.

  (1) Carrier synchronization signal Scry: This is the synchronization timing of the carrier oscillator of the master, and the slave follows this.

  (2) TX12_data: Serial data transmitted from the master using Cmd_line, Sync_code is a special code for identifying the carrier vertex, Tc_ref is the number of clocks indicating the carrier period, and Td_ref is a prediction of the delay time of the transmission path , Vref is operation information shared by the master and the slave, and a three-phase voltage command is assumed here. Although the COM code is omitted in FIG. 12, in order to realize the CDR function, it is inserted before Sync_code or at several data breaks.

  (3) RX12_data: Indicates the received data of the slave. In order to show the delay time of the transmission path, it is shown with a slight delay from Tx12_data.

  (4) Srx12: a timing signal for completion of reception of the synchronization code by the receiving circuit. A 10-bit code is restored from RX12_data, and a Sync_code reception completion signal Srx12 is also generated. The signal Srx12 need not be limited to the completion of reception of Sync_code, but may be the reception time of block data including the signal, or the timing of COM generated before and after that. It is only necessary to detect a fixed position with respect to the transmission cycle. However, an expected delay time Td_ref, which will be described later, is corrected to correspond to the type of timing to be selected.

  (5) Scry2: A synchronization timing signal of the carrier generation unit CryGen2 on the slave side. By establishing synchronization, the signal Scry2 is made to coincide with the timing of the signal Scry1. Since we want to start this signal Scry2 from the synchronized time as much as possible, use the carrier cycle Tc_ref and the predicted delay time Td_ref (contents are the initial setting value Td_ref_ini) of the transmission data from the master and the time T_rx12 of the previous reception timing Srx12 The start time is calculated by the following equation (1).

T_cry2 '= (T_rx12 + Tc_ref) −Td_ref (1)
This is based on the assumption that the next reception time (T_rx12 + Tc_ref) is predicted using the information of time T_rx12, and that the time that is further back by the expected delay time Td_ref for transmission and detection is the synchronization timing. When the signal Scry2 is activated, measurement of the time difference Tdly2 between the signal Scry2 and the signal Srx12 is also started.

  (6) Tx21_data: Serial data returned from the slave side to the master side using Ack_line. When the signal Scry2 is activated, serial transmission is started in synchronization with it. Here, the measured value of the signal Tdly2 is included in the reply data Tx21_data. Here, it is shown that the data is transmitted to the master immediately after the measurement of Tdly2. However, in actuality, it is necessary to consider the processing time, so the data may be transmitted at the next transmission timing. The contents of other transmission data are arbitrary, but the data length is the same as Tx12_data, and Sync_code and COM are embedded in the same way so that the data structure is equivalent (time) Make the process symmetrical).

  (7) Rx21_data: Receive data on the master side. Similar to Tx12_data, this is also drawn with a delay of the transmission path with respect to the transmission source timing.

  (8) Srx21: This is the reception timing of the synchronization code by the receiving circuit on the master side, which is generated when the 10-bit code is restored from RX21_data and Sync_code reception is completed. This makes the detection delay times of the master and slave receiving circuits equal by using the same detection circuit as Srx12. When the slave-side carrier starts and Srx21 starts to be generated, measurement of the time difference Tdly1 between the signal Scry1 and the signal Srx21 is also started on the master side.

   The above is the definition of each signal, time and time difference.

     An example of the operation of the synchronization control units PLL1 and PLL2 based on transmission / reception information will be described with reference to FIG.

<Scry1 (1)>
When CryGen1 starts oscillation, transmission from the master to the slave is started at the timing of the signal Scry (1). This data includes carrier cycle setting Tc_ref and predicted reception delay Td_ref (Td_ref_ini). On the slave side, the timing of the synchronization signal reception timing Srx12 (1) is used as a reference for starting carrier oscillation.

<Scry1 (2)>
On the master side, the signal Scry1 (2) is generated after the lapse of time from the signal Scry1 (1) to the signal Tc_ref, and the next transmission is started. Also on the slave side, the timing corresponding to the signal Scry1 (2) on the master side is predicted from the time of the signal Srx12 (1) by the above equation (1), and carrier oscillation is started from the predicted time. At the same time, a signal Scry2 (2) is output to start transmission from the slave side to the master. Although the delay time Tdly2 is transmitted by this reply data, appropriate dummy data is transmitted before the measurement has started yet.

  As a result, mutual transmission starts, and therefore, delay times Tdly1 (2) and Tdly2 (2) from the start of transmission to the completion of reception of the synchronization code and the like are measured, and synchronization control is performed from these delay time information. At the beginning, the operation of the synchronization control unit PLL1 is not performed, and on the slave side, the block of the synchronization control unit PLL2 works so that the delay time Tdly2 (2) matches the value of the received signal Td_ref so that the carrier period is reduced. Adjust (PLL control).

<Scry1 (3)>
This is a state in which the signal Tdly2 gradually converges to the signal Td_ref by the operation of the slave-side synchronization control unit PLL2. At this time, the difference between the signal Td_ref and the signal Tdly1 (3) includes both the tracking error component of the synchronization control unit PLL2 and the error component of the transmission delay time predicted by the signal Td_ref.

<Scry1 (p)>
If the operation of the slave-side synchronization controller PLL2 converges and the signal Tdly2 matches the signal Td_ref, there may be a slight time shift from the master, but the slave-side carrier cycle is stable and synchronized. It becomes. Then, the difference between the signal Td_ref and the signal Tdly1 (p) in the delay time measurement value on the master side is only the error component of the delay time of the actual transmission path and the predicted Td_ref. Therefore, this time, correction is performed so that the signal Td_ref = signal Tdly1 (p) is established on the master side. Here, on the master side, the carrier frequency is not corrected, but specifically, it is only corrected so that the value of the signal Td_ref approaches the value of the signal Tdly1 (p). Then, it waits for convergence of the synchronization control unit PLL2 on the slave side.

<Scry1 (q)>
If both the master synchronization control unit PLL1 and the slave synchronization control unit PLL2 continue to operate, the signal Tdly1 (q) becomes the signal Td_ref ( converge to q).

<Scry1 (r)>
Eventually, it converges to Td_ref (r) = Tdly1 (q) = Tdly2 (r), synchronization between the master and slave is established, the carrier frequency becomes stable, and at the same time, correction of the delay time of the transmission path is also completed. To do. Thereafter, even if the delay time fluctuates, the synchronization control unit PLL1 operates to change the value of the signal Td_ref and continue the correction, so that accurate carrier synchronization can be maintained. Note that if the master synchronization controller PLL1 and the slave synchronization controller PLL2 operate at the same time, they may become unstable due to interference, so the convergence characteristics of the synchronization controller PLL2 should be increased (response setting increased). The synchronization control unit PLL1 side sets the response setting low so that the signal Tdly1 does not change immediately even if it slightly changes.

  The inverter system according to the first embodiment has the following effects.

  In this embodiment, 8B10B encoding and a CDR circuit are used to improve the clock recovery accuracy on the receiving side, and the carrier synchronization signal is directly used as a transmission start signal. Compared with the two-stage method that oscillates the carrier based on it after establishing only the synchronization timing as in IEEE1588, the source signal of the carrier generation unit is used as the transmission timing, so the timing when passing through a multi-stage circuit Deviations are not mixed, and accurate timing can be measured and accurate synchronization can be realized. In addition, since the amount of calculation processing of transmission data and reception data is small, it is not necessary to transfer a large amount of data at a high speed such as 100 Mbps. 6 and 7 and the CDR circuit of FIG. 8 do not use a special PHY circuit including an analog circuit or the like, and PLL control for extracting a clock from a serial signal is also possible with an FPGA or the like. Only digital arithmetic circuits can be configured.

  Therefore, according to the present embodiment, the communication circuit can be simplified. Without using a special dedicated circuit such as PHY in the physical layer of Ethernet, it is configured to use only a digital communication transmission line with relatively low transmission frequency and a digital logic circuit such as FPGA, and simplify the circuit as much as possible. In addition, the number of parts and mounting area can be reduced. Therefore, a special circuit such as a 100BASE-TX PHY is not required, and it can be constituted by a digital transmission line and an FPGA.

   The transmission data necessary for synchronization may be about several bytes. In addition, detection of abnormal data is facilitated by a special code (such as COM) of the 8B10B code. Furthermore, if data reception timing by CDR is generated, accurate sample timing can be generated while suppressing the influence of jitter. Therefore, the reliability of the transmission signal can be increased as compared with a method in which a start bit is added to simple byte data (binary number) as in the asynchronous method. In other words, the synchronization signal can be accurately detected without adding a special circuit or special data area to prevent erroneous detection, and reliability can be ensured. The amount of transmitted data can be reduced.

  Therefore, according to the present embodiment, it is possible to reduce the amount of transmission data necessary for realizing synchronous control. If the transmission frequency [bps] is kept low, the amount of data that can be transmitted during the synchronization period is reduced. However, according to the present embodiment, the amount of transmission data necessary for establishing synchronization can be reduced.

  In addition, since the inverter unit is likely to generate electromagnetic noise, it is desirable that the serial transmission path between multiple units is less likely to conduct noise such as an optical fiber. Then, unlike RS485 multi-drop wiring, many units cannot be connected by one transmission line, and many serial transmissions between one to one are combined. In this case, it is desirable that the synchronization control be easily configured in multiple stages. Furthermore, even if a transmission error occurs somewhere in this multi-stage connection, even if the synchronization control at both ends of the transmission path is interrupted, the system operation is continued by continuing the oscillation of the synchronization signal for a short time. A configuration is desired in which the synchronization control is resumed when the transmission abnormality is resolved.

  On the other hand, in this embodiment, since all the transmission lines are made to communicate one-to-one, an optical fiber or the like can be applied to the transmission line, and conduction noise can be reduced as compared with the metal wiring. In the case of multi-drop connection or the like, if noise is mixed in the transmission path, it is necessary to discard the received data of all the machines. However, since this embodiment only combines independent one-to-one communication even with a large number of machines, Even if noise is mixed in one place, the synchronization is stopped only during that period, but the synchronization control of other parts can be continued without stopping.

  Furthermore, in this embodiment, since the reference clock (the same frequency as the CDR) of the high-speed transmission circuit is applied to the measurement of the synchronization timing shift time, the synchronization accuracy close to the resolution of this clock can be realized. Although the synchronization accuracy depends on the quality such as the frequency band of the transmission line and the waveform distortion characteristics, according to the present embodiment, the synchronization timing can achieve a high accuracy of about sub-microseconds. Specifically, for example, even when a transmission path of about 20 to 50 Mbps is used, a synchronization accuracy of about 0.1 μs can be obtained.

  In this embodiment, a full-duplex (bidirectional) transmission / reception circuit uses a transmission circuit and a reception circuit having the same configuration. The only difference between the transmission circuit and the reception circuit is the function of finely adjusting the frequencies of the PLL control part and the carrier generation part. Therefore, as in Embodiments 4 and 5 described later, even when three or more inverter units are provided, it is only necessary to duplicate the counter circuit of transmission / reception as necessary, and circuit design is possible even with synchronization of multiple units. Is easy and the delay time can be aligned.

  In order to measure the transmission delay between the master and the slave, it is necessary to assume that the transmission delay times for transmission and reply are equal. Therefore, it is necessary to equalize the delay time in the digital circuit by sharing the master and slave transmission / reception circuits as much as possible (circuit copy). On the other hand, according to the present embodiment, as described above, variations and fluctuations in the delay time of the transmission path can be measured and corrected, and the communication circuit can be shared as much as possible.

  As described above, according to the inverter system of the first embodiment, it is possible to reduce useless overhead and improve synchronization accuracy in a small-scale data transmission path applied to a carrier synchronization system.

[Embodiment 2]
The inverter system of the second embodiment shown in FIG. 9 is the same as the first embodiment except that the function of the slave-side synchronization control unit PLL2 is moved to the master side and further integrated with the function of the master-side synchronization control unit PLL1. It becomes the same mode as the inverter.

  In the first embodiment, the synchronization control unit PLL1 and the synchronization control unit PLL2 are configured by two synchronization controls. However, if the response setting is low, these may be operated simultaneously. The adjustment target of the synchronization control is only the period (phase) correction of the carrier generation unit CryGen2 by Tcom2. Further, considering the stable state in which the two synchronization controls converge and the synchronization is completed, the transmission delay time elapses. Only the correction, ie the signal Td_ref, has changed. From this, the PLL control can be integrated into one. Therefore, the main point of the second embodiment is that the function of the synchronization control unit PLL2 on the slave side is moved to the master side, and further, the function is integrated with the synchronization control unit PLL1 and configured as the synchronization control unit PLL3. This is intended to simplify the circuit configuration on the slave side as much as possible even if the amount of information on the transmission path is slightly increased.

  The output of the synchronization control unit PLL3 (that is, the output of the synchronization control unit PLL2) Tcomp2 is a value corresponding to the output signal Tcomp2 of the synchronization control unit PLL2 of the first embodiment, and this is transmitted to the slave via the transmission line Cmd_line. The value of the output signal Tcomp2 is stored in Vref, etc of the serial data Tx12_data in FIG. On the slave side, the phase of the carrier generation unit CryGen2 is corrected by the value of the received output signal Tcomp2 as in the first embodiment.

  In the first embodiment, the Td_ref value is changed by the synchronization control unit PLL1, but in the configuration of FIG. 9, this signal is included in the block of PLL3 and does not appear outside. However, if the initial value Td_ref_ini of the predicted delay time is used, CryGen2 can be oscillated from an accurate start time, so this initial value Td_ref_ini is transmitted together with an initial setting value such as Tc_ref.

  Since other configurations and functions are the same as those of the first embodiment, description thereof is omitted.

  Only the operation of the synchronization control units PLL1 and PLL2 and the data to be transmitted to each other are changed, and other operations and actions are almost the same as those in the first embodiment. In particular, in the second embodiment, the operation of the synchronization control unit PLL2 is moved to the master side and integrated with the synchronization control unit PLL1 to form the synchronization control unit PLL3. The output signal Tcomp2 of the synchronization control unit PLL2 is transmitted from the synchronization control unit PLL3 to the slave through the transmission path. Further, since the adjustment value of the signal Td_ref becomes an internal variable of the synchronization control unit PLL3, only correction information used only at the start of the slave carrier corresponding to the signal Td_ref (1) shown in FIG. It is transmitted as a signal Td_ref_ini. Other operations are the same as those in the time charts of FIGS.

  According to the present embodiment, the slave-side circuit can be simplified in addition to the effects of the first embodiment by moving the slave-side PLL arithmetic processing to the master side. That is, the configuration on the slave side is simplified by mounting the arithmetic processing function only on the master side.

  When the PLL control is actually applied, it is necessary to perform processing such as calculation of an initial value and multiplication by a gain, abnormality determination, and the like, and complicated processing needs to be realized by software such as a CPU. When a CPU is mounted, the mounting area and the number of components such as peripheral circuits and software write terminals increase.

   In addition, there are cases where it is not desired to mount a complicated circuit such as a numerical operation on the slave side. The system that needs to establish synchronization is not limited to unit parallel only, and the slave side may implement only the function of detecting the voltage and current of the remote part. When detecting a current or voltage component including a pulse width tuning ripple, a method of detecting at a timing synchronized with the pulse width tuning is applied so that the harmonic component of the carrier frequency can be easily removed. In this case, a simple configuration such as a sensor, an AD converter, and an FPGA circuit is desirable. In other words, we do not want to implement complex PLL control calculations on the slave side, but want to execute PLL control calculations only on the master side. Instead, information such as time correction required for carrier synchronization correction should be transmitted to the slave side each time it is added to communication data.

   On the other hand, this embodiment can be realized with only the FPGA if it is about a counter or a simple sequence circuit. If arithmetic processing is implemented only on the master side, the slave has a simple configuration. The circuit scale can be greatly reduced. Also, even if the PLL processing is shifted to the master side, the amount of computation of the CPU does not increase so much and the amount of data to be transmitted and received does not increase so much. It is done.

[Embodiment 3]
Embodiments 1 and 2 adopt a serial transmission and carrier synchronization method between a master and a slave. Since the carrier generation units CryGen1 and CryGen2 are configured to count up and down the reference clocks Clk1 and Clk2, the resolution of the pulse width modulation PWM pattern is set to the same high resolution as the communication reference clock.

  However, since disturbances such as switching delay are mixed in the main circuit in the subsequent stage, even if the time resolution of the pulse width modulation pattern is increased, the effect cannot be obtained practically. Even if the resolution of the pattern is coarse, the cross current suppression effect can be obtained if the same pulse width modulation pattern is generated between the parallel units by accurately synchronizing the carriers.

  Therefore, the inverter system of the third embodiment uses a high-frequency reference clock for circuits that require high time resolution, such as communication and synchronization control, and a low-frequency reference for circuits that are sufficient for other low operation clocks. Operate with clock. This is for the purpose of suppressing power supply current and heat generation (temperature rise) in a digital circuit such as an FPGA, and this function is realized in the third embodiment.

  The inverter system of the third embodiment illustrated in FIG. 10 is a modification of the inverter system of the second embodiment, but the same modification can be applied to the inverter system of the first embodiment.

  The difference between the inverter system of the third embodiment and the aspect of the second embodiment will be described. The master unit 1 divides the reference clock Clk1 by the first frequency dividing circuit ClkDivider1 to generate a low-frequency reference clock Clk1L. This is used as a reference clock for the carrier generation unit CryGen1 and the PWMcomp circuit. Therefore, the first carrier synchronization signal Scry1 and the first carrier signal Cry1 output from the carrier generation unit CryGen1 are generated based on the low-frequency reference clock Clk1L. As a result, the operating frequency and current consumption of the carrier generation unit CryGen1 and the PWMcomp circuit can be suppressed.

  Similarly, the slave-side unit 2 divides the reference clock Clk2 by the second frequency dividing circuit ClkDivider2 to generate a low-frequency reference clock Clk2L, which is used as a reference clock for the carrier generation unit CryGen2 and the PWMcomp circuit. Therefore, the second carrier synchronization signal Scry2 and the second carrier signal Cry2 output from the carrier generation unit CryGen2 are generated based on the low-frequency reference clock Clk2L. However, the second frequency dividing circuit ClkDivider2 on the slave side has a variable frequency dividing function. If the output signal Tcomp2 is a command to advance the synchronization time, the second divider circuit ClkDivider2 reduces the division ratio to generate a short cycle clock to advance the generation time of the synchronization timing, and the output signal Tcomp2 is synchronized in phase. If it is a command to delay the time, the second frequency dividing circuit ClkDivider2 increases the frequency division ratio to generate a clock with a long cycle, thereby delaying the generation time of the synchronization timing. That is, by adjusting the frequency division ratio indirectly, the carrier synchronization timing can finally be adjusted. As a result, the carrier generating circuit can be operated with a low-frequency reference clock, and the carrier synchronization accuracy can be controlled while maintaining the time resolution of the high frequency reference clock.

  In the first and second embodiments, the period is finely adjusted by increasing or decreasing the amplitude of the carrier counter. On the other hand, the third embodiment uses a low clock obtained by dividing the reference clock of the communication circuit as the reference clock of the carrier generation unit, and correction (increase / decrease) of the carrier period is indirectly performed by this divided clock. Control is performed by finely adjusting the upper limit count value intermittently.

  In the first and second embodiments, when the carrier cycle is changed, the counter upper limit value is adjusted to ± 1 clock. Also in the third embodiment, as an operation equivalent to the first and second embodiments, when the carrier counter reaches the upper limit, the upper limit value of the clock division counter is increased or decreased to adjust the clock cycle. Thereby, carrier synchronous operation equivalent to the first and second embodiments is realized. Furthermore, the reference frequency of a PWM generation circuit using a carrier signal can be lowered.

  In the FPGA or the like, current consumption increases due to a reference clock or an internal logic change, and logic operation at a frequency as low as possible is desirable. In order to reduce the power consumption and heat generation amount of the FPGA, the transmission circuit is operated with a reference clock that is close to the highest of the FPGA. May be used. Therefore, when the frequency of the reference clock of the transmission circuit and the reference clock of the carrier signal circuit are different (for example, when Fclk_srl = 160 MHz of the transmission circuit is divided by 4 so that the pulse width modulation PWM clock Fclk_pwm = 40 MHz) ), High synchronization accuracy is desired.

  On the other hand, in the third embodiment, the transmission circuit and the measurement circuit part for PLL employ a high-speed reference clock to increase the measurement resolution of the transmission frequency and time, and even with a low-speed clock frequency (time resolution). The part related to the generation of a good pulse width modulated PWM applies a low frequency reference clock. Therefore, the consumption current of the FPGA can be reduced, and the longer the clock cycle, the greater the allowable amount of propagation delay of the logic circuit. Therefore, a larger amount of complicated operations can be executed within one clock. Further, since the synchronization control unit of the present embodiment performs measurement and phase correction using a high-speed reference clock, the same synchronization accuracy as in the first and second embodiments can be maintained. In particular, if a crystal oscillator is applied to the reference clocks Clk1 and Clk2, the master and slave reference clocks have a very small frequency error.

[Embodiment 4]
The inverter system of the fourth embodiment is a combination of any of the units of the first to third embodiments. As an aspect of the combination, the same signal is transmitted from two master circuits and synchronized with two individually connected slaves (embodiment 4), and data and synchronization signals are cascaded. A mode of serial connection for transmission (embodiment 5 described later) is included.

  In the inverter system according to the fourth embodiment shown in FIG. 3, the parallel connection method corresponds to establishing synchronization from unit 1 to unit 2 and unit 3.

  When this mode is expressed as a master / slave transmission path, transmission between the master circuit MST1b of the first unit 11 and the slave circuit SLB2 of the second unit 12, as in the inverter system shown in FIG. This corresponds to communication between the master circuit MST1a of one unit 11 and the slave circuit SLB3 of the second unit 13. The master circuit MST in any unit 1 of the first to third embodiments is applied to the master circuits MST1a and MST1b, and the slave circuit SLB in any unit 2 of the first to third embodiments is applied to the slave circuits SLB2 and SLB3. Is done.

  The two master circuits MST1b and master circuit MST1a have a parallel connection configuration in which the same input signals Tc_ref, Scry, Vref, and the like are input. However, the CDR, the synchronization control unit PLL1 and the synchronization control unit PLL2 (or only PLL3) in each slave circuit operate individually to establish synchronization.

  As described above, the inverter system of the fourth embodiment can connect the aspects of the first to third embodiments in parallel and give the same command, but can establish synchronization independently.

[Embodiment 5]
The serial connection of the present embodiment corresponds to a configuration in which synchronization is established from unit 1 to unit 3 in the inverter system of FIG. 3 and then synchronization between unit 3 and unit 4 is established. By the synchronization control configured in two stages of this aspect, the second carrier signals of both unit 3 and unit 4 are finally synchronized with the first carrier signal of unit 1.

  When this mode is expressed as a transmission path between the master and the slave, the transmission between the master circuit MST1a of the first unit 11 and the slave circuit SLB3 of the second unit 13 shown in FIG. This corresponds to a portion in which the master circuit MST3 and the slave circuit SLB4 of the third unit 14 are connected in series. First, synchronization on the first stage side (between the master circuit MST1a and slave circuit SLB3) is established, and then synchronization on the subsequent stage (MST3-SLB4) is established. The master circuit MST in any unit 1 of Embodiments 1 to 3 is applied to the master circuits MST1a and MST3, and the slave circuit SLB in any unit 2 of Embodiments 1 to 3 is applied to the slave circuits SLB3 and SLB4. Is done. In this mode, the two stages may converge at the same time, but there is a difference in the response gains of the PLL control in the first stage and the latter stage, so that synchronization control interference and instability occur between multiple transmission lines connected in series. It is necessary to consider not to occur.

  The signals necessary for the synchronization of the second stage of the serial connection are the set value of the carrier cycle of the signal Tc_ref received by the slave circuit SLB3, the voltage command, and the synchronization signal Scry synchronized with the unit 1, The received information may be transferred as it is.

  As mentioned above, the inverter system of Embodiment 5 connects the aspect of Examples 1-3 in series in multiple stages, and establishes synchronization in order from the master side.

  Further, the inverter system of the present invention is not limited to the aspect of the inverter system of FIG. 11, and an inverter system in which a plurality of second units 13 are connected in series between the first unit 11 and the third unit 14. It can also be set as this aspect.

  In addition, this invention is not limited to the aspect of above-mentioned Embodiment 1-5, It can implement in a various aspect within the claim of this invention.

1, 2 ... Unit (Inverter unit)
11 ... first unit 12, 13 ... second unit 14 ... third unit
MST, MST1a, MST1b, MST3 ... Master circuit
SLB, SLB2, SLB3, SLB4 ... Slave circuit
TX12, TX21 ... Transmission circuit
RX12, RX21 ... Receiver circuit
PWMcomp ... Comparator for carrier generation
CryGen1, CryGen2 ... Carrier generator
CDR ... clock data recovery circuit
CryGen1, CryGen2 ... Carrier generator
PLL1 ... Synchronous control unit on the master (unit 1) side
PLL2 ... Slave (unit 2) side synchronization control unit

Claims (8)

A method for synchronous control of an inverter system having at least two inverter units,
The master circuit of one inverter unit that is the master is
A serial including a synchronization code indicating the synchronization timing in synchronization with the first carrier synchronization signal, a predicted delay time until the slave circuit of the other inverter unit as a slave receives and detects the synchronization code, and a carrier cycle command Send the data to the slave circuit of the other inverter unit,
The slave circuit of the other inverter unit is
At the time when the reception of the synchronization code of the serial data is normally completed or the time when the entire block data including the reception is completed, the first reception timing signal of the synchronization code is generated,
Next, a second carrier synchronization signal is generated based on the first reception timing signal, the carrier cycle command, and the predicted delay time,
Measuring a second differential time based on a time difference between the timing of the first reception timing signal and the second carrier synchronization signal;
Next, in synchronization with the second carrier synchronization signal, the serial data including the synchronization code and the second differential time is transmitted as reply data to the master circuit of the one inverter unit,
The master circuit of the one inverter unit is
Generate a second reception timing signal of the synchronization code at the time when the reception of the synchronization code of the reply data is completed normally or at the time when the entire block data including the reception is completed,
Then, the first difference time based on the time difference between the second reception timing signal and the first carrier synchronization signal is measured, and the prediction delay time is corrected based on the first difference time and the second difference time,
The carrier generating comparator of the one inverter unit is
Perform pulse width modulation based on the first carrier signal synchronized with the first carrier synchronization signal,
The carrier generating comparator of the other inverter unit is
Performing pulse width modulation based on the second carrier signal synchronized with the second carrier synchronization signal

A method for synchronous control of an inverter system. The slave circuit of the other inverter unit performs synchronous control to match the second differential time and the predicted delay time,
2. The synchronous control method for an inverter system according to claim 1, wherein the master circuit of the one inverter unit performs synchronous control for matching the first differential time with the second differential time. The master circuit of the one inverter unit performs synchronization control for matching the first difference time and the second difference time, and synchronization control for matching the second difference time and the predicted delay time, and the first difference Instead of correcting the predicted delay time based on the time and the second differential time and storing it in the reply data, an output signal of a synchronous control for matching the second differential time with the predicted delay time Store the value in the reply data,
The slave circuit of the other inverter unit includes the second carrier based on the first reception timing signal, the carrier cycle command, the second differential time, and the value of the synchronous control output signal for matching the predicted delay time. The synchronization control method for an inverter system according to claim 1, wherein the synchronization signal is generated. The master circuit of the one inverter unit has a first divider circuit that divides the reference clock, and based on the output signal of the first divider circuit, the first carrier synchronization signal and the first carrier signal are Generate
The slave circuit of the other inverter unit has a second divider circuit that divides the reference clock, and based on the output signal of the second divider circuit, the second carrier synchronization signal and the second carrier signal The synchronous control method for an inverter system according to any one of claims 1 to 3, wherein:   An inverter system in which one inverter unit according to any one of claims 1 to 4 and the other inverter unit are connected in parallel. An inverter system having a plurality of inverter units that function as masters or slaves,
A first unit having a master circuit of the inverter unit according to any one of claims 1 to 4, which functions as the master;
A second unit having a slave circuit of the inverter unit according to any one of claims 1 to 4 functioning as the slave,
The number of the second unit is two or more,
The inverter system according to claim 1, wherein the first unit includes the master circuit in parallel corresponding to the number of the second units. An inverter system having a plurality of inverter units that function as masters or slaves,
A first unit having a master circuit of the inverter unit according to any one of claims 1 to 4, which functions as the master;
5. The slave circuit according to claim 1, wherein the slave circuit is connected in series with the master circuit of the first unit and functions as a master connected in series with the slave circuit. To a second unit having the master circuit according to any one of 4 to 4,
An inverter system comprising at least a third unit having a slave circuit according to any one of claims 1 to 4 which functions as a slave connected in series with a master circuit of the second unit. .   The inverter system according to claim 7, wherein a plurality of the second units are connected in series.

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