JP2019054300A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high withstand voltage of a gate insulating film. A semiconductor device of an embodiment is a SiC substrate, a SiC layer provided on the SiC substrate and having a trench extending from a surface toward the SiC substrate, and a first conductive type provided in the SiC layer. A first SiC region, a second conductive type second SiC region provided between the first SiC region and the SiC substrate, and a first conductive region provided between the second SiC region and the SiC substrate. A third SiC region of the mold, a gate insulating film provided on the side surface and the bottom surface of the trench, and a gate electrode provided on the gate insulating film are provided, and a second SiC region and a third SiC region are provided. The boundary with and is in contact with the side surface of the trench, and the boundary becomes larger as the distance from the surface of the SiC layer increases as the distance from the trench increases. The distance between the SiC regions is greater than half the distance between the third SiC region and the first SiC region. [Selection diagram] Fig. 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  SiC (silicon carbide) is expected as a material for next-generation semiconductor devices. Compared with Si (silicon), SiC has excellent physical properties such as a band gap of 3 times, a breakdown electric field strength of about 10 times, and a thermal conductivity of about 3 times. By utilizing this characteristic, it is possible to realize a semiconductor device capable of operating at high temperature with low loss.

  However, for example, when a MIS (Metal Insulator Semiconductor) structure is formed using SiC, since the breakdown voltage of SiC is high, the breakdown voltage of the gate insulating film is lower than that of the MIS structure using Si (silicon). There is a risk of lowering the withstand voltage. In particular, when the MIS structure is formed in the trench in order to increase the integration degree of the device, there is a problem that the breakdown voltage of the gate insulating film is lowered due to electric field concentration at the bottom of the trench.

JP 2013-214658 A

  An object of the present invention is to provide a semiconductor device in which a gate insulating film has a high breakdown voltage.

  The semiconductor device of the embodiment includes a SiC substrate, a SiC layer provided on the SiC substrate, having a first trench having a side surface and a bottom surface on the surface side, and a first conductive provided in the SiC layer. A first SiC region of a mold, a second SiC region of a second conductivity type provided between the first SiC region and the SiC substrate in the SiC layer, and the second SiC region in the SiC layer. A first conductivity type third SiC region provided between the two SiC regions and the SiC substrate, a gate insulating film provided on the side surface and the bottom surface of the first trench, A gate electrode in which the gate insulating film is provided between the first SiC region, the second SiC region, and the third SiC region, and the second SiC region and the third SiC region. The boundary with the SiC region of the first trench The boundary is provided on a side of the side surface, and the boundary includes a first region, and the first region increases as the distance from the surface of the SiC layer increases from the first trench. The distance from the side surface of the trench to the end of the first region on the first trench side is not less than 0 μm and not more than 0.3 μm, and includes the end on the bottom surface side of the gate electrode on the surface A first distance along the side surface between a parallel virtual plane and the second SiC region is a first distance along the side surface between the third SiC region and the first SiC region. Greater than half of the distance of 2.

1 is a schematic cross-sectional view illustrating an example of a semiconductor device according to a first embodiment. FIG. 3 is a schematic cross-sectional view showing another example of the semiconductor device of the first embodiment. In the manufacturing method of the semiconductor device of a 1st embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 1st embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 1st embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 1st embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. In the manufacturing method of the semiconductor device of a 1st embodiment, a schematic cross section showing a semiconductor device in the middle of manufacture. FIG. 6 is a schematic cross-sectional view illustrating an example of a semiconductor device of a comparative form. FIG. 3 is a schematic cross-sectional view showing another example of the semiconductor device of the first embodiment. Explanatory drawing of the effect | action and effect of the semiconductor device of 1st Embodiment. Explanatory drawing of the effect | action and effect of the semiconductor device of 1st Embodiment. Explanatory drawing of the effect | action and effect of the semiconductor device of 1st Embodiment. FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device of a comparative form. Explanatory drawing of the effect | action and effect of the semiconductor device of 2nd Embodiment. FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to a third embodiment. FIG. 6 is a schematic cross-sectional view showing a semiconductor device according to a fourth embodiment. FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a fifth embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and description of members once described is omitted as appropriate.

In the following description, the notations n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ represent the relative level of impurity concentration in each conductivity type. That is, n ⁺ indicates that the n-type impurity concentration is relatively higher than n, and n ⁻ indicates that the n-type impurity concentration is relatively lower than n. Further, p ⁺ indicates that the p-type impurity concentration is relatively higher than p, and p ⁻ indicates that the p-type impurity concentration is relatively lower than p. In some cases, n ⁺ type and n ⁻ type are simply referred to as n type, p ⁺ type and p ⁻ type as simply p type.

(First embodiment)
The semiconductor device of the present embodiment includes a SiC substrate, a SiC layer provided on the SiC substrate, extending from the surface toward the SiC substrate, having a trench having a side surface and a bottom surface, and a first layer provided in the SiC layer. A first SiC region of one conductivity type, a second SiC region of a second conductivity type provided between the first SiC region and the SiC substrate in the SiC layer, and a second SiC in the SiC layer A third SiC region of a first conductivity type provided between the region and the SiC substrate, a first SiC region, a second SiC region, and a third SiC region provided on a side surface and a bottom surface of the trench; A gate insulating film in contact with the SiC region, and a gate electrode provided on the gate insulating film. The boundary between the second SiC region and the third SiC region is in contact with the side surface of the trench, and the boundary increases as the distance from the surface of the SiC layer increases away from the trench. And a first region having a distance from a side surface of the trench of 0 μm or more and 0.3 μm or less.

  FIG. 1 is a schematic cross-sectional view showing an example of the configuration of a MISFET that is a semiconductor device of the present embodiment.

  The MISFET 100 is an n-type MISFET using electrons as carriers. The MISFET 100 is a vertical device. The MISFET 100 is a trench gate type MISFET in which a gate insulating film and a gate electrode are provided in a trench.

  The MISFET 100 includes an SiC substrate 10, an SiC layer 12, a drift region (third SiC region) 14, an interface 15, a first region 15a, a second region 15b, a third region 15c, and a fourth region 15d, p. Well region (second SiC region) 16, source region (first SiC region) 18, p well contact region (fourth SiC region) 20, gate insulating film (insulating film) 28, gate electrode 30, interlayer insulation A film 32, a source electrode (electrode) 34, a drain electrode 36, and a trench 50 are provided.

  In this specification, with respect to the surface of the SiC substrate 10 or the like, the upper surface in FIG.

The MISFET 100 includes an n ⁺ type SiC substrate 10. The SiC substrate 10 is a 4H—SiC SiC substrate containing, for example, N (nitrogen) as an n-type impurity. The impurity concentration of the n-type impurity is, for example, 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. The SiC substrate 10 functions as a drain region of the MISFET 100.

  The surface of the SiC substrate 10 is, for example, a surface that is inclined at 0 ° or more and 10 ° or less with respect to the (0001) plane (silicon surface). The back surface of the SiC substrate 10 is, for example, a surface that is inclined at 0 degree or more and 10 degrees or less with respect to the (000-1) plane (carbon plane).

SiC layer 12 is provided on SiC substrate 10. The SiC layer 12 includes, for example, N (nitrogen) as an n-type impurity. The concentration of the n-type impurity in the SiC layer 12 is, for example, 1 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. The SiC layer 12 is, for example, a SiC epitaxial growth layer formed on the SiC substrate 10 by epitaxial growth.

  The surface of SiC layer 12 is also a plane inclined at 0 ° or more and 10 ° or less with respect to the silicon surface. The film thickness of the SiC layer 12 is not less than 5 μm and not more than 150 μm, for example.

  SiC layer 12 has a trench 50 extending from the surface of SiC layer 12 toward SiC substrate 10 and having a side surface and a bottom surface.

  The drift region (third SiC region) 14, the p well region (second SiC region) 16, the source region (first SiC region) 18, and the p well contact region (fourth SiC region) 20 are composed of SiC layers. 12 is provided.

N ⁻ type drift region 14 is provided between p well region 16 and SiC substrate 10. The drift region 14 includes, for example, N (nitrogen) as an n-type impurity. The concentration of the n-type impurity in the drift region 14 is, for example, 1 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less.

  The p-type p well region 16 is provided between the source region 18 and the SiC substrate 10. The p well region 16 functions as a channel region of the MISFET 100.

The p well region 16 includes, for example, Al (aluminum) as a p-type impurity. The concentration of the p-type impurity in the p-well region 16 is, for example, 5 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. The depth of the p well region 16 is, for example, not less than 0.6 μm and not more than 1.2 μm.

The n ⁺ type source region 18 is provided in the p well region 16. A part of source region 18 is in contact with the surface of SiC layer 12.

The source region 18 includes, for example, N (nitrogen) as an n-type impurity. The concentration of the n-type impurity in the source region 18 is, for example, 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ cm ⁻³ or less. The depth of the source region 18 is shallower than the depth of the p well region 16. The depth of the source region 18 is, for example, about 0.3 μm.

The p ⁺ type p well contact region 20 is provided in the p well region 16. The p-well contact region 20 is provided on the side of the source region 18.

The p-well contact region 20 contains, for example, Al (aluminum) as a p-type impurity. The p-type impurity concentration in the p-well contact region 20 is higher than the p-type impurity concentration in the p-well region 16. For example, it is 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. The depth of the p well contact region 20 is shallower than the depth of the p well region 16 and is, for example, about 0.3 μm.

  The trench 50 is provided in the SiC layer 12. The side surface of the trench 50 is, for example, an m-plane or an a-plane. The depth of the trench 50 is shallower than the maximum depth of the p-well region 16.

The boundary 15 between the p-well region 16 and the drift region 14 is in contact with the side surface of the trench 50.
The boundary 15 between the p-well region 16 and the drift region 14 includes a first region 15a, a second region 15b, a third region 15c, and a fourth region 15d.

  The distance of first region 15 a from the surface of SiC layer 12 increases as the distance from trench 50 increases. The first region 15a has a first inclination angle (θ in FIG. 1). The first tilt angle (θ in FIG. 1) is greater than 0 degrees. The distance (d in FIG. 1) between the first region 15a and the side surface of the trench 50 is not less than 0 μm and not more than 0.3 μm.

  Second region 15 b is substantially parallel to the surface of SiC layer 12. The second region 15 b is provided between the first region 15 a and the trench 50. The second region 15 b is in contact with the side surface of the trench 50.

  Third region 15 c is substantially parallel to the surface of SiC layer 12. A first region 15 a is provided between the third region 15 c and the trench 50.

  Fourth region 15 d is substantially perpendicular to the surface of SiC layer 12. A first region 15 a is provided between the fourth region 15 d and the trench 50. The fourth region 15d is provided between the third region 15c and the first region 15a.

  Note that the shape of the boundary 15 between the p-well region 16 and the drift region 14 can be observed by, for example, scanning capacitance microscopy (Scanning Capacitance Microscopy).

  The gate insulating film 28 is provided on the side surface and the bottom surface of the trench 50. At least a part of the gate insulating film 28 is in contact with the source region 18, the p-well region 16, and the drift region 14. Gate insulating film 28 is provided between SiC layer 12 and gate electrode 30.

  For example, an oxide film is applied to the gate insulating film 28. As the gate insulating film 28, for example, a silicon oxide film, a silicon oxynitride film, or a high-k insulating film can be applied.

  The gate electrode 30 is provided on the gate insulating film 28. For example, doped polysilicon or the like can be applied to the gate electrode 30.

  The interlayer insulating film 32 is provided on the gate electrode 30. The interlayer insulating film 32 is formed of, for example, a silicon oxide film.

  Source electrode 34 is provided on SiC layer 12. Source electrode 34 is electrically connected to source region 18 and p well contact region 20. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16.

  The source electrode 34 is a conductive material. The source electrode 34 is, for example, metal or metal silicide. The source electrode 34 includes, for example, a stacked structure of a nickel silicide layer and an aluminum (Al) layer on the nickel silicide layer.

  Drain electrode 36 is provided on the side opposite to SiC layer 12 of SiC substrate 10, that is, on the back surface side. Drain electrode 36 is electrically connected to SiC substrate 10.

  The drain electrode 36 is a conductive material. The drain electrode 36 is, for example, metal or metal silicide. The drain electrode 36 includes, for example, a stacked structure of a nickel silicide layer and a gold (Au) layer on the nickel silicide layer.

  In this embodiment, the n-type impurity is preferably N (nitrogen) or P (phosphorus), for example, but As (arsenic) or Sb (antimony) can also be applied. For example, Al (aluminum) is preferable as the p-type impurity, but B (boron), Ga (gallium), In (indium), or the like can also be applied.

  FIG. 2 is a schematic cross-sectional view showing another example of the configuration of the MISFET that is the semiconductor device of the present embodiment.

  The MISFET 101 shows a case where the distance between the first region 15a and the side surface of the trench 50 is 0 μm. That is, in the MISFET 101, there is no second region 15b, and the first region 15a is in direct contact with the side surface of the trench 50.

  Next, an example of a method for manufacturing the semiconductor device of this embodiment will be described. 3 to 7 are schematic cross-sectional views showing the semiconductor device being manufactured in the manufacturing method of the semiconductor device of the present embodiment.

First, an n ⁺ type SiC substrate 10 having a silicon surface on the front surface and a carbon surface on the back surface is prepared. Next, an n ⁻ type SiC layer 12 is formed on the surface of the SiC substrate 10 by an epitaxial growth method (FIG. 3).

  Next, a photoresist 60 is formed in a predetermined region by a known photolithography method (FIG. 4).

  Next, the photoresist 60 is thermally shrunk by heat treatment. The side surface of the photoresist 60 becomes tapered due to thermal shrinkage.

  Then, p-type impurities are ion-implanted into the SiC layer 12 using the photoresist 60 as a mask (FIG. 5). The acceleration energy of the p-type impurity is set so that the p-type impurity passes through the photoresist 60 and reaches the SiC layer 12.

  A p-well region 16 is formed by ion implantation of p-type impurities. A drift region 14 is formed between the p-well region 16 and the SiC substrate 10. The p-type impurity is, for example, aluminum (Al).

  The shape of the photoresist 60 is reflected in the shape of the boundary 15 between the p-well region 16 and the drift region 14. A boundary 15 having a first region 15a, a second region 15b, a third region 15c, and a fourth region 15d is formed.

  Next, a trench 50 is formed in the SiC layer 12 (FIG. 6). The trench 50 is formed by a known lithography method and dry etching method.

  Next, the gate insulating film 28 is formed on the side surface and the bottom surface of the trench 50. The gate insulating film 28 is formed, for example, by thermally oxidizing the side surface and the bottom surface of the trench 50. The gate insulating film 28 can also be formed by the LPCVD method. Next, a gate electrode 30 is formed on the gate insulating film 28 by a known method (FIG. 7). The gate electrode 30 is, for example, doped polysilicon formed by LPCVD.

  Thereafter, the interlayer insulating film 32, the source electrode 34, and the drain electrode 36 are formed by a known process, and the MISFET 100 of this embodiment shown in FIG. 1 is manufactured.

  Hereinafter, the operation and effect of the semiconductor device of this embodiment will be described.

  In the trench gate type MISFET, there is a problem that the breakdown voltage of the gate insulating film is lowered due to the electric field concentration at the bottom of the trench in the OFF state of the MISFET. In particular, due to the electric field concentration at the corners of the trench, the breakdown voltage of the gate insulating film is lowered and the breakdown voltage of the MISFET is lowered.

  FIG. 8 is a schematic cross-sectional view showing an example of the configuration of the MISFET of the comparative form. In order to alleviate the electric field concentration at the bottom of the trench, a part of the p-well region 16 is deepened. In the off state of the MISFET 800, a depletion layer extends from the deep p-well region 16 toward the trench 50, so that the electric field at the corner of the trench is relaxed. Therefore, the breakdown voltage of the gate insulating film is improved.

  On the other hand, in the on state of MISFET 800, since deep p well region 16 exists, the resistance of drift region 14a between p well region 16 and the side surface of trench 50 increases. Therefore, a new problem that the on-resistance of the MISFET 800 increases occurs.

  FIG. 9 is a schematic cross-sectional view showing another example of the configuration of the MISFET of this embodiment. FIG. 9 has the same configuration as the MISFET 101 of FIG.

  By changing the channel length (Lch in FIG. 9) of the MISFET 101, the relationship between the maximum electric field in the gate insulating film and the on-resistance was obtained by simulation. The channel length was 0.1 μm, 0.2 μm, and 0.3 μm. When the channel length was changed, the boundary 15 was moved up and down while maintaining the shape. The first inclination angle θ was fixed at 45 degrees.

  Similarly, for the comparative MISFET 800, the channel length (Lch in FIG. 8) was changed, and the relationship between the maximum electric field in the gate insulating film and the on-resistance was obtained by simulation. The channel length was 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, and 0.6 μm.

  FIG. 10 is an explanatory diagram of operations and effects of the semiconductor device of this embodiment. FIG. 10 is a diagram showing the relationship between the maximum electric field in the gate insulating film 28 and the on-resistance. As can be seen from FIG. 10, the maximum electric field and the on-resistance in the gate insulating film 28 are in a trade-off relationship in both the embodiment and the comparative embodiment.

  When the channel length (Lch) of the MISFETs 101 and 800 is shortened, the electric field relaxation effect at the corner of the trench 50 by the depletion layer extending from the p well region 16 is reduced, and the maximum electric field in the gate insulating film 28 is increased. Therefore, the breakdown voltage of the gate insulating film 28 is reduced.

  Further, when the channel length (Lch) of the MISFETs 101 and 800 is shortened, the channel resistance is decreased and the on-resistance is decreased.

  As is clear from FIG. 10, in the case of the embodiment, the trade-off relationship between the maximum electric field in the gate insulating film 28 and the on-resistance is improved as compared with the case of the comparative embodiment. In the case of the embodiment, (1) since the on-current flows along the inclined first region 15a as shown by the white arrow in FIG. 2) Since the depletion layer extends from the inclined first region 15a toward the trench 50, it is considered that the electric field relaxation effect at the corner of the trench 50 is greater than that in the comparative example. Therefore, when compared with the same on-resistance, in the case of the MISFET 101 of the embodiment, the maximum electric field in the gate insulating film 28 is relaxed, and the breakdown voltage of the gate insulating film 28 is improved.

  FIG. 11 is an explanatory diagram of operations and effects of the semiconductor device of this embodiment. In the structure of the MISFET 100 shown in FIG. 1, the result of obtaining the relationship between the distance (d in FIG. 1) between the first region 15 a and the side surface of the trench 50 and the breakdown voltage of the MISFET 100 by simulation is shown.

  The breakdown voltage shown on the vertical axis is the breakdown voltage between the source electrode 34 and the drain electrode 36. In the simulation, the channel length (Lch in FIG. 1) is fixed to 0.1 μm.

  As shown in FIG. 11, when the distance between the first region 15a and the side surface of the trench 50 exceeds 0.3 μm, the withstand voltage is drastically decreased. If it is 0.2 μm or less, a high breakdown voltage can be stably maintained.

  The MISFET of this embodiment has the inclined first region 15a. Since the first region 15a is inclined, the extension of the depletion layer from the drift region 14 toward the channel region is suppressed in the OFF state of the MISFET. Therefore, even when the channel length is shortened, punch-through of the MISFET is suppressed and the breakdown voltage of the MISFET is improved.

  However, if the distance between the first region 15a and the side surface of the trench 50 is too long, the effect of suppressing the growth of the depletion layer from the drift region 14 toward the channel region is reduced. Therefore, the breakdown voltage of the MISFET is lowered.

  From the result shown in FIG. 11, the distance between the first region 15a and the side surface of the trench 50 (d in FIG. 1) is preferably 0 μm or more and 0.3 μm or less from the viewpoint of improving the breakdown voltage of the MISFET. . The distance (d in FIG. 1) between the first region 15a and the side surface of the trench 50 is more preferably 0.2 μm or less, and further preferably 0.1 μm or less.

  FIG. 12 is a diagram illustrating the operation and effect of the semiconductor device of this embodiment. The relationship between the maximum electric field in the gate insulating film and the on-resistance was obtained by simulation by changing the first inclination angle θ of the first region 15a of the MISFET 101 shown in FIG. The voltage applied between the source electrode 34 and the drain electrode 36 was 1200V.

In order to reduce the on-resistance as compared with the planar type MISFET, the on-resistance is desirably ² mΩcm ² or less. Further, when the gate insulating film 28 is a silicon oxide film, the maximum electric field is desirably 3 MV / cm or less from the viewpoint of ensuring the withstand voltage of the gate insulating film 28. Therefore, it is desirable that the first inclination angle θ is not less than 15 degrees and not more than 60 degrees.

  From the viewpoint of improving the breakdown voltage of the gate insulating film 28, it is desirable that the film thickness of the gate insulating film 28 on the bottom surface of the trench 50 is larger than the film thickness of the gate insulating film 28 on the side surface of the trench 50.

  According to the MISFET of this embodiment, the trade-off relationship between the maximum electric field in the gate insulating film 28 and the on-resistance is improved. Therefore, the breakdown voltage of the gate insulating film 28 is increased. In addition, punch-through in the channel region is suppressed, and the breakdown voltage between the source and drain is increased. Therefore, a MISFET having a high breakdown voltage can be realized.

(Second Embodiment)
The semiconductor device of this embodiment is the same as that of the first embodiment except that the boundary between the second SiC region and the third SiC region does not include the fourth region. Therefore, description of the contents overlapping with those of the first embodiment is omitted.

  FIG. 13 is a schematic cross-sectional view showing the configuration of a MISFET that is a semiconductor device of this embodiment. The MISFET 200 is a trench gate type MOSFET.

  The boundary 15 between the p-well region 16 and the drift region 14 is in contact with the side surface of the trench 50. A boundary 15 between the p-well region 16 and the drift region 14 includes a first region 15a and a third region 15c.

  The first region 15 a is in contact with the side surface of the trench 50. Further, the boundary 15 between the p-well region 16 and the drift region 14 does not include a bent portion having an angle of 90 degrees or less.

  FIG. 14 is a schematic cross-sectional view showing an example of the configuration of a MISFET of a comparative form. In order to alleviate the electric field concentration at the bottom of the trench 50, a part of the p-well region 16 is deepened. In the off state of the MISFET 900, the depletion layer extends from the deep p well region 16 to the trench 50 side, so that the electric field at the corner of the trench 50 is relaxed. Therefore, the breakdown voltage of the gate insulating film 28 is improved.

  The relationship between the maximum electric field in the gate insulating film 28 and the on-resistance was obtained by simulation by changing the channel length (Lch in FIG. 13) of the MISFET 200. The channel length was 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, and 0.6 μm. The first inclination angle θ was fixed at 45 degrees.

  Similarly, for the comparative MISFET 900, the channel length (Lch in FIG. 14) was changed, and the relationship between the maximum electric field in the gate insulating film and the on-resistance was obtained by simulation. The channel length was 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, and 0.6 μm.

  FIG. 15 is an explanatory diagram of operations and effects of the semiconductor device of this embodiment. FIG. 15 is a diagram showing the relationship between the maximum electric field in the gate insulating film and the on-resistance.

  As is apparent from FIG. 15, in the case of the embodiment, the trade-off relationship between the maximum electric field in the gate insulating film 28 and the on-resistance is improved as compared with the case of the comparative embodiment. Therefore, when compared with the same on-resistance, in the case of the MISFET 200 of the embodiment, the maximum electric field in the gate insulating film 28 is relaxed, and the breakdown voltage of the gate insulating film 28 is improved.

  According to the MISFET of this embodiment, the breakdown voltage of the gate insulating film 28 and the breakdown voltage between the source and the drain are increased as in the MISFET of the first embodiment. Further, since the boundary 15 does not include a bent portion having an angle of 90 degrees or less, electric field concentration at the boundary 15 in the OFF state of the MISFET is suppressed, and dielectric breakdown at the boundary 15 is suppressed. Therefore, a MISFET having a higher breakdown voltage can be realized.

(Third embodiment)
The semiconductor device of this embodiment is provided with a second conductivity type fifth SiC region provided in the SiC layer between the bottom surface of the trench and the third SiC region, and in contact with the bottom surface. This is the same as the first embodiment. Therefore, description of the contents overlapping with those of the first embodiment is omitted.

  FIG. 16 is a schematic cross-sectional view showing the configuration of a MISFET that is a semiconductor device of the present embodiment. The MISFET 300 is a trench gate type MOSFET.

  The MISFET 300 includes a p-type electric field relaxation region 40 in the SiC layer 12. The electric field relaxation region 40 is provided between the bottom surface of the trench 50 and the drift region 14. The electric field relaxation region 40 has a function of relaxing electric field concentration at the bottom of the trench 50 when the MISFET 300 is in an off state.

The electric field relaxation region 40 includes, for example, Al (aluminum) as a p-type impurity. The concentration of the p-type impurity in the electric field relaxation region 40 is, for example, 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less.

  According to the MISFET of this embodiment, the breakdown voltage of the gate insulating film 28 and the breakdown voltage between the source and the drain are increased as in the MISFET of the first embodiment. In addition, by providing the electric field relaxation region 40, the breakdown voltage of the gate insulating film 28 at the bottom of the trench 50 is further improved.

(Fourth embodiment)
The semiconductor device of this embodiment is the same as that of the first embodiment except that the source electrode 34 is provided in the trench. Therefore, description of the contents overlapping with those of the first embodiment is omitted.

  FIG. 17 is a schematic cross-sectional view showing a configuration of a MISFET which is a semiconductor device of the present embodiment. The MISFET 400 is a trench gate type MOSFET.

In the MISFET 400, the source electrode 34 is provided in the trench 55 provided in the SiC layer 12. A p ⁺ type p-well contact region 20 is provided at the bottom or side surface of the trench 55.

  According to the MISFET of this embodiment, the breakdown voltage of the gate insulating film 28 and the breakdown voltage between the source and the drain are increased as in the MISFET of the first embodiment. Further, by providing the source electrode 34 in the trench 55, the contact structure can be miniaturized.

  In addition, providing the source electrode 34 in the trench 55 facilitates formation of the deep p-well region 16. That is, after forming the trench 55 in the SiC layer 12, ions are implanted into the bottom of the trench 55 to form the p well region 16, thereby facilitating the formation of the deep p well region 16.

(Fifth embodiment)
The semiconductor device of the present embodiment is the same as that of the first embodiment except that it is not an MISFET but an IGBT (Insulated Gate Bipolar Transistor). Therefore, description of the contents overlapping with those of the first embodiment is omitted.

  FIG. 18 is a schematic cross-sectional view showing the configuration of the IGBT that is the semiconductor device of the present embodiment. The IGBT 500 is a trench gate type IGBT in which a gate insulating film and a gate electrode are provided in a trench.

  The IGBT 500 includes an SiC substrate 110, an SiC layer 12, a drift region (third SiC region) 14, an interface 15, a first region 15a, a second region 15b, a third region 15c, and a fourth region 15d, p. Base region (second SiC region) 116, emitter region (first SiC region) 118, p base contact region (fourth SiC region) 120, gate insulating film (insulating film) 28, gate electrode 30, interlayer insulation A film 32, an emitter electrode (electrode) 134, a collector electrode 136, and a trench 50 are provided.

IGBT 500 includes a p ⁺ type SiC substrate 110. The SiC substrate 110 is a 4H—SiC SiC substrate containing, for example, Al (aluminum) as a p-type impurity. The impurity concentration of the p-type impurity is, for example, 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. SiC substrate 110 functions as a collector region of IGBT 500.

  The surface of the SiC substrate 110 is, for example, a surface that is inclined at 0 ° or more and 10 ° or less with respect to the (0001) plane (silicon surface). The back surface of SiC substrate 110 is, for example, a surface that is inclined at 0 degree or more and 10 degrees or less with respect to the (000-1) plane (carbon plane).

SiC layer 12 is provided on SiC substrate 110. The SiC layer 12 includes, for example, N (nitrogen) as an n-type impurity. The concentration of the n-type impurity in the SiC layer 12 is, for example, 1 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. The SiC layer 12 is, for example, an SiC epitaxial growth layer formed on the SiC substrate 110 by epitaxial growth.

  The surface of SiC layer 12 is also a plane inclined at 0 ° or more and 10 ° or less with respect to the silicon surface. The film thickness of the SiC layer 12 is not less than 5 μm and not more than 150 μm, for example.

  The drift region (third SiC region) 14, the p base region (second SiC region) 116, the emitter region (first SiC region) 118, and the p base contact region (fourth SiC region) 120 are SiC layers. 12 is provided.

N ⁻ type drift region 14 is provided between p base region 116 and SiC substrate 110. The drift region 14 includes, for example, N (nitrogen) as an n-type impurity. The concentration of the n-type impurity in the drift region 14 is, for example, 1 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less.

  The p-type p base region 116 is provided between the emitter region 118 and the SiC substrate 110. The p base region 116 functions as a channel region of the IGBT 500.

The p base region 116 includes, for example, Al (aluminum) as a p-type impurity. The concentration of the p-type impurity in the p base region 116 is, for example, 5 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. The depth of the p base region 116 is, for example, not less than 0.6 μm and not more than 1.2 μm.

The n ⁺ -type emitter region 118 is provided in the p base region 116. A part of emitter region 118 is in contact with the surface of SiC layer 12.

The emitter region 118 includes, for example, N (nitrogen) as an n-type impurity. The n-type impurity concentration in the emitter region 118 is, for example, 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ cm ⁻³ or less. The depth of the emitter region 118 is shallower than the depth of the p base region 116. The depth of the emitter region 118 is, for example, about 0.3 μm.

The p ⁺ -type p base contact region 120 is provided in the p base region 116. The p base contact region 120 is provided on the side of the emitter region 118.

The p base contact region 120 contains, for example, Al (aluminum) as a p-type impurity. The p-type impurity concentration in the p base contact region 120 is higher than the p-type impurity concentration in the p base region 116. For example, it is 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. The depth of the p base contact region 120 is shallower than the depth of the p base region 116, for example, about 0.3 μm.

  The trench 50 is provided in the SiC layer 12. The side surface of the trench 50 is, for example, an m-plane or an a-plane. The depth of the trench 50 is shallower than the maximum depth of the p base region 116.

The boundary 15 between the p base region 116 and the drift region 14 is in contact with the side surface of the trench 50.
The boundary 15 between the p base region 116 and the drift region 14 includes a first region 15a, a second region 15b, a third region 15c, and a fourth region 15d.

  The distance of first region 15a from the surface of SiC layer 12 increases as the distance from trench 50 increases. The first region 15a has a first inclination angle (θ in FIG. 1). The distance (d in FIG. 1) between the first region 15a and the side surface of the trench 50 is not less than 0 μm and not more than 0.3 μm.

  Second region 15 b is substantially parallel to the surface of SiC layer 12. The second region 15 b is provided between the first region 15 a and the trench 50. The second region 15 b is in contact with the side surface of the trench 50.

  Third region 15 c is substantially parallel to the surface of SiC layer 12. A first region 15 a is provided between the third region 15 c and the trench 50.

  Fourth region 15 d is substantially perpendicular to the surface of SiC layer 12. A first region 15 a is provided between the fourth region 15 d and the trench 50. The fourth region 15d is provided between the third region 15c and the first region 15a.

  Note that the shape of the boundary 15 between the p base region 116 and the drift region 14 can be observed by, for example, scanning capacitance microscopy.

  The gate insulating film 28 is provided on the side surface and the bottom surface of the trench 50. At least a part of the gate insulating film 28 is in contact with the emitter region 118, the p base region 116, and the drift region 14. Gate insulating film 28 is provided between SiC layer 12 and gate electrode 30.

  For example, an oxide film is applied to the gate insulating film 28. As the gate insulating film 28, for example, a silicon oxide film, a silicon oxynitride film, or a high-k insulating film can be applied.

  The gate electrode 30 is provided on the gate insulating film 28. For example, doped polysilicon or the like can be applied to the gate electrode 30.

  The interlayer insulating film 32 is provided on the gate electrode 30. The interlayer insulating film 32 is formed of, for example, a silicon oxide film.

  Emitter electrode 134 is provided on SiC layer 12. Emitter electrode 134 is electrically connected to emitter region 118 and p base contact region 120. The emitter electrode 134 also functions as a p base electrode that applies a potential to the p base region 116.

  The emitter electrode 134 is a conductive material. The emitter electrode 134 is, for example, metal or metal silicide. The emitter electrode 134 includes, for example, a stacked structure of a nickel silicide layer and an aluminum (Al) layer on the nickel silicide layer.

  Collector electrode 136 is provided on the opposite side to SiC layer 12 of SiC substrate 110, that is, on the back side. Collector electrode 136 is electrically connected to SiC substrate 110.

  The collector electrode 136 is a conductive material. The collector electrode 136 is, for example, metal or metal silicide. The collector electrode 136 includes, for example, a stacked structure of a nickel silicide layer and a gold (Au) layer on the nickel silicide layer.

  In this embodiment, the n-type impurity is preferably N (nitrogen) or P (phosphorus), for example, but As (arsenic) or Sb (antimony) can also be applied. For example, Al (aluminum) is preferable as the p-type impurity, but B (boron), Ga (gallium), In (indium), or the like can also be applied.

  According to the IGBT of this embodiment, like the MISFET of the first embodiment, the trade-off relationship between the maximum electric field in the gate insulating film 28 and the on-resistance is improved. Therefore, the breakdown voltage of the gate insulating film 28 is increased. In addition, punch-through in the channel region is suppressed, and the breakdown voltage between the emitter and collector is increased. Therefore, an IGBT having a high breakdown voltage can be realized.

  In the first to fifth embodiments, the characteristics of the device having the structure in which the n-type and the p-type are interchanged can also be improved.

  As described above, in the embodiment, the case where 4H—SiC is used as the crystal structure of silicon carbide has been described as an example. However, the present invention can also be applied to silicon carbide having other crystal structures such as 6H—SiC and 3C—SiC. is there.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. For example, a component in one embodiment may be replaced or changed with a component in another embodiment. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 SiC substrate 12 SiC layer 14 Drift region (third SiC region)
15 boundary 15a first region 15b second region 15c third region 15d fourth region 16 p-well region (second SiC region)
18 Source region (first SiC region)
20 p-well contact region (fourth SiC region)
28 Gate insulating film 30 Gate electrode
34 Source electrode 36 Drain electrode 40 Electric field relaxation region (fifth SiC region)
50 trench 55 trench 100 MISFET (semiconductor device)
101 MISFET (semiconductor device)
110 SiC substrate 114 Emitter region (third SiC region)
116 p base region (second SiC region)
118 Collector region (first SiC region)
120 p base contact region (fourth SiC region)
134 Emitter electrode 136 Collector electrode 200 MISFET (semiconductor device)
300 MISFET (semiconductor device)
400 MISFET (semiconductor device)
500 IGBT (semiconductor device)

Claims (22)

A SiC substrate;
A SiC layer provided on the SiC substrate and having a first trench having a side surface and a bottom surface on a surface side;
A first conductivity type first SiC region provided in the SiC layer;
A second SiC region of a second conductivity type provided between the first SiC region and the SiC substrate in the SiC layer;
A third SiC region of a first conductivity type provided between the second SiC region and the SiC substrate in the SiC layer;
A gate insulating film provided on the side surface and the bottom surface of the first trench;
A gate electrode provided with the gate insulating film between the first SiC region, the second SiC region, and the third SiC region;
The boundary between the second SiC region and the third SiC region is on the side of the side surface of the first trench,
The boundary includes a first region, and the first region increases as the distance from the surface of the SiC layer increases from the first trench, and from the side surface of the first trench. The distance to the end of the region 1 on the first trench side is 0 μm or more and 0.3 μm or less;
The first distance along the side surface between the virtual plane including the end on the bottom surface side of the gate electrode and parallel to the surface and the second SiC region is the third SiC region. A semiconductor device that is greater than one-half of a second distance along the side surface between the first SiC region.   The semiconductor device according to claim 1, wherein the first region is in contact with the side surface of the first trench.   The boundary includes a second region substantially parallel to the surface of the SiC layer, the second region is provided between the first region and the first trench, and the second region 2. The semiconductor device according to claim 1, wherein is in contact with the side surface of the first trench.   4. The semiconductor device according to claim 1, wherein the first region has a first inclination angle with respect to the surface, and the first inclination angle is not less than 15 degrees and not more than 70 degrees. .   4. The semiconductor device according to claim 1, wherein the first region has a first inclination angle with respect to the surface, and the first inclination angle is not less than 15 degrees and not more than 60 degrees. .   The boundary is provided with a third region substantially parallel to the surface, and the first region is provided between the third region and the first trench. A semiconductor device according to item.   The boundary is provided with a fourth region that is substantially perpendicular to the surface, and the first region is provided between the fourth region and the first trench. A semiconductor device according to item.   The semiconductor device according to claim 1, wherein the gate insulating film is an oxide film.   The film thickness of the gate insulating film on the bottom surface of the first trench is larger than the film thickness of the gate insulating film on the side surface of the first trench. The semiconductor device according to one item.   A second conductivity type fourth SiC region provided in a side of the first SiC region in the SiC layer and having a second conductivity type impurity concentration higher than that of the second SiC region; The semiconductor device according to claim 1.   2. The fifth SiC region of a second conductivity type provided between the bottom surface of the first trench and the third SiC region in the SiC layer and in contact with the bottom surface. Item 11. The semiconductor device according to any one of Items 10. A first electrode;
A second electrode in which the SiC layer and the SiC substrate are provided between the first electrode and the first electrode;
The SiC layer has a second trench on the surface side;
10. The first to ninth embodiments, wherein the first SiC region is provided between the first trench and the second trench, and the first electrode is provided in the second trench. 11. The semiconductor device according to any one of 11 above.   The second conductivity type second layer is provided in the SiC layer between the bottom surface of the second trench and the third SiC region, and has a second impurity concentration higher than that of the second SiC region. The semiconductor device according to claim 12, further comprising four SiC regions.   The semiconductor device according to any one of claims 1 to 13, wherein an inner angle of the boundary portion of the second SiC region is 90 degrees or more.   The semiconductor device according to claim 1, wherein the boundary does not include a bent portion having an angle of 90 degrees or less.   The semiconductor device according to claim 1, wherein the first conductivity type is an n-type.   The semiconductor device according to claim 1, wherein the SiC substrate is of a first conductivity type.   The semiconductor device according to claim 1, wherein the SiC substrate is of a second conductivity type. A SiC substrate;
A SiC layer provided on the SiC substrate and having a first trench having a side surface and a bottom surface on a surface side;
A first conductivity type first SiC region provided in the SiC layer;
A second SiC region of a second conductivity type provided between the first SiC region and the SiC substrate in the SiC layer;
A third SiC region of a first conductivity type provided between the second SiC region and the SiC substrate in the SiC layer;
A gate insulating film provided on the side surface and the bottom surface of the first trench;
A gate electrode provided with the gate insulating film between the first SiC region, the second SiC region, and the third SiC region;
The boundary between the second SiC region and the third SiC region is on the side of the side surface of the first trench,
The boundary comprises a first region, the first region having a first point near the first trench and a second point far from the first trench, and the second point The distance between the surface of the SiC layer is greater than the distance between the first point and the surface of the SiC layer, and the distance from the side surface of the first trench The distance to the end portion on the first trench side is 0 μm or more and 0.3 μm or less,
The first distance along the side surface between the virtual plane including the end on the bottom surface side of the gate electrode and parallel to the surface and the second SiC region is the third SiC region. A semiconductor device that is greater than one-half of a second distance along the side surface between the first SiC region. A SiC substrate;
A SiC layer provided on the SiC substrate and having a first trench having a side surface and a bottom surface on a surface side;
A first conductivity type first SiC region provided in the SiC layer;
A second SiC region of a second conductivity type provided between the first SiC region and the SiC substrate in the SiC layer;
A third SiC region of a first conductivity type provided between the second SiC region and the SiC substrate in the SiC layer;
A gate insulating film provided on the side surface and the bottom surface of the first trench;
A gate electrode provided with the gate insulating film between the first SiC region, the second SiC region, and the third SiC region;
The boundary between the second SiC region and the third SiC region is on the side of the side surface of the first trench,
The boundary comprises a first region, the first region having a first point near the first trench and a second point far from the first trench, and the second point The distance between the back surface of the SiC substrate is smaller than the distance between the first point and the back surface of the SiC substrate, and the first region of the first region from the side surface of the first trench. The distance to the end of one trench side is not less than 0 μm and not more than 0.3 μm,
The first distance along the side surface between the virtual plane including the end on the bottom surface side of the gate electrode and parallel to the surface and the second SiC region is the third SiC region. A semiconductor device that is greater than one-half of a second distance along the side surface between the first SiC region.   The semiconductor device according to claim 1, wherein the second distance is not less than 0.1 μm and not more than 0.6 μm. A first electrode provided on the surface side of the SiC layer;
A second electrode in which the SiC layer and the SiC substrate are provided between the first electrode and the first electrode;
A second conductivity type fourth SiC region provided in a side of the first SiC region in the SiC layer and having a second conductivity type impurity concentration higher than that of the second SiC region; ,
A minimum distance between the second electrode and the first trench is greater than a minimum distance between the second electrode and the second SiC region;
A third distance in a direction perpendicular to the surface between the first electrode and the boundary between the second SiC region and the fourth SiC region is a second distance between the second SiC region and the fourth SiC region. The first distance is smaller than a fourth distance in a direction perpendicular to the surface between the boundary with the SiC region and the boundary between the second SiC region and the third SiC region. 21. The semiconductor device according to claim 20.

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