JP2019046956A - Circuit board and manufacturing method thereof - Google Patents

Abstract

To provide a heat dissipation substrate and a manufacturing method thereof capable of reducing defects caused by heat generation of electronic components mounted on the heat dissipation substrate.SOLUTION: A circuit board 10 according to the present invention includes a core substrate 11 and buildup layers 20, 20 stacked on an F surface 11F and an S surface 11S of the core substrate 11. In a first buildup layer 20A on the F surface 11F side, a first cavity 30A opened to the outer surface is formed, and in a second buildup 20B layer on the S surface 11S side, a second cavity 30B opened to the outer surface is formed, and the first cavity 30A and the second cavity 30B are arranged at positions not overlapping in the thickness direction of the circuit board 10, and are connected by a heat radiation path (conductor layers 12F and S and connecting conductor 15) made of metal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a circuit board in which a buildup layer is stacked on a core board and a method of manufacturing the same.

  Conventionally, as a circuit board of this type, it is known that a heat dissipation block housed in a cavity is connected to an electronic component (for example, a semiconductor element) mounted on the circuit board via a via conductor or the like. (See, for example, Patent Document 1).

JP-A-2013-135168 (paragraphs [0028] to [0030], FIG. 3 (B))

  However, in the above-described conventional circuit board, if the heat generation of the electronic components mounted on the circuit board is accumulated, warpage or the like of the circuit board due to the heat is considered to occur and problems such as disconnection occur.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit board capable of suppressing a defect due to heat generation of an electronic component mounted on the circuit board and a method of manufacturing the same.

  A circuit board according to the present invention made to achieve the above object comprises a core substrate, and a buildup layer laminated on the first surface and the second surface of the core substrate. Then, a first cavity opened to the outer surface is formed in the buildup layer on the first surface side, and a second cavity opened to the outer surface is formed in the buildup layer on the second surface side, The first cavity and the second cavity are disposed at positions not overlapping in the thickness direction of the circuit board, and are in communication with each other via a metal heat radiation path.

  Further, in the method of manufacturing a circuit board according to the present invention, a buildup layer is laminated on the first surface and the second surface which are both the front and back surfaces of the core substrate, and the buildup layer on the first surface side Forming a first cavity opening on the outer surface thereof, and building the second surface at a position not overlapping the first cavity and the thickness direction of the circuit board with the buildup layer on the second surface side. Forming a second cavity open to the outer surface of the up layer; and forming a heat dissipation path of metal connecting the first cavity and the second cavity.

Side cross-sectional view of the circuit board according to the first embodiment of the present invention Side sectional view showing the manufacturing process of the circuit board Side sectional view showing the manufacturing process of the circuit board Side sectional view showing the manufacturing process of the circuit board Side sectional view showing the manufacturing process of the circuit board Side sectional view showing the manufacturing process of the circuit board Side sectional view showing the manufacturing process of the circuit board Side sectional view showing the manufacturing process of the circuit board Side sectional view showing an example of use of a circuit board Side cross-sectional view of the circuit board of the modified example Side cross-sectional view of the circuit board of the modified example

First Embodiment
Hereinafter, a first embodiment of the present invention will be described based on FIGS. 1 to 9. As shown in FIG. 1, the circuit board 10 of the present embodiment has a structure in which buildup layers 20 and 20 are laminated on both the front and back sides of the core substrate 11 and further solder resist layers 26 and 26 are laminated. ing. Hereinafter, the surface on one end side of the core substrate 11 in the thickness direction is referred to as F surface 11 F (corresponding to the “first surface” in the present invention), and the surface on the other end is S surface 11 S (in the present invention) It corresponds to "the second side."

  In the core substrate 11, conductor layers 12 are formed on both the front and back sides of the insulating base material 11K. When the conductor layers 12 are distinguished from each other, the conductor layer 12 on the F surface 11F side of the core substrate 11 is referred to as a first conductor layer 12F, and the conductor layer 12 on the S surface 11S side of the core substrate 11 is a second conductor It is called layer 12S. The insulating base material 11K is a prepreg obtained by impregnating a woven fabric of reinforcing fibers (for example, glass cloth) with a resin. The thickness of the insulating base 11K is, for example, about 50 to 150 [μm].

  Further, a plurality of conductive through holes 11H are formed in the insulating base material 11K. The conductive through hole 11H has an intermediate narrow shape. Plating is filled in each conductive through hole 11H to form a plurality of connection conductors 15, and the connection conductors 15 connect the first conductor layer 12F and the second conductor layer 12S.

  The buildup layer 20 is composed of a plurality of insulating layers 21 and a plurality of conductor layers 22 stacked alternately. When the buildup layers 20 and 20 are to be distinguished, the buildup layer 20 stacked on the F surface 11F side of the core substrate 11 is referred to as a first buildup layer 20A, and on the S surface 11S side of the core substrate 11 The buildup layer 20 being stacked is referred to as a second buildup layer 20B.

  The conductor layers 12 and 22 are mainly made of copper plating and have a thickness of about 10 to 25 μm. The conductor layers 12 and 22 are connected by the via conductor 17 penetrating the insulating layer 21 or the connection conductor 15 penetrating the insulating base 11K. The via conductor 17 and the connection conductor 15 are configured by plating. The via conductor 17 and the connection conductor 15 correspond to the “connection conductor” in the present invention.

  The insulating layer 21 and the solder resist layer 26 are resin layers not containing reinforcing fibers. The thickness of the insulating layer 21 is, for example, about 15 to 30 μm, and the thickness of the solder resist layer 26 is, for example, about 18 to 35 μm.

  Further, in the solder resist layer 26, a plurality of openings 26H and 26H for exposing a part of the conductor layer 22 are formed. The portions of the conductor layer 22 exposed from the openings 26 H, 26 H constitute pads 29, 29.

  As shown in FIG. 1, the first buildup layer 20A is provided with a first cavity 30A. The first cavity 30A penetrates the solder-resist layer 26 and the first buildup layer 20A. Then, the first conductor layer 12F is exposed from the bottom surface of the first cavity 30A.

  In addition, a second cavity 30B is provided in the second buildup layer 20B. The second cavity 30B penetrates the solder-resist layer 26 and the second buildup layer 20B. And the 2nd conductor layer 12S is exposed from the bottom of the 2nd cavity 30B.

  The first conductor layer 12F and the second conductor layer 12S have a circuit pattern 23 and a plain pattern 24 that constitutes the bottom of the first cavity 30A or the second cavity 30B. The plane-like pattern 24 of the first conductor layer 12F is formed to have substantially the same size or a slightly larger size as the bottom surface of the first cavity 30A. The plane pattern 24 of the second conductor layer 12S is formed so as to overlap in the thickness direction of the circuit board 10 in any of the first cavity 30A and the second cavity 30B.

  The first conductor layer 12F constituting the bottom surface of the first cavity 30A and the second conductor layer 12S constituting the bottom surface of the second cavity 30B are connected by a plurality of connection conductors 15. Specifically, the plurality of connection conductors 15 extend toward the lower side of the first cavity 30A, and are in the form of a plane of the second conductor layer 12S disposed at a position overlapping the first cavity 30A in the thickness direction of the circuit board 10. It is connected with the pattern 24. The plane pattern 24 of the first conductor layer 12F, the plane pattern 24 of the second conductor layer 12S, and the connection conductor 15 connecting them correspond to the "heat radiation path" in the present invention.

The circuit board 10 of the present embodiment is manufactured as follows.
(1) As shown in FIG. 2A, a copper-clad laminate 11Z is prepared in which copper foils 11C are laminated on both sides of the insulating base 11K.

  (2) As shown in FIG. 2B, a plurality of conductive through holes 11H for forming the connection conductor 15 (see FIG. 1) are formed in the copper-clad laminate 11Z. Specifically, for example, a CO 2 laser is irradiated from both sides of the copper-clad laminate 11Z to form the conductive through holes 11H for the connection conductor 15.

  (3) The electroless plating process is performed, and an electroless plating film (not shown) is formed on the copper foil 11C and the inner surface of the conductive through hole 11H. Next, as shown in FIG. 2C, a plating resist 33 having a predetermined pattern is formed on the electroless plating film on the copper foil 11C.

  (4) As shown in FIG. 2D, the electrolytic plating process is performed, and the electrolytic plating is filled in the conductive through holes 11H to form the connection conductor 15, and the copper-clad laminate 11Z is formed. Electrolytic plating films 34 and 34 are formed on a portion of the formed electroless plating film (not shown) exposed from the plating resist 33.

  (5) The plating resist 33 is peeled off, and the electroless plating film (not shown) below the plating resist 33 and the copper foil 11C are removed, and as shown in FIG. Conductor layers 12 and 12 each having a circuit pattern 23 and a plain pattern 24 are formed on both sides of the insulating substrate 11K by the plating film 34, the electroless plating film and the copper foil 11C. Thus, the core substrate 11 is obtained. A part of connection conductors 15 of the plurality of connection conductors 15 connect the circuit patterns 23 with each other, and another part of the connection conductors 15 connect the plain patterns 24 with each other.

  (6) As shown in FIG. 3B, the peelable masks 45, 45 are stacked on the plain pattern 24 of the first conductor layer 12F and the second conductor layer 12S. The peelable masks 45, 45 are stacked only on the portion where the first cavity 30A and the second cavity 30B are formed.

  (7) As shown in FIG. 3C, the insulating layers 21 and 21 are stacked on the F surface 11F and the S surface 11S of the core substrate 11.

  (8) As shown in FIG. 3D, the insulating layers 21 and 21 are irradiated with a CO 2 laser, and a plurality of via holes 21H penetrating the insulating layers 21 and 21 are formed.

  (9) The electroless plating process is performed, and an electroless plating film (not shown) is formed on each of the insulating layers 21 and 21 and the inner surface of the via hole 21H. Next, as shown in FIG. 4A, a plating resist 33 having a predetermined pattern is formed on the electroless plating film on each of the insulating layers 21.

  (10) Electrolytic plating is carried out, and as shown in FIG. 4B, electrolytic plating is filled in the via holes 21H to form the via conductors 17, and electroless plating of the respective insulating layers 21, 21 is performed. The electrolytic plating films 34 and 34 are formed on portions of the film (not shown) exposed from the plating resist 33.

  (11) Next, as shown in FIG. 4C, the plating resist 33 is peeled off, and the electroless plating film (not shown) below the plating resist 33 is removed, and the remaining electrolytic plating film is left. The conductor layers 22 and 22 are formed by the reference numeral 34 and the electroless plating film. Then, the conductor layers 12 and 12 on the front and back sides of the core substrate 11 and the conductor layers 22 and 22 are connected by via conductors 17.

  (12) Then, the processing similar to the processing of (7) to (11) is repeated a plurality of times, and as shown in FIG. 4 (D) to FIG. 7 (B), the F surface 11 F of the core substrate 11 and A plurality of insulating layers 21 and conductor layers 22 are alternately stacked on the S surface 11S to form buildup layers 20A and 20B.

  (19) As shown in FIG. 7C, the solder resist layers 26, 26 are laminated on both the front and back sides of the buildup layers 20, 20.

  (20) Then, as shown in FIG. 8A, a tapered opening 26H is formed at a predetermined location on the solder resist layers 26, 26 on the F surface 11F side and the S surface 11S side, and the circuit of the conductor layer 22 is formed. A part of the pattern 23 is exposed from the solder resist layer 26, and the pads 29, 29 are formed.

  (21) As shown in FIG. 8B, the frame-like groove 30T that reaches the first conductor layer 12F from the solder resist layer 26 on the F surface 11F side by the CO 2 laser is a plain of the first conductor layer 12F. It is formed along the outer edge of the pattern 24. Further, a frame-like groove 30T that reaches the second conductor layer 12S from the solder resist layer 26 on the S surface 11S side is formed on the plain pattern 24 of the second conductor layer 12S by the CO 2 laser.

  (22) As shown in FIG. 8C, the upper portion of the first buildup layer 20A above the peelable mask 45 on the inner side than the frame-like groove 30T is peeled off from the plain pattern 24 of the first conductor layer 12F. The first cavity 30A is formed by removal. In addition, the second buildup layer 20B is formed by peeling the lower portion of the second buildup layer 20B lower than the peelable mask 45 inside the frame shaped groove 30T from the plain pattern 24 of the second conductor layer 12S and removing the second buildup layer 20B. The second cavity 30B is formed in

  (23) On the pad 29, a nickel layer, a palladium layer and a gold layer are stacked in this order to form a metal film (not shown). Thus, the circuit board 10 shown in FIG. 1 is completed.

  The description of the structure and the manufacturing method of the circuit board 10 according to the present embodiment is as described above. Next, the operation and effect of the circuit board 10 will be described together with an example of use of the circuit board 10. As shown in FIG. 9, in the circuit board 10 of the present embodiment, the electronic component 90 is mounted in the first cavity 30A, and the heat sink 95 is mounted in the second cavity 30B. In the example shown in FIG. 9, the terminal 90A provided on the upper surface of the electronic component 90 and the pad 29 formed on the circuit board 10 are connected by wire bonding.

  When the electronic component 90 mounted in the first cavity 30 generates heat, the heat is transmitted from the first conductor layer 12F to the second conductor layer 12S via the vias 17. Then, the heat transferred to the second conductor layer 12S is transferred to the heat sink 95 mounted in the second cavity 30B. Thus, the heat of the electronic component 90 mounted in the first cavity 30A is dissipated from the heat sink 95 mounted in the second cavity 30B via the first conductor layer 12F and the second conductor layer 12S. Is possible.

  Further, since the bottom surfaces of the first cavity 30A and the second cavity 30B form the plain pattern 24, the contact surface with the electronic component 90 and the heat sink 95 can be enlarged.

Furthermore, since a plurality of vias 17 connecting the first conductor layer 12F and the second conductor layer 12S are provided, the heat of the electronic component 90 can be efficiently transmitted to the heat sink 95.
[Other embodiments]

  The present invention is not limited to the above-described embodiment, and, for example, the embodiments described below are also included in the technical scope of the present invention, and various other variations are possible without departing from the scope of the invention. It can be changed and implemented.

  (1) In the circuit board 10 of the above embodiment, the plain pattern 24 is exposed at the bottoms of the first cavity 30A and the second cavity 30B, but a plurality of lands are exposed instead of the plain pattern 24. The configuration may be

  (2) As shown in FIG. 10, the metal block 40 may be embedded in the core substrate 11. In the example shown in FIG. 10, the conductor layers 22, 22 connected to the metal block 40 via the connection conductor 15A are exposed from the bottom surfaces of the first cavity 30A and the second cavity 30B. In the embodiment shown in FIG. 10, the metal block 40, the conductor layers 22 and 22, and the connection conductor 15A correspond to the "heat radiation path" in the present invention.

  (3) As shown in FIG. 11, the core substrate 11 may be a metal core in which the metal layer 40 is laminated. At this time, the conductor layers 12F and 12S connected via the metal layer 40 and the connection conductor 15A may be exposed from the bottom surfaces of the first cavity 30A and the second cavity 30B. In the embodiment shown in FIG. 11, the metal layer 40, the conductor layers 12F and 12S, and the connection conductor 15A correspond to the "heat radiation path" in the present invention.

DESCRIPTION OF SYMBOLS 10 circuit board 11 core board | substrate 12,22 conductor layer 12F 1st conductor layer 12S 2nd conductor layer 15 connection conductor 17 via conductor 20A 1st buildup layer 20B 2nd buildup layer 21 insulating layer 23 circuit pattern 24 plane-like pattern 30A 1st cavity 30B 2nd cavity 90 electronic component 95 heat sink

Claims (7)

A circuit board comprising: a core substrate; and buildup layers respectively laminated on the first surface and the second surface of the core substrate,
The buildup layer includes a plurality of conductor layers alternately stacked, a plurality of insulating layers, and a connection conductor connecting the plurality of conductor layers.
In the buildup layer on the first surface side, a first cavity is formed which opens on the surface opposite to the surface facing the core substrate,
In the buildup layer on the second surface side, a second cavity is formed that opens on the side opposite to the surface facing the core substrate,
The first cavity and the second cavity are disposed at positions not overlapping in the thickness direction of the circuit board, and are in communication with each other via a metal heat radiation path. The circuit board according to claim 1, wherein
The heat radiation path is
A conductor layer on the first surface side of the core substrate, the first conductor layer exposed on the bottom surface of the first cavity;
A conductor layer on the second surface side of the core substrate, the second conductor layer exposed to the bottom surface of the second cavity;
And the connection conductor connecting the first conductor layer and the second conductor layer. The circuit board according to claim 2, wherein
Furthermore, a metal block is embedded at a position where both of the first cavity and the second cavity of the core substrate overlap in the thickness direction of the circuit substrate,
The heat radiation path is
Said metal block,
And a connection conductor connecting the metal block and the first conductor layer and the second conductor layer. The circuit board according to claim 2, wherein
Furthermore, a metal layer is provided inside the core substrate,
The heat radiation path is
The metal layer,
And a connection conductor connecting the metal layer to the first conductor layer and the second conductor layer. The circuit board according to claim 2, wherein
At least one conductor layer of the first conductor layer or the second conductor layer is
It overlaps with any of the first cavity and the second cavity in the thickness direction of the circuit board. The circuit board according to any one of claims 1 to 5, wherein
The connection conductor is a filled plating conductor. A method of manufacturing a circuit board,
Laminating build-up layers on the first surface and the second surface which are both the front and back surfaces of the core substrate;
Forming, in the buildup layer on the first surface side, a first cavity that opens on the side opposite to the surface facing the core substrate;
Forming a second cavity in the buildup layer on the second surface side at a position not overlapping the first cavity and the thickness direction of the circuit board with a surface opposite to the surface facing the core substrate; When,
Forming a heat dissipation path of metal connecting the first cavity and the second cavity.

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