JP2019041283A - Image pick-up device and imaging apparatus - Google Patents

Abstract

To set a gain automatically for each pixel circuit according to a signal level, in a configuration where amplification means capable of changing the gain is provided in each pixel circuit.SOLUTION: An image pick-up device includes photoelectric conversion means generating charges according to an incident ray volume, multiple pixel circuits including a charge storage capacity for storing the charges, and amplification means for amplifying a voltage, corresponding to the charge amount stored in the charge storage capacity, and outputting an optical signal, respectively, multiple AD conversion means including comparison means for comparing the optical signal from the amplification means with a reference signal and outputting a comparison result, and multiple gain setting means for setting a gain of the amplification means, respectively, where the gain setting means sets the gain of the amplification means, on the basis of the comparison result from the comparison means corresponding to each pixel circuit, for each pixel circuit.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an imaging element and an imaging apparatus.

  Due to the demand for higher image quality for imaging devices such as digital cameras, higher signal-to-noise ratios of imaging signals are required for imaging devices mounted on imaging devices. The S / N ratio is a ratio between a signal generated according to incident light and noise. If there is little noise and the S / N ratio is high, gain enhancement by signal processing can be performed to achieve high sensitivity as an imaging apparatus. it can.

  As noise generated in a solid-state image sensor, pixel noise such as dark current generated in a photodiode or a charge storage capacitor of a pixel, 1 / f noise generated in a pixel source follower, and readout noise generated in a reading circuit are known. Among each noise, components generated in the pixel source follower and the readout circuit can be equivalently suppressed by setting the conversion gain of the pixel source follower high.

  Patent Document 1 discloses a solid-state imaging device in which a plurality of photoelectric conversion units share a floating diffusion unit and a pixel source follower. In Patent Document 1, in the above-described configuration, the solid-state imaging device is driven so as to change the capacitance of the floating diffusion unit when reading a signal depending on the color of the color filter provided in the photoelectric conversion unit. Specifically, the conversion gain of the pixel source follower is switched by changing the capacitance of the floating diffusion unit when a signal is read out from the photoelectric conversion unit of a specific color in accordance with an external signal instruction. Thereby, a pixel signal of a color with low sensitivity is output with a high gain, and noise of the pixel of the color is suppressed.

JP 2008-305983 A

  When considering an actual shooting scene by the image pickup apparatus, the amount of accumulated signal varies from pixel to pixel even for pixels of the same color. However, in the conventional technique disclosed in Patent Document 1, the conversion gain of the pixel source follower is switched according to a predetermined drive pattern according to the color of the color filter provided in the photoelectric conversion unit. Therefore, when various light sources and subjects are photographed, it is not possible to selectively apply high gain to pixels with a small signal amount and drive them to suppress noise.

  The present invention has been made in view of the above problems, and in a configuration in which each pixel circuit is provided with an amplifying means capable of changing the gain, the gain is automatically set for each pixel circuit in accordance with the signal level. Objective.

  In order to achieve the above object, an imaging device according to the present invention includes a photoelectric conversion unit that generates a charge according to the amount of incident light, a charge storage capacitor that stores the charge, and a charge amount that is stored in the charge storage capacitor. A plurality of pixel circuits, each of which includes amplifying means for amplifying a corresponding voltage and outputting an optical signal; and a comparing means for comparing the optical signal from the amplifying means with a reference signal and outputting a comparison result A plurality of AD conversion means and a plurality of gain setting means for setting gains of the amplifying means, respectively, wherein the gain setting means is provided for each of the pixel circuits with the comparison means corresponding to each pixel circuit. Based on the comparison result, the gain of the amplification means is set.

  According to the present invention, in a configuration in which each pixel circuit is provided with an amplifying means capable of changing the gain, the gain can be automatically set for each pixel circuit in accordance with the signal level.

1 is a block diagram showing a schematic configuration of an imaging apparatus according to an embodiment of the present invention. 1 is a block diagram illustrating a schematic configuration of an image sensor according to a first embodiment. FIG. 3 is an equivalent circuit diagram of the image sensor according to the first embodiment. 3 is a drive timing chart of the image sensor according to the first embodiment. 5 is a flowchart illustrating image signal correction processing according to the first embodiment. The equivalent circuit diagram of the image sensor in the modification of 1st Embodiment. The block diagram which shows schematic structure of the image pick-up element in the modification of 1st Embodiment. FIG. 6 is an equivalent circuit diagram of an image sensor according to the second embodiment. The drive timing chart of the image sensor in 2nd Embodiment. The drive timing chart of the image sensor in 2nd Embodiment. 9 is a flowchart illustrating imaging signal correction processing according to the second embodiment. The equivalent circuit schematic of the image sensor in 3rd Embodiment. 10 is a drive timing chart of an image sensor according to a third embodiment. 10 is a flowchart illustrating imaging signal correction processing according to the third embodiment. FIG. 10 is an equivalent circuit diagram of an image sensor according to the fourth embodiment. 10 is a drive timing chart of an image sensor according to a fourth embodiment. 10 is a flowchart illustrating imaging signal correction processing according to the fourth embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram illustrating a schematic configuration of an imaging apparatus according to an embodiment of the present invention. The overall control / arithmetic circuit 3 performs overall drive / control of the entire imaging apparatus. The image sensor 1 receives a control signal from the overall control / arithmetic circuit 3, takes in incident light that has passed through the photographing lens 7, converts it into an image signal, and outputs it. The signal processing unit 2 receives a control signal from the overall control / arithmetic circuit 3 and performs various corrections such as signal amplification and data rearrangement on the image signal output from the image sensor 1.

  The recording unit 5 is a recording medium such as a memory card that records and holds an image signal or the like output from the overall control / arithmetic circuit 3. The display unit 4 displays an image after shooting, a live view image, various setting screens, and the like. The lens driving unit 6 receives the control signal from the overall control / arithmetic circuit 3 and drives the photographing lens 7.

<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described. FIG. 2 is a block diagram illustrating a configuration of the image sensor 1 according to the first embodiment. The pixel unit 10 includes a plurality of pixel circuits 100 arranged in a matrix. The configuration of each pixel circuit 100 will be described later. The column circuit unit 11 includes a plurality of column circuits 110, and is provided corresponding to each pixel column of the pixel unit 10 in the first embodiment. The configuration of each column circuit 110 will be described later.

  The column circuit control unit 12 supplies a control signal for controlling each circuit element to the column circuit 110. The pixel control unit 13 supplies a control signal for controlling each circuit element to each pixel circuit 100.

  FIG. 3 is an equivalent circuit diagram illustrating a configuration of the image sensor 1 according to the first embodiment. The image sensor 1 is characterized in that the gain of a pixel source follower that functions as an output amplifier that outputs a signal from a pixel can be switched according to the comparison result of the comparator 111. By setting the pixel source follower gain, it is possible to switch the amplification level of the signal level without providing a column amplifier, eliminating the noise generated by the column amplifier and without amplifying the noise generated by the pixel source follower. Thus, it is possible to perform signal readout with high gain. Furthermore, by switching the gain of the pixel source follower according to the comparison result of the comparator 111, it is possible to automatically select the gain according to the signal level independently for each pixel.

  Each pixel circuit 100 includes a photoelectric conversion unit 101 configured by a photodiode or the like that generates a signal charge corresponding to the amount of incident light. The floating diffusion layer FD is a first charge storage capacitor that stores charges generated in the photoelectric conversion unit 101. The transfer switch 102 controls the transfer of the signal charge generated in the photoelectric conversion unit 101 to the floating diffusion layer FD by the transfer pulse PTX supplied from the pixel control unit 13.

  The amplification transistor 103 functions as a pixel source follower that is a source follower amplifier together with a charge storage capacitor connected to a gate input unit including the floating diffusion layer FD, and amplifies and outputs the voltage of the charge storage capacitor. From the relational expression (V = Q / C) between the voltage V and the amount of charge Q stored in the capacitor C (V = Q / C), the pixel source corresponding to the amount of charge Q stored in the capacitor C decreases as the capacitance of the gate input portion of the amplification transistor 103 decreases. It can be seen that the output voltage of the follower increases. Therefore, the gain of the pixel source follower can be changed by changing the capacitance of the gate input portion of the amplification transistor 103.

  The additional capacitor 105 is a second charge storage capacitor and is provided in parallel with the floating diffusion layer FD. The capacity addition switch 104 connects / disconnects the additional capacity 105. By turning off the capacitor addition switch 104, the additional capacitor 105 can be disconnected from the floating diffusion layer FD, and the gain of the pixel source follower can be improved. The capacitance addition switch 104 is controlled by a gain setting pulse PGAIN or a direct control pulse PCR supplied from the column circuit 110.

  The reset switch 106 is used to reset the charges of the floating diffusion layer FD and the additional capacitor 105 and is controlled by a transfer pulse PRES supplied from the pixel control unit 13. The selection switch 107 controls connection between the pixel circuit 100 and the column circuit 110 by a selection pulse PSEL supplied from the pixel control unit 13.

  The current source I supplies current according to the output voltage of the pixel source follower of the pixel circuit 100 connected to the column circuit 110.

  The counter 120 is provided in the column circuit control unit 12 and counts up signals. The count value COUNT output from the counter 120 is input in common to the first memory 113n and the second memory 113s of the plurality of column circuits 110 provided in the column circuit unit 11.

  The pixel circuit 100 is connected to the column circuit 110. Here, one column circuit 110 is provided for each pixel column, but one column circuit 110 only needs to correspond to a plurality of pixel circuits 100. For example, one column circuit 110 corresponds to a predetermined pixel block unit. A column circuit 110 may be provided.

  The comparator 111 compares the signal voltage Vpix output from the pixel circuit 100 with the level of the reference signal RAMP, and outputs a high level when the voltage of the reference signal RAMP is high and a low level when it is low. The first memory 113n and the second memory 113s receive the transition from the high level to the low level of the output of the comparator 111, and store the count value input from the counter 120 as a digital signal value. The comparator 111, the counter 120, the first memory 113n, and the second memory 113s constitute an AD conversion circuit that can convert the signal voltage Vpix that is an analog signal into a digital signal.

  A gated latch circuit (hereinafter referred to as a latch circuit) 112 accepts input from each terminal only while the input enable pulse PLE is at a high level. At this time, when a high level is input as the output reset pulse PLR, the gain setting pulse PGAIN is reset to a low level. The moment the high level is input from the comparator 111 while the output reset pulse PLR is at the low level, the gain setting pulse PGAIN transitions to the high level and keeps the high level until it is reset by the output reset pulse PLR. . The gain setting pulse PGAIN output from the latch circuit 112 is supplied to the pixel circuit 100 connected to the column circuit 110 and is connected to the capacitance addition switch 104 of the pixel circuit 100.

  The control changeover switch 114 switches the control of the capacitance addition switch 104 from the control by the gain setting pulse PGAIN to the control by the direct control pulse PCR. When the direct control pulse PCR is at the high level, the direct control pulse PCR is connected to the gate electrode of the capacitance addition switch 104, and when the direct control pulse PCR is at the low level, the gain setting pulse PGAIN is connected to the gate electrode of the capacitance addition switch 104, respectively.

  Note that although FIG. 3 illustrates a configuration in which one pixel source follower including the amplification transistor 103 and the floating diffusion layer FD is provided for each photoelectric conversion unit 101, one pixel is included in the plurality of photoelectric conversion units 101. It is good also as a structure which shares a source follower.

  Next, with reference to FIG. 4, a signal reading operation from the pixel circuit 100 of the image sensor 1 in the first embodiment will be described. The feature of the signal readout operation in the first embodiment is that, in the signal readout operation from the pixel circuit 100, the gain of the pixel source follower is automatically set according to the output voltage of the pixel source follower according to the signal from each pixel. It is a point set up automatically. This readout operation makes it possible to set the gain independently for each pixel in accordance with the signal level.

  FIG. 4 is a drive timing chart when reading a signal from the pixel circuit 100. As a first step in signal readout, the latch circuit 112, the floating diffusion layer FD, and the additional capacitor 105 are reset between time T201 and time T208 before signal readout.

  First, at time T201, the input enable pulse PLE is set to high level, and the input to each terminal of the latch circuit 112 is enabled. At time T202, the output reset pulse PLR is set to the high level, the gain setting pulse PGAIN output from the latch circuit 112 is reset to the low level, and the capacitance addition switch 104 of the pixel circuit 100 is unified to the off state. The additional capacitor 105 is disconnected from the floating diffusion layer FD, the charge storage capacitance is reduced, and the gain of the pixel source follower is unified to the first gain which is a high gain.

  Next, at time T203, the output reset pulse PLR is set to low level. At this time, the latch circuit 112 continues to hold the low level as the gain setting pulse PGAIN. At time T204, the input enable pulse PLE is set to the low level, and the input to each terminal of the latch circuit 112 is disabled.

  At time T205, the selection pulse PSEL is set to high level, the selection switch 107 is turned on, and the pixel circuit 100 is connected to the column circuit 110. Further, the reference signal RAMP is set to the minimum input voltage Vrmax corresponding to the lower limit of the conversion range of the AD conversion circuit.

  At time T206, the reset pulse PRES is set to the high level, the reset switch 106 is turned on, and the charge of the floating diffusion layer FD is reset. At this time, the direct control pulse PCR is set to the high level, the control changeover switch 114 is turned on, and the charge of the additional capacitor 105 is simultaneously reset. At time T207, the reset pulse PRES is set to the low level, the reset switch 106 is turned off, and the resetting of the charges in the floating diffusion layer FD and the additional capacitor 105 is completed.

  At time T208, the direct control pulse PCR is set to low level, the control changeover switch 114 is turned off, the additional capacitor 105 is disconnected from the floating diffusion layer FD, and the gain of the pixel source follower is set to the first gain.

  Next, as a second step in signal readout, AD conversion of the reset signal Ref, which is the reset level of the floating diffusion layer FD, is performed between time T209 and time T210. First, writing to the first memory 113n is enabled. Then, during the period from time T209 to time T210, as the reference signal RAMP, a ramp wave whose voltage decreases from Vrmax in proportion to time is input, and at the same time, the counter 120 counts up from the count value 0. At the moment when the voltage of the ramp wave falls below the output voltage Vpix from the pixel circuit 100, the output COMP of the comparator 111 changes from low level to high level. In response to the transition of the output COMP of the comparator 111 to the low level, the count value of the counter 120 at that time is stored in the first memory 113n as the reset signal Ref, and writing to the first memory 113n is disabled. To.

  At time T210 when the AD conversion of the reset signal Ref is completed, the reference signal RAMP is set to the minimum input voltage Vrmin corresponding to the upper limit of the conversion range of the AD conversion circuit. Further, the count value of the counter 120 is set to the maximum value.

  Next, as a third step in signal readout, AD conversion of the optical signal Sig in which the optical signal level accumulated in the photoelectric conversion unit 101 is added to the reset signal Ref is performed between time T211 and time T216.

  First, between time T211 and time T213, the input enable pulse PLE is set to the high level, the input to each terminal of the latch circuit 112 is enabled, and the gain selection operation described below is performed.

  At time T211, the transfer pulse PTX is set to high level, the transfer switch 102 is turned on, and the charge accumulated in the photoelectric conversion unit 101 is transferred to the floating diffusion layer FD. At time T212, the transfer pulse PTX is set to low level, the transfer switch 102 is turned off, and the transfer of the charge accumulated in the photoelectric conversion unit 101 to the floating diffusion layer FD is completed.

  The comparator 111 compares the output voltage Vpix from the pixel circuit 100 with the voltage Vrmin of the reference signal RAMP. As shown in FIG. 4A, when the output voltage Vpix falls below the voltage Vrmin (that is, when the output voltage Vpix exceeds the upper limit of the AD conversion range), the output COMP of the comparator 111 changes from the high level to the low level. Transition. As a result, the latch circuit 112 holds the high level as the gain setting pulse PGAIN, and the capacitor addition switch 104 is turned on. As a result, the additional capacitor 105 is connected to the floating diffusion layer FD, and the gain of the pixel source follower is changed to the second gain that is lower than the first gain. As a result, the output voltage Vpix from the pixel circuit 100 exceeds the minimum input voltage Vrmin corresponding to the upper limit of the AD conversion range, and changes to a voltage within the AD conversion range.

  On the other hand, as shown in FIG. 4B, when the output voltage Vpix does not fall below the voltage Vrmin (that is, when the output voltage Vpix does not exceed the upper limit of the AD conversion range), the gain setting pulse PGAIN is at the low level. Will remain. As a result, the pixel source follower remains at the first gain which is a high gain. Since this gain setting operation is performed in each column circuit 110 every time a signal reading operation is performed, the gain of the pixel source follower is set for each pixel.

  At time T213, the input enable pulse PLE is set to the low level, the input to each terminal of the latch circuit 112 is disabled, and the gain selection operation is terminated.

  At time T214, the reference signal RAMP is set to the minimum input voltage Vrmax corresponding to the lower limit of the conversion range of the AD conversion circuit.

  Writing to the second memory 113s is enabled, and a ramp wave whose voltage decreases from Vrmax to Vrmin in proportion to time is input as the reference signal RAMP between time T215 and time T216. At the same time, the counter 120 counts up from the count value 0. At the moment when the voltage of the ramp wave falls below the output voltage Vpix from the pixel circuit 100, the output COMP of the comparator 111 changes from high level to low level. In response to the transition of the output COMP of the comparator 111 to the low level, the count value of the counter 120 at that time is stored in the second memory 113s as the optical signal Sig, and writing to the second memory 113s is disabled. To.

  At time T217, the selection pulse PSEL is set to low level, the selection switch 107 is turned off, and the pixel circuit 100 is disconnected from the column circuit 110. Thereafter, the reset signal Ref stored in the first memory 113n and the optical signal Sig stored in the second memory 113s are read. Further, 0 is read if the gain setting pulse PGAIN is at a low level, and 1 is read if the gain setting pulse PGAIN is at a high level, and the signal reading operation from the pixel is completed.

  The signal readout operation from the pixel circuit 100 described above is repeated until a signal of a desired number of pixels is read out, and a series of signal readout operations from the image sensor 1 is performed.

  In the first embodiment, the gain of the pixel source follower is set to the first gain which is a high gain and the gain setting operation is performed. However, the first gain which is lower than the first gain is used. The gain setting operation may be performed by setting the gain to 2. In this case, when the gain selection operation is performed on the input voltage corresponding to the value obtained by multiplying the upper limit value of the AD conversion range of the AD conversion circuit by the ratio G2 / G1 of the first gain G1 and the second gain G2. Set the reference signal RAMP and perform the gain setting operation. In addition, the pixels that do not fall below this voltage level may be driven to change the setting to the first gain G1, which is a higher gain than the second gain G2.

  In this read operation, the reset signal Ref is driven so as to be read with the first gain G1, which is a high gain. This is a pixel that outputs a signal that is read with a high gain G1, that is, a low-luminance signal that has a large influence on the S / N ratio, in a correction operation to be described later. This is to improve accuracy.

  Next, with reference to FIG. 5, the correction process of the signal read from the image sensor 1 will be described. One of the gains of two types of pixel source followers is set for each pixel in the optical signal Sig read by the signal reading operation of the present embodiment. Therefore, it is necessary to generate an image signal of one frame after performing correction so that the total gain applied to the optical signal Sig of each pixel becomes uniform. The main correction may be performed in the signal processing unit 2 of the imaging apparatus, or a correction circuit that performs the main correction may be provided inside the imaging device 1.

  In S101, a count value i of a counter (not shown) that counts the number of pixels subjected to signal processing is set to 1, and the process proceeds to S102. In S102, the optical signal Sig, the reset signal Ref, and the gain determination value GAIN are acquired for the i-th pixel, and the process proceeds to S103.

  In S103, it is determined whether the gain determination value GAIN is zero. If it is 0, it is determined that the pixel source follower is set to the first gain G1, which is a high gain, and the process proceeds to S104. If it is not 0, it is determined that the pixel source follower is set to the second gain G2, which is a low gain. Then, the process proceeds to S105.

  In S104, a correction operation is performed on the optical signal Sig read with the pixel source follower set to the first gain G1, which is a high gain. By subtracting the reset signal Ref from the optical signal Sig, the variation component of the reset level of the pixel source follower is removed to obtain a corrected signal S for the pixel, and the process proceeds to S106.

  In S105, a correction operation is performed on the optical signal Sig read with the pixel source follower set to the second gain G2, which is a low gain. Gain correction is performed by multiplying the optical signal Sig by the ratio G1 / G2 of the first gain G1 and the second gain G2, and then the reset signal Ref is subtracted to obtain the corrected signal S in the pixel. The process proceeds to S106.

  In S106, it is determined whether the count value i is equal to the total number of pixels in one frame. If the count value i has not reached the total number of pixels in one frame, the process proceeds to S107, and if the count value i has reached the total number of pixels in one frame, the correction process is terminated. In S107, 1 is added to the count value i, and the process returns to S102 and the above processing is repeated.

  By performing the correction processing as described above, a signal S having the same total gain can be obtained from the image sensor 1 and the signal processing unit 2 from the optical signal Sig of each pixel in which the gain of the pixel source follower is set. . An image signal of one frame is generated using the signal S of each pixel thus obtained.

  As described above, in the first embodiment, the charge storage capacity of the pixel source follower can be switched according to the output voltage of the pixel circuit, so that the gain of the pixel source follower is automatically set according to the output voltage for each pixel. The configuration can be set with. Thereby, gain setting according to the signal level can be performed independently for each pixel, and noise can be suppressed according to the signal level for each pixel.

<Modification>
Next, a modification of the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 6 is an equivalent circuit diagram showing a configuration of the image sensor 1 in a modification of the first embodiment of the present invention. The image sensor 1 in this modification is different from the first embodiment in that the readout circuit 410 corresponding to the column circuit 110 of the first embodiment is provided for each pixel circuit 400 one by one. This is the point. Accordingly, one signal latch circuit 112 is provided corresponding to each pixel circuit 400. Note that the selection switch 107 provided in the second embodiment is not necessary here because it is not necessary to select the pixel circuit 400 connected to the readout circuit 410 when performing readout.

  FIG. 7 is a block diagram showing a configuration of the image sensor 1 in the present modification. In this modification, since the readout circuit 410 is provided for each pixel circuit 400, the circuit scale per pixel increases. In order to suppress a decrease in the aperture ratio of the photoelectric conversion unit 101 in such a configuration, here, an example in which the imaging element 1 is divided into a plurality of substrates and the divided substrates are stacked is shown. FIG. 7A shows a cross-sectional view (dotted line X1-X2 in FIG. 7B) of the image sensor 1 in this modification, and FIGS. 7B and 7C show top views. Here, the first substrate 1u and the second substrate 1d are stacked. In addition, a pixel unit 40 in which a plurality of pixel circuits 400 are arranged in a matrix and a pixel control unit 43 are arranged on the first substrate 1u. Then, a read circuit unit 41 provided with a plurality of read circuits 410 corresponding to each pixel circuit 400 and a read circuit control unit 42 that supplies a control signal for controlling the read circuit unit 41 are provided on the second substrate 1d. It is arranged.

  Since the other configuration of the image sensor 1 is the same as that of the image sensor 1 of the first embodiment, the description thereof is omitted.

  In the configuration in which the readout circuit 410 is provided for each pixel circuit 400 as in this modification, signal readout from all the pixel circuits 400 can be performed simultaneously in parallel. Also in the image sensor having such a configuration, a configuration in which the gain of the pixel source follower can be automatically set according to the output voltage for each pixel can be applied as in the first embodiment.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. In the second embodiment, an image sensor 1 a having a configuration different from that of the image sensor 1 in the first embodiment is used instead of the image sensor 1. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  The image sensor 1a in the second embodiment is different from the image sensor 1 of the first embodiment in that the gain of the pixel source follower that functions as an output amplifier that outputs a signal from the pixel can be switched in a plurality of stages. It is the point which is made up.

  FIG. 8 is an equivalent circuit diagram showing the configuration of the image sensor 1a in the second embodiment. In FIG. 8, as an example of a configuration in which the gain of the pixel source follower can be switched to a plurality of stages, a configuration in which three types of gains can be set by switching the gain of the pixel source follower in two stages.

  In addition to the configuration of the pixel circuit 100 described with reference to FIG. 3, the pixel circuit 100a according to the second embodiment further includes an additional capacitor as a third charge storage capacitor provided in parallel with the floating diffusion layer FD. 105a and a capacity addition switch 104a. The capacity addition switch 104a connects / disconnects the additional capacity 105a. By turning off the capacitor addition switch 104a, the additional capacitor 105a can be disconnected from the floating diffusion layer FD, and the gain of the pixel source follower can be improved. The capacitance addition switch 104 is controlled by the first gain setting pulse PGAIN1 or the direct control pulse PCR supplied from the column circuit 110a. The capacitance addition switch 104a is controlled by the second gain setting pulse PGAIN2 or the direct control pulse PCR supplied from the column circuit 110a.

  A pixel circuit 100a is connected to the column circuit 110a. The gain setting pulse PGAIN1 output from the gated latch circuit (hereinafter referred to as a latch circuit) 112 is supplied to the pixel circuit 100a connected to the column circuit 110a, and is connected to the capacitance addition switch 104 of the pixel circuit 100a. The latch circuit 112a accepts input from each terminal only while the input enable pulse PLE2 is at a high level. As the input enable pulse PLE2, either the input enable pulse PLE common to the latch circuit 112 or the delay signal of the gain setting pulse PGAIN1 output from the latch circuit 112 is selectively input by the input selection pulse PLESEL. The gain setting pulse PGAIN1 input to the latch circuit 112a is delayed by the delay element 115. When the high level is input as the output reset pulse PLR while the input enable pulse PLE2 is at the high level, the gain setting pulse PGAIN2 is reset to the low level. The moment the high level is input from the comparator 111 while the output reset pulse PLR is at the low level, the gain setting pulse PGAIN2 transitions to the high level and keeps the high level until it is reset by the output reset pulse PLR. . The gain setting pulse PGAIN2 output from the latch circuit 112a is supplied to the pixel circuit 100a connected to the column circuit 110a, and is connected to the capacitance addition switch 104a of the pixel circuit 100a.

  The control changeover switch 114a switches the control of the capacitance addition switch 104a from the control by the gain setting pulse PGAIN2 to the control by the direct control pulse PCR. When the direct control pulse PCR is at the high level, the direct control pulse PCR is connected to the gate electrode of the capacitance addition switch 104a, and when the direct control pulse PCR is at the low level, the gain setting pulse PGAIN2 is connected.

  Since the other configuration of the image sensor 1a is the same as that of the image sensor 1 of the first embodiment, description thereof is omitted.

  Next, with reference to FIG. 9, a signal readout operation from the pixel circuit 100a of the image sensor 1a in the second embodiment will be described. The features of the signal reading operation in the second embodiment that are different from those in the first embodiment are as follows. That is, in the signal read operation from the pixel circuit 100a, when the gain of the pixel source follower is automatically set according to the output voltage of the pixel source follower according to the signal from each pixel, 0 for each pixel. One of the gain changes is performed in any one of the two stages. By this readout operation, an appropriate gain can be selected and set from a plurality of gains according to the signal level independently for each pixel.

  FIG. 9 is a drive timing chart when reading a signal from the pixel circuit 100a. As a first step in signal readout, the latch circuits 112 and 112a, the floating diffusion layer FD, and the additional capacitors 105 and 105a are reset between time T601 and time T608 before signal readout.

  First, at time T601, the input enable pulse PLE and the input selection pulse PLESEL are set to the high level, and the input to each terminal of the latch circuits 112 and 112a is enabled. At time T602, the output reset pulse PLR is set to high level, and the gain setting pulse PGAIN1 output from the latch circuit 112 and the gain setting pulse PGAIN2 output from the latch circuit 112a are reset to low level. This unifies the capacitance addition switches 104 and 104a of the pixel circuit 100a to the off state. The additional capacitors 105 and 105a are separated from the floating diffusion layer FD, the charge storage capacitance is reduced, and the gain of the pixel source follower is unified to the first gain which is a high gain.

  Next, at time T603, the output reset pulse PLR is set to low level. At this time, the latch circuit 112 continues to hold the low level as the gain setting pulse PGAIN1. The latch circuit 112a continues to hold the low level as the gain setting pulse PGAIN2. At time T604, the input enable pulse PLE and the input selection pulse PLESEL are set to low level, and the inputs to the respective terminals of the latch circuits 112 and 112a are disabled.

  At time T605, the selection pulse PSEL is set to the high level, the selection switch 107 is turned on, and the pixel circuit 100a is connected to the column circuit 110a. Further, the reference signal RAMP is set to the minimum input voltage Vrmax corresponding to the lower limit of the conversion range of the AD conversion circuit.

  At time T606, the reset pulse PRES is set to high level, the reset switch 106 is turned on, and the charge of the floating diffusion layer FD is reset. At this time, the direct control pulse PCR is set to the high level, the control changeover switches 114 and 114a are turned on, and the charges of the additional capacitors 105 and 105a are simultaneously reset. At time T607, the reset pulse PRES is set to the low level, the reset switch 106 is turned off, and the resetting of the charges in the floating diffusion layer FD and the additional capacitors 105 and 105a is completed.

  At time T608, the direct control pulse PCR is set to the low level, the control changeover switches 114 and 114a are turned off, the additional capacitors 105 and 105a are disconnected from the floating diffusion layer FD, and the gain of the pixel source follower is set to the first gain. .

  Next, as a second step in signal readout, AD conversion of the reset signal Ref, which is the reset level of the floating diffusion layer FD, is performed between time T609 and time T610. Note that the operation from time T609 to time T610 is the same as the operation from time T209 to time T210 in the first embodiment, and thus description thereof is omitted.

  Next, as a third step in signal readout, AD conversion of the optical signal Sig in which the optical signal level accumulated in the photoelectric conversion unit 101 is added to the reset signal Ref is performed between time T611 and time T616.

  First, between time T611 and time T613, the input enable pulse PLE is set to the high level, the input to each terminal of the latch circuit 112 is enabled, and the gain selection operation described below is performed.

  At time T611, the transfer pulse PTX is set to high level, the transfer switch 102 is turned on, and the charge accumulated in the photoelectric conversion unit 101 is transferred to the floating diffusion layer FD. At time T612, the transfer pulse PTX is set to low level, the transfer switch 102 is turned off, and the transfer of the charge accumulated in the photoelectric conversion unit 101 to the floating diffusion layer FD is completed.

  The comparator 111 compares the output voltage Vpix from the pixel circuit 100a with the voltage Vrmin of the reference signal RAMP. As shown in FIGS. 9A and 9B, when the output voltage Vpix is lower than the voltage Vrmin (that is, when the output voltage Vpix exceeds the upper limit of the AD conversion range), the output COMP of the comparator 111 is low level. Transition from to high level. As a result, the latch circuit 112 holds the high level as the gain setting pulse PGAIN1, and the capacitor addition switch 104 is turned on. Accordingly, the additional capacitor 105 is connected to the floating diffusion layer FD, the gain of the pixel source follower is changed to the second gain that is lower than the first gain, and the output voltage Vpix from the pixel circuit 100a is changed. , Change to a higher voltage.

  On the other hand, as shown in FIG. 10, when the output voltage Vpix does not fall below the voltage Vrmin (that is, when the output voltage Vpix does not exceed the upper limit of the AD conversion range), the gain setting pulse PGAIN1 remains at the low level. . As a result, the pixel source follower remains at the first gain which is a high gain.

  Since the delay signal of the gain setting pulse PGAIN1 is input to the latch circuit 112a, when the gain setting pulse PGAIN1 transits to a high level as shown in FIGS. 9A and 9B, the signals to the respective terminals of the latch circuit 112a are supplied. The input is enabled. At this time, as shown in FIG. 9A, when the output voltage Vpix is still lower than the voltage Vrmin (that is, when the output voltage Vpix exceeds the upper limit of the AD conversion range), the output COMP of the comparator 111 is output. Remains low. As a result, the high level is held as the gain setting pulse PGAIN2 in the latch circuit 112a, the capacitance additional switch 104a is turned on, and the additional capacitance 105a is connected to the floating diffusion layer FD. As a result, the gain of the pixel source follower is changed to a third gain that is lower than the second gain. As a result, the output voltage Vpix from the pixel circuit 100a exceeds the minimum input voltage Vrmin corresponding to the upper limit of the AD conversion range, and changes to a voltage within the AD conversion range. As shown in FIG. 9B, when the output voltage Vpix does not fall below the voltage Vrmin (that is, when the output voltage Vpix does not exceed the upper limit of the AD conversion range), the gain setting pulse PGAIN2 remains at the low level. Therefore, the gain of the pixel source follower remains the second gain.

  Since this gain setting operation is performed in each column circuit each time a signal readout operation is performed, the number of stages in which the gain is switched differs depending on the level of the output signal, and the gain of the pixel source follower is changed to three types of gains. Are selected and set for each pixel.

  At time T613, the input enable pulse PLE is set to low level, the input to each terminal of the latch circuit 112 is disabled, and the gain selection operation is terminated.

  Since the operation from time T614 to time T616 is the same as the operation from time T214 to time T216 in the first embodiment, description thereof will be omitted.

  At time T617, the selection pulse PSEL is set to low level, the selection switch 107 is turned off, and the pixel circuit 100a is disconnected from the column circuit 110a. Thereafter, the reset signal Ref stored in the first memory 113n and the optical signal Sig stored in the second memory 113s are read. Further, 0 is read if the gain setting pulse PGAIN1 is at a low level, and 1 is read if the gain setting pulse PGAIN1 is at a high level, as the gain determination value GAIN1 that is information indicating the gain. Further, as the gain determination value GAIN2, which is information indicating the gain, 0 is read if the level of the gain setting pulse PGAIN2 is low, and 1 is read if the level is high, and the signal reading operation from the pixel circuit 100a is terminated.

  The signal readout operation from the pixel circuit 100a described above is repeated until a signal having a desired number of pixels is read out, and a series of signal readout operations from the image sensor 1a is performed.

  Next, with reference to FIG. 11, the correction process of the signal read from the image sensor 1a will be described. In the optical signal Sig read by the signal reading operation of the second embodiment, any one of three different pixel source follower gains is set for each pixel. Therefore, it is necessary to generate an image signal of one frame after performing correction so that the total gain applied to the optical signal Sig of each pixel becomes uniform. The main correction may be performed in the signal processing unit 2 of the imaging apparatus, or a correction circuit that performs the main correction may be provided inside the imaging device 1a.

  In S201, the count value i of a counter (not shown) that counts the number of pixels subjected to signal processing is set to 1, and the process proceeds to S202. In S202, the optical signal Sig, the reset signal Ref, and the gain determination values GAIN1 and GAIN2 are acquired for the i-th pixel, and the process proceeds to S203.

  In S203, it is determined whether or not the gain determination value GAIN1 is zero. If it is 0, it is determined that the pixel source follower is set to the first gain G1, which is a high gain, and the process proceeds to S204. If it is not 0, it is determined that the pixel source follower is set to another gain, and the process proceeds to S205. .

  In S204, the pixel source follower is set to the first gain G1 and correction calculation is performed on the read optical signal Sig. By subtracting the reset signal Ref from the optical signal Sig, the variation component of the reset level of the pixel source follower is removed to obtain a corrected signal S for the pixel, and the process proceeds to S208.

  In S205, it is determined whether or not the gain determination value GAIN2 is zero. If it is 0, it is determined that the pixel source follower is set to the second gain G2, and the process proceeds to S206. If it is not 0, it is determined that the pixel source follower is set to the lower third gain G3, and the process proceeds to S207.

  In S206, the pixel source follower is set to the second gain G2, and the correction operation is performed on the optical signal Sig read out. Gain correction is performed by multiplying the optical signal Sig by the ratio G1 / G2 of the first gain G1 and the second gain G2, and then the reset signal Ref is subtracted to obtain the corrected signal S in the pixel. , Go to S208.

  In S207, the pixel source follower is set to the third gain G3, and a correction operation is performed on the read optical signal Sig. Gain correction is performed by multiplying the optical signal Sig by the ratio G1 / G3 of the first gain G1 and the third gain G3, and then the reset signal Ref is subtracted to obtain the corrected signal S in the pixel. , Go to S208.

  In S208, it is determined whether the count value i is equal to the total number of pixels in one frame. If the count value i has not reached the total number of pixels in one frame, the process proceeds to S209, and if the count value i has reached the total number of pixels in one frame, the correction process is terminated. In S209, 1 is added to the count value i, and the process returns to S202 to repeat the above processing.

  By performing the correction process as described above, a signal S having the same total gain can be obtained from the optical signal Sig of each pixel in which the gain of the pixel source follower is set. . An image signal of one frame is generated using the signal S of each pixel thus obtained.

  In the second embodiment, a configuration in which three types of gains can be set by switching gains in two stages has been described as an example. However, by developing in a similar manner, the number of stages is not limited to two, and more stages. It is possible to develop a configuration in which gain switching is possible.

  As described above, in the second embodiment, the charge storage capacity of the pixel source follower is configured to be switchable in a plurality of stages, and the number of stages for switching the capacity is varied according to the output voltage of the pixel circuit. Thus, the gain of the pixel source follower can be automatically set according to the output voltage for each pixel. Accordingly, it is possible to change the gain setting in a plurality of stages according to the signal level independently for each pixel, and it is possible to suppress noise according to the signal level for each pixel.

<Third Embodiment>
Next, a third embodiment of the present invention will be described. In the third embodiment, an image sensor 1 b having a configuration different from that of the image sensor 1 in the first embodiment is used instead of the image sensor 1. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  FIG. 12 is an equivalent circuit diagram illustrating a configuration of the image sensor 1b according to the third embodiment. The image sensor 1b in the third embodiment is different from the image sensor 1 in the first embodiment in that the gain of the pixel source follower that functions as an output amplifier that outputs a signal from the pixel is not stepwise. This is a configuration that can be changed continuously.

  A pixel circuit 100b according to the third embodiment includes a MOS capacitor 108 as illustrated in FIG. 12 instead of the additional capacitor 105 of the pixel circuit 100 described with reference to FIG. When the gate voltage at which the capacitance of the MOS capacitor 108 is maximized is Vgmax and the minimum gate voltage is Vgmin, the gate voltage is continuously changed between Vgmin and Vgmax, thereby continuously increasing the gain of the pixel source follower. Can be changed. The gate of the MOS capacitor 108 is controlled by a gain setting voltage VGAIN supplied from the DAC circuit 130.

  The counter 120b is provided in the column circuit control unit 12, and performs up-counting and down-counting of signals. The count value COUNT is input in common to the memories 113n, 113s, 113g of the plurality of column circuits 110b provided in the column circuit unit 11.

  The pixel circuit 100b is connected to the column circuit 110b. The comparator 111b compares the signal voltage Vpix output from the pixel circuit 100b with the level of the reference signal RAMP, and outputs a low level when the signal voltage Vpix is low and a high level when the signal voltage Vpix is high. The first memory 113n, the second memory 113s, and the third memory 113g store the count value input from the counter 120b as a digital signal value in response to the transition from the low level to the high level of the output of the comparator 111b. To do.

  The gated latch circuit (hereinafter latch circuit) 112b accepts input from each terminal only while the input enable pulse PLE is at a high level. At this time, when a high level is input as the output reset pulse PLR, the gate voltage holding pulse PVGH is reset to the high level. The moment the high level is input from the comparator 111b while the output reset pulse PLR is low level, the gate voltage holding pulse PVGH transitions to low level and remains low until reset by the output reset pulse PLR. to continue. The gate voltage holding pulse PVGH output from the latch circuit 112b is provided on the supply line of the gain setting voltage VGAIN supplied from the column circuit 110b to the pixel circuit 100b, and is connected to the gate voltage holding switch 117.

  Since the other configuration of the image sensor 1b is the same as that of the image sensor 1 of the first embodiment, description thereof is omitted.

  Next, with reference to FIG. 13, a signal readout operation from the pixel circuit 100b of the image sensor 1b in the third embodiment will be described. The signal readout operation according to the third embodiment is characterized in that the gain of the pixel source follower is automatically set according to the output voltage from each pixel circuit 100b during the signal readout operation from the pixel circuit 100b. However, the gain is changed continuously, not in steps.

  FIG. 13 is a drive timing chart when reading a signal from the pixel circuit 100b. As a first step in signal readout, the latch circuit 112b and the floating diffusion layer FD are reset between time T901 and time T908 before signal readout.

  First, at time T901, the input enable pulse PLE is set to the high level, and the input to each terminal of the latch circuit 112b is enabled. At time T902, with the output voltage from the DAC circuit 130 set to Vgmin, the output reset pulse PLR is set to high level, and the gate voltage holding pulse PVGH output from the latch circuit 112b is reset to high level. As a result, the gate voltage holding switch 117 of each column circuit 110b is turned on, and the gain setting voltage VGAIN supplied to the MOS capacitor 108 of each pixel circuit 100b is unified to Vgmin. Accordingly, the capacitance of the MOS capacitor 108 is minimized, and the gain of the pixel source follower is unified to the maximum gain.

  At time T903, the output reset pulse PLR is set to low level. At this time, the latch circuit 112b continues to hold the high level as the gate voltage holding pulse PVGH. At time T904, the input enable pulse PLE is set to the low level, and the input to each terminal of the latch circuit 112b is disabled.

  At time T905, the selection pulse PSEL is set to high level, the selection switch 107 is turned on, and the pixel circuit 100b is connected to the column circuit 110b.

  At time T906, the reset pulse PRES is set to high level, the reset switch 106 is turned on, and the charge of the floating diffusion layer FD is reset. At time T907, the reset pulse PRES is set to the low level, the reset switch 106 is turned off, and the resetting of the charge in the floating diffusion layer FD is completed.

  Next, as a second step in signal readout, AD conversion of a reset signal Ref that is a reset level of the floating diffusion layer FD is performed between time T908 and time T909. First, writing to the first memory 113n is enabled. Then, during time T908 to time T209, as a reference signal RAMP, a ramp wave whose voltage decreases in proportion to time is input from Vrmax, and at the same time, the counter 120b counts up from the count value 0. At the moment when the voltage of the ramp wave falls below the output voltage Vpix from the pixel circuit 100b, the output COMP of the comparator 111b changes from the low level to the high level. In response to the transition of the output COMP of the comparator 111b to the high level, the count value of the counter 120b at that time is stored in the first memory 113n as the reset signal Ref, and writing to the first memory 113n is disabled. To.

  At time T909 when the AD conversion of the reset signal Ref is completed, the reference signal RAMP is set to the minimum input voltage Vrmin corresponding to the upper limit of the conversion range of the AD conversion circuit. Further, the count value of the counter 120b is set to Cmax.

  The operation from time T909 to time T910 is the same as the operation from time T210 to time T211 of the first embodiment, but the count value of the counter 120b is set to zero.

  Next, as a third step in signal readout, AD conversion of the optical signal Sig in which the optical signal level accumulated in the photoelectric conversion unit 101 is added to the reset signal Ref is performed between time T910 and time T915.

  First, at time T910, the transfer pulse PTX is set to the high level, the transfer switch 102 is turned on, and the charge accumulated in the photoelectric conversion unit 101 is transferred to the floating diffusion layer FD. At time T911, the transfer pulse PTX is set to low level, the transfer switch 102 is turned off, and the transfer of the charge accumulated in the photoelectric conversion unit 101 to the floating diffusion layer FD is completed.

  From time T911 to time T912, the input enable pulse PLE is set to high level, the input to each terminal of the latch circuit 112b is enabled, and the gain setting operation described below is performed.

  Writing to the third memory 113g is enabled, and a voltage waveform that changes the gain of the pixel source follower from the maximum to the minimum in proportion to the time is output from the DAC circuit 130 from time T911 to time T912. .

  The comparator 111b compares the output voltage Vpix from the pixel circuit 100b with the voltage waveform of the reference signal RAMP, and when the output voltage Vpix exceeds the voltage Vrmin of the reference signal RAMP, the output COMP of the comparator 111b changes from the low level. Transition to high level. As a result, the latch circuit 112b holds the low level as the gate voltage holding pulse PVGH, the gate voltage holding switch 117 is turned off, the capacitance of the MOS capacitor 108 connected to the floating diffusion layer FD is fixed, and the pixel source follower Gain is determined.

  On the other hand, as shown in FIG. 13B, if the output voltage Vpix is not lower than the voltage Vrmin at time T911 (that is, the output voltage Vpix exceeds the AD conversion range even if the pixel source follower has the maximum gain). If not, the pixel source follower is held at maximum gain. In the other pixels, as shown in FIG. 13A, the gain of the pixel source follower decreases with time in accordance with the output voltage from the DAC circuit. When the output voltage Vpix exceeds the voltage Vrmin, the capacitance of the MOS capacitor 108 is fixed, and the gain of the pixel source follower is held.

  The counter 120b counts down from the count value Cmax to the count value 0 between time T911 and time T912. In response to the transition of the output COMP of the comparator 111b to the high level, the count value at that time is stored in the third memory 113g as a gain coefficient Cgain which is information indicating the gain, and writing to the third memory 113g is performed. Disable state. Since this gain setting operation is performed in each column circuit 110b every time a signal reading operation is performed, the gain of the pixel source follower is set for each pixel.

  At time T912, the input enable pulse PLE is set to low level, the input to each terminal of the latch circuit 112b is disabled, and the gain setting operation is terminated.

  At time T913, the reference signal RAMP is set to the minimum input voltage Vrmax corresponding to the lower limit of the conversion range of the AD conversion circuit.

  Writing to the second memory 113s is enabled, and a ramp wave whose voltage decreases from Vrmax to Vrmin in proportion to time is input as the reference signal RAMP between time T914 and time T915. At the same time, the counter 120b counts up from the count value 0. At the moment when the voltage of the ramp wave falls below the output voltage Vpix from the pixel circuit 100b, the output COMP of the comparator 111b changes from the low level to the high level. In response to the transition of the output COMP of the comparator 111b to the high level, the count value of the counter 120b at that time is stored in the second memory 113s as the optical signal Sig, and writing to the second memory 113s is disabled. To.

  At time T916, the selection pulse PSEL is set to low level, the selection switch 107 is turned off, and the pixel circuit 100b is disconnected from the column circuit 110b. Thereafter, the reset signal Ref stored in the first memory 113n, the optical signal Sig stored in the second memory 113s, and the gain coefficient Cgain stored in the third memory 113g are read out, and the signal is read out from the pixel circuit 100b. End the operation.

  The signal readout operation from the pixel circuit 100b described above is repeated until a signal having a desired number of pixels is read out, and a series of signal readout operations from the image sensor 1b is performed.

  In the third embodiment, the gain setting operation is performed by setting the gain of the pixel source follower to the maximum gain, but the gain setting operation is performed by setting the gain of the pixel source follower to the minimum gain. You may do it. In this case, from time T911 to time T912, a voltage waveform that changes the gain of the pixel source follower from the minimum to the maximum in proportion to the time is output from the DAC circuit 130 to perform the gain setting operation. . Even if the pixel source follower gain is set to the maximum gain, the pixel source follower gain is set to the maximum gain for pixels that do not fall below the minimum input voltage Vrmin corresponding to the upper limit of the conversion range of the AD converter circuit. The subsequent signal reading operation may be performed.

  Next, with reference to FIG. 14, the correction process of the signal read from the image sensor 1b will be described. In the optical signal Sig read by the signal reading operation of the third embodiment, different pixel source follower gains are set for each pixel. Therefore, it is necessary to generate an image signal of one frame after performing correction so that the total gain applied to the optical signal Sig of each pixel becomes uniform. The main correction may be performed in the signal processing unit 2 of the imaging apparatus, or a correction circuit that performs the main correction may be provided inside the imaging device 1b.

  In S301, the count value i of a counter (not shown) that counts the number of pixels subjected to signal processing is set to 1, and the process proceeds to S302. In S302, the optical signal Sig, the reset signal Ref, and the gain coefficient Cgain are acquired for the i-th pixel, and the process proceeds to S303.

  In S303, it is determined whether or not the gain coefficient Cgain is zero. If it is 0, it is determined that the pixel source follower is set to the maximum gain, and the process proceeds to S304. If it is not 0, it is determined that the pixel source follower is set to a lower gain, and the process proceeds to S305.

  In S304, the pixel source follower is set to the maximum gain, and a correction operation is performed on the optical signal Sig read out. By subtracting the reset signal Ref from the optical signal Sig, the variation component of the reset level of the pixel source follower is removed to obtain a corrected signal S for the pixel, and the process proceeds to S306.

In S305, the pixel source follower is set to a lower gain and a correction operation is performed on the optical signal Sig read out. The maximum gain is Gmax, the minimum gain is Gmin, and the gain Gsig of the pixel source follower at the time of reading the optical signal Sig of the pixel is obtained from the gain coefficient Cgain according to the equation (1). The gain correction is performed by multiplying the optical signal Sig by the ratio to the maximum gain according to the equation (2), and then the reset signal Ref is subtracted to obtain the corrected signal S for the pixel, S306 Proceed to
Gsig = (Gmax-Gmin) * Cgain / Cmax + Gmin (1)
S = Gmax / Gsig * Sig-Ref (2)

  In S306, it is determined whether the count value i is equal to the total number of pixels in one frame. If the count value i has not reached the total number of pixels in one frame, the process proceeds to S307, and if the count value i has reached the total number of pixels in one frame, the correction process is terminated. In S307, 1 is added to the count value i, and the process returns to S302 to repeat the above processing.

  By performing the correction processing as described above, a signal S having the same total gain can be obtained from the image signal 1b and the signal processing unit 2 from the optical signal Sig of each pixel in which the gain of the pixel source follower is set. . One-frame image signals may be generated using the signal S of each pixel thus obtained.

  As described above, according to the third embodiment, the gain of the pixel source follower can be set for each pixel by continuously changing the capacitance of the floating diffusion layer in accordance with the output voltage of the pixel. As a result, the amplifying means provided in the pixel circuit enables continuous gain change according to the signal level independently for each pixel, and noise can be suppressed according to the signal level for each pixel. .

<Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, an image sensor 1 c having a configuration different from that of the image sensor 1 in the first embodiment is used instead of the image sensor 1. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  The fourth embodiment is different from the first embodiment in that the reset signal Ref is read with both the first gain and the second gain. In the pixel circuit 100, when the potentials of the floating diffusion layer FD and the additional capacitor 105 in a state where the charges are reset are different, the reset signal Ref depends on whether the additional capacitor 105 is connected to the floating diffusion layer FD or not. The level of changes. Therefore, in order to remove the variation in the reset level with higher accuracy, in the fourth embodiment, the reset signal Ref is read with both the first gain and the second gain.

  FIG. 15 is an equivalent circuit diagram showing the configuration of the image sensor 1c in the third embodiment. The image sensor 1c in the fourth embodiment stores reset signals for both the first gain and the second gain. Therefore, the column circuit 110c is different from the first embodiment in that it includes a third memory 118 having the same function in addition to the first and second memories 113n and 113s. Since the other configuration of the image sensor 1c is the same as that of the image sensor 1 of the first embodiment, description thereof is omitted.

  Next, with reference to FIG. 16, a signal reading operation from the pixel circuit 100 of the image sensor 1c in the fourth embodiment will be described.

  The operation performed before time T1501 is the same as the operation from time T201 to time T205 shown in FIG. At time T1501, the reset pulse PRES is set to high level, the reset switch 106 is turned on, and the charge of the floating diffusion layer FD is reset. At this time, the direct control pulse PCR is set to the high level, the control changeover switch 114 is turned on, and the charge of the additional capacitor 105 is simultaneously reset. At time T1502, the reset pulse PRES is set to the low level, the reset switch 106 is turned off, and the resetting of the charges in the floating diffusion layer FD and the additional capacitor 105 is completed.

  From time T1503 to time T1504, the direct control pulse PCR is kept at the high level. Then, in a state where the control changeover switch 114 of each pixel is turned on, AD conversion of the second reset signal Ref2 that is the reset level of the floating diffusion layer FD is performed with the second gain that is low gain. Further, writing to the third memory 118 is enabled, and a ramp wave whose voltage decreases in proportion to time from Vrmax is input as the reference signal RAMP between time T1503 and time T1504. Simultaneously with the input of the ramp wave, the counter 120 counts up from the count value 0. At the moment when the voltage of the ramp wave falls below the output voltage Vpix from the pixel circuit 100, the output COMP of the comparator 111 changes from high level to low level. In response to the transition of the output COMP of the comparator 111 to the low level, the count value of the counter 120 at that time is stored in the third memory 118 as the second reset signal Ref2, and the write to the third memory 118 is performed. Disable state. At time T1504, the count value of the counter 120 is reset to zero.

  At time T1505, the reference signal RAMP is set to the maximum input voltage Vrmax corresponding to the lower limit of the conversion range of the AD conversion circuit. At time T1506, the direct control pulse PCR is set to the low level, the control switch 114 is turned off, the additional capacitor 105 is disconnected from the floating diffusion layer FD, and the gain of the pixel source follower is higher than the second gain. Set to the first gain.

  Between time T1507 and time T1508, AD conversion of the first reset signal Ref1 that is the reset level of the floating diffusion layer FD is performed with the first gain. First, writing to the first memory 113n is enabled. Then, during the period from time T1507 to time T1508, as the reference signal RAMP, the same ramp wave as that input from time T1503 to time T1504 is input, and at the same time, the counter 120 counts up from the count value 0. At the moment when the voltage of the ramp wave falls below the output voltage Vpix from the pixel circuit 100, the output COMP of the comparator 111 changes from high level to low level. In response to the transition of the output COMP of the comparator 111 to the low level, the count value of the counter 120 at that time is stored in the first memory 113n as the reset signal Ref, and writing to the first memory 113n is disabled. To.

  After time T1509, although not shown, the same operation as from time T210 to time T217 in FIG. 4 is performed to perform AD conversion of the optical signal Sig. Thereafter, the first reset signal Ref1 stored in the first memory 113n, the optical signal Sig stored in the second memory 113s, and the second reset signal Ref2 stored in the third memory 118 are read. As the gain determination value GAIN, 0 is read if the level of the gain setting pulse PGAIN is low, and 1 is read if the level is high, and the signal reading operation from the pixel circuit 100 is terminated.

  The signal readout operation from the pixel circuit 100 described above is repeated until a signal of a desired number of pixels is read out, and a series of signal readout operations from the image sensor 1c is performed.

  With the above read operation, both the first reset signal Ref1 with the first gain and the second reset signal Ref2 with the second gain can be obtained.

  Next, with reference to FIG. 17, the correction process of the signal read from the image sensor 1c will be described. One of the gains of two types of pixel source followers is set for each pixel of the optical signal Sig read by the signal reading operation of the fourth embodiment. Therefore, in the fourth embodiment, depending on which of the first gain and the second gain is set, the reset signal to be subtracted from the optical signal Sig is the first reset signal Ref1 and the second reset signal Ref2. Choose from.

  In S401, the count value i of a counter (not shown) that counts the number of pixels subjected to signal processing is set to 1, and the process proceeds to S402. In S402, the optical signal Sig, the reset signal Ref1, the reset signal Ref2, and the gain determination value GAIN are acquired for the i-th pixel, and the process proceeds to S403.

  In S403, it is determined whether the gain determination value GAIN is zero. If it is 0, it is determined that the pixel source follower is set to the first gain G1, which is a high gain, and the process proceeds to S404. If it is not 0, it is determined that the pixel source follower is set to the second gain G2, which is a low gain. Then, the process proceeds to S405.

  In S404, a correction operation is performed on the optical signal Sig read with the pixel source follower set to the first gain G1, which is a high gain. By subtracting the first reset signal Ref1 read out with the first gain from the optical signal Sig, the variation component of the reset level of the pixel source follower is removed to obtain a corrected signal S for the pixel, and the process proceeds to S406. move on.

  In S405, a correction operation is performed on the optical signal Sig read out with the pixel source follower set to the second gain, which is a low gain. The variation component of the reset level of the pixel source follower is removed by subtracting the second reset signal Ref2 read out with the second gain from the optical signal Sig. Thereafter, gain correction is performed by multiplying the optical signal Sig by the ratio G1 / G2 of the first gain G1 and the second gain G2, thereby obtaining a corrected signal S for the pixel, and the process proceeds to S406.

  The operations in S406 and S407 are the same as the operations described in S106 and S107 in FIG. 5 in the first embodiment, and thus the description thereof is omitted.

  By performing the correction processing as described above, a signal S having the same total gain can be obtained from the image signal 1c and the signal processing unit 2 from the optical signal Sig of each pixel in which the gain of the pixel source follower is set. . One-frame image signals may be generated using the signal S of each pixel thus obtained.

  As described above, in the fourth embodiment, the gain of the pixel source follower is set for each pixel by the amplifying means provided in the pixel circuit, and the reset level of the pixel source follower is read with each settable gain. I made it. This makes it possible to perform highly accurate reset level correction on each pixel signal for which gain has been set independently according to the signal level, and to provide a solid-state imaging device that can further suppress noise. It is.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

  For example, about the 2nd-4th embodiment, the same deformation | transformation as the modification of 1st Embodiment mentioned above is possible.

  1, 1a, 1b, 1c: imaging device, 2: signal processing unit, 3: overall control / calculation unit, 100, 100a, 100b: pixel circuit, 110, 110a, 110b, 110c: column circuit, 103: amplification transistor, 104: capacity addition switch, 105: additional capacity, 111: comparator, 112: gated latch circuit, 113n: first memory, 113s: second memory, 113g, 118: third memory, 114: control switching Switch, 120, 120b: Counter, FD: Floating diffusion layer, I: Current source

Claims (14)

Photoelectric conversion means for generating charge according to the amount of incident light;
A charge storage capacity for storing the charge;
Amplifying means for amplifying a voltage corresponding to the amount of charge stored in the charge storage capacitor and outputting an optical signal;
A plurality of pixel circuits each including
A plurality of AD conversion means including comparison means for comparing the optical signal from the amplification means with a reference signal and outputting a comparison result;
A plurality of gain setting means for setting the gain of the amplifying means;
With
The image pickup device, wherein the gain setting means sets the gain of the amplification means for each of the pixel circuits based on a comparison result of the comparison means corresponding to each pixel circuit. Each pixel circuit has an additional capacitor provided in parallel with the charge storage capacitor, and a switch for connecting / disconnecting the additional capacitor to / from the charge storage capacitor,
2. The gain setting unit according to claim 1, wherein the gain setting unit sets a gain of the amplification unit by controlling a connection between the additional capacitor and the charge storage capacitor by controlling the switch. Image sensor. Each pixel circuit includes a plurality of additional capacitors provided in parallel with the charge storage capacitor, and a plurality of switches for connecting / disconnecting the plurality of additional capacitors to / from the charge storage capacitor, respectively.
2. The gain setting means sets the gain of the amplifying means by controlling connection between each of the plurality of additional capacitors and the charge storage capacitor by controlling the switch. The imaging device described in 1.   The image pickup device according to claim 2 or 3, wherein the gain setting means makes the gain of the amplification means lower by connecting the additional capacitor than when the gain setting means is disconnected. Each of the pixel circuits has an additional capacitor provided in parallel with the charge storage capacitor and capable of continuously changing the capacitance.
The image pickup device according to claim 1, wherein the gain setting unit sets a gain of the amplification unit by controlling a capacitance of the additional capacitor.   The image pickup device according to claim 2, wherein the gain setting unit further reduces the gain of the amplification unit by increasing the capacity of the additional capacitor.   The imaging device according to claim 1, wherein the gain setting unit reduces the gain when the optical signal is smaller than the reference signal.   A signal when the charge storage capacitor is reset is amplified by the amplifying means set with a gain determined in advance by the gain setting means, and the optical signal and the reset signal are respectively output from the AD converter. 5. The image pickup device according to claim 1, further comprising a control unit that controls to output a signal AD-converted by the unit and information indicating the set gain. 6. .   A signal when the charge storage capacitor is reset, a plurality of reset signals that are amplified and output by the amplifying unit with a plurality of gains that can be set by the gain setting unit, and the optical signal, respectively. 5. The control device according to claim 1, further comprising a control unit that controls to output a signal AD-converted by the AD conversion unit and information indicating the set gain. 6. Image sensor.   10. The image pickup device according to claim 1, wherein the AD conversion unit and the gain setting unit are arranged for each of a predetermined number of pixel circuits. 11. The plurality of pixel circuits are arranged in a matrix,
The image pickup device according to claim 10, wherein the AD conversion unit and the gain setting unit are arranged corresponding to each column.   12. The device according to claim 1, wherein the plurality of pixel circuits, the plurality of AD conversion units, and the plurality of gain setting units are arranged on a plurality of different substrates. Image sensor. The image sensor according to claim 7 or 8,
Correction means for correcting the gain so that the gain of the optical signal corresponding to the plurality of pixel circuits is uniform based on the information indicating the set gain with respect to the optical signal output from the imaging device; An imaging device comprising:   The imaging apparatus according to claim 13, wherein the correction unit further corrects noise of the optical signal of each pixel circuit based on the reset signal of each pixel circuit.

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