JP2018200625A - Design support device, design support method and program - Google Patents

Abstract

To improve efficiency of arrangement of an interlayer connection section connecting a wiring layer and other wiring layer.SOLUTION: A design support device supports a design of a multilayer substrate having a plurality of wiring layers. The design support device includes a generation section which generates an interlayer connection section for making a connection to the other wiring layer out of the plurality of wiring layers from a wiring pattern in the selected wiring layer out of the plurality of wiring layers. The generation section presents a candidate which guarantees so as not to generate an error to a user as a condition for generating the interlayer connection section (1002), and generates the interlayer connection section according to the condition specified by the user based on the candidate.SELECTED DRAWING: Figure 12

Description

  The present invention relates to a design support apparatus, a design support method, and a program for supporting the design of a multilayer board having a plurality of wiring layers.

  In order to design a multilayer substrate having a plurality of wiring layers, a design support apparatus can be generally used. In the design of a multilayer board, an interlayer connection (via) for connecting one wiring layer and another wiring layer can be arranged. In general, the interlayer connection portion extends in a direction perpendicular to the wiring layer. In Patent Document 1, when a start layer to which one end of a via is connected and a termination layer to which the other end of the via is selected are selected, arrangement of at least one of the layers from the start layer to the termination layer A CAD design apparatus that displays an image superimposed on an arrangement image of a start layer is described.

JP 2011-59812 A

  In the CAD design apparatus described in Patent Document 1, the user can freely select a termination layer from among a plurality of layers constituting the multilayer substrate. Therefore, in the CAD design apparatus described in Patent Document 1, a layer that cannot originally arrange a via correctly can be selected by the user as a termination layer. Note that Patent Document 1 describes that an existing arrangement is pushed away when a via is arranged, but it is not always possible to push away. Therefore, when push-out is impossible, it is necessary to change the via placement position or the termination layer, which is inefficient.

  On the other hand, in the conventional configuration in which vias are connected vertically to the wiring pattern, there is another problem in that noise can be radiated from the connection portion between the wiring pattern and the via.

  The present invention has been made on the basis of recognition of the above problems, and it is possible to improve the efficiency of the arrangement process of the interlayer connection part that connects the wiring layer and another wiring layer, or between the wiring pattern and the interlayer connection part. The object is to reduce the emission of noise from the connection.

  A first aspect of the present invention addresses the former problem and relates to a design support apparatus for supporting the design of a multi-layer substrate having a plurality of wiring layers, wherein the design support apparatus includes the plurality of wirings. A generation unit for generating an interlayer connection for connecting the wiring pattern in the selected wiring layer of the layers to another wiring layer among the plurality of wiring layers, and the generation unit includes the interlayer connection As a condition for generating the error, a candidate guaranteed not to generate an error is presented to the user, and the interlayer connection unit is generated according to a condition specified by the user based on the candidate.

  A second aspect of the present invention addresses the latter problem and relates to a design support apparatus for designing a multilayer substrate having a plurality of wiring layers, wherein the design support apparatus includes a plurality of wiring layers. A generating unit for generating an interlayer connection for connecting the wiring pattern in the selected wiring layer to another wiring layer among the plurality of wiring layers, the generating unit including the wiring pattern and the interlayer The interlayer connection portion is generated so that the connection portion with the connection portion is configured by a curve in a cross section perpendicular to the main surface of the multilayer substrate.

  The third aspect of the present invention corresponds to the former or the latter problem, and relates to a program that causes a computer to operate as the design support apparatus according to the first aspect or the second aspect.

  A fourth aspect of the present invention addresses the former problem and relates to a design support method for supporting the design of a multilayer substrate having a plurality of wiring layers, the design support method including the plurality of wirings. Including a step of generating an interlayer connection for connecting to another wiring layer among the plurality of wiring layers from a wiring pattern in a selected wiring layer of the layers, wherein the interlayer connection is generated in the step As a condition for this, a candidate that is guaranteed not to generate an error is presented to the user, and the interlayer connection unit is generated according to a condition specified by the user based on the candidate.

  A fifth aspect of the present invention addresses the latter problem and relates to a design support method for supporting the design of a multilayer substrate having a plurality of wiring layers, the design support method including the plurality of wirings. Including a step of generating an interlayer connection for connecting to another wiring layer among the plurality of wiring layers from a wiring pattern in a selected wiring layer of the layers, wherein the interlayer connection is generated in the step As a condition for this, a candidate that is guaranteed not to generate an error is presented to the user, and the interlayer connection unit is generated according to a condition specified by the user based on the candidate.

  According to the present invention, the arrangement process of the interlayer connection portion that connects the wiring layer and another wiring layer is made efficient, or the emission of noise from the connection portion between the wiring pattern and the interlayer connection portion is reduced.

The figure which shows the structure of the design assistance apparatus of preferable embodiment of this invention. The figure which shows typically an example of the cross-section of the multilayer substrate which has a some wiring layer. The figure explaining the process which generate | occur | produces an interlayer connection part in vertical connection mode. The figure explaining the process which generate | occur | produces an interlayer connection part in vertical connection mode. The figure explaining the process which generate | occur | produces an interlayer connection part in diagonal connection mode. The figure explaining the process which generate | occur | produces an interlayer connection part in diagonal connection mode. The figure explaining the process which generate | occur | produces an interlayer connection part in diagonal connection mode. The figure explaining the process which generate | occur | produces an interlayer connection part in diagonal connection mode. The figure which illustrates the setting screen for setting the generation conditions of an interlayer connection part. The figure which illustrates the setting screen for setting the generation conditions of an interlayer connection part. The figure which illustrates the screen which provides a user with the candidate which can be specified as conditions for generating an interlayer connection part in vertical connection mode. The figure which illustrates the screen which provides a user with the candidate (candidate of the wiring layer which can arrange | position an end point) which can be specified as conditions for generating an interlayer connection part in diagonal connection mode. The figure which illustrates the screen which provides a user with the candidate (candidate of the position which can arrange | position an end point) which can be specified as conditions for generating an interlayer connection part in diagonal connection mode. The figure which illustrates the screen which provides a user with the candidate (candidate of the position which can arrange | position an end point) which can be specified as conditions for generating an interlayer connection part in diagonal connection mode. The figure which illustrates the generation process of the interlayer connection part performed by the generation part. The figure which illustrates the setting screen for setting the generation conditions of an interlayer connection part. The figure which illustrates the screen which provides a user with the candidate (candidate of the position which can arrange | position an end point) which can be specified as conditions for generating an interlayer connection part in perpendicular | vertical or diagonal connection mode.

  Hereinafter, the present invention will be described through exemplary embodiments thereof with reference to the accompanying drawings.

  FIG. 1 shows a configuration of a design support apparatus 100 according to a preferred embodiment of the present invention. The design support apparatus 100 can be typically configured by incorporating the program 112 into a general-purpose or dedicated computer (information processing apparatus). The design support apparatus 100 operates as an apparatus (CAD) that supports the design of a multilayer board having a plurality of wiring layers.

  The design support apparatus 100 or the computer may include, for example, an auxiliary memory 110, a CPU (processor) 120, a main memory 130, a display 140, and an input unit 160. The auxiliary memory 110 is composed of, for example, a non-volatile memory such as a hard disk drive, EEPROM, or magnetoresistive memory, and can store a program 112. The CPU 120 operates according to the program 112 and causes the design support apparatus 100 to have the functions of the generation unit 122 (or the generation unit 122 and the data generation unit 124). The main memory 130 is composed of, for example, a volatile memory, and provides a work area to the CPU 120. The input unit 160 constitutes a user interface for the user, and may include, for example, a keyboard and a pointing device (mouse, touchpad, etc.).

  The generation unit 122 generates an interlayer connection unit for performing connection from a wiring pattern in a selected wiring layer of the plurality of wiring layers to another wiring layer of the plurality of wiring layers from a user via a user interface. Occurs according to the instructions. The generation unit 122 presents to the user a candidate that is guaranteed not to generate an error as a condition for generating the interlayer connection, and generates the interlayer connection according to the condition specified by the user based on the candidate. . Candidates that are guaranteed not to cause an error can be provided to the user via a display on display 140. The user can specify a condition for generating an interlayer connection based on the candidates displayed on the display 140. The designation of the condition can be made, for example, by selecting one candidate from the plurality of candidates when a plurality of candidates are presented to the user via display on the display 140. Alternatively, the condition can be specified through specification of a position in the specifiable area. Thus, by presenting to the user candidates that are guaranteed not to cause an error, it is possible to eliminate the need for reworking and to improve the efficiency of the arrangement process of the interlayer connection portion.

  Here, the error may be an error discovered in DRC (design rule check), for example. Guaranteeing that no errors will occur can be done by searching for conditions that can comply with the design rules. For example, a plurality of preliminary candidates are determined, DRC is performed on the plurality of preliminary candidates, and the preliminary candidate that has passed the preliminary candidates is determined as a candidate that is guaranteed not to generate an error. it can.

  The generation unit 122 generates an interlayer connection, generates a wiring pattern for each of the plurality of wiring layers, and synthesizes the wiring pattern data of the interlayer connection and the plurality of wiring layers. Data can be generated.

  The data generation unit 124 can generate manufacturing data for manufacturing the multilayer substrate 1 based on the design data of the multilayer substrate 1 generated by the design support apparatus 100. The manufacturing data can include, for example, data for manufacturing the multilayer substrate 1 by a 3D printer. Alternatively, the manufacturing data can include wiring pattern data and drill data for manufacturing the multilayer substrate 1 by a normal manufacturing method.

  FIG. 2 schematically shows an example of a cross-sectional structure in the design stage of the multilayer substrate 1 having a plurality of wiring layers. In this example, the plurality of wiring layers are composed of the first to tenth wiring layers, but the number of layers is arbitrary. In the example shown in FIG. 2, the plurality of wiring layers include wiring patterns P1 to P8. The state illustrated in FIG. 2 is a state in which an interlayer connection portion is to be added starting from a part of the wiring pattern P3 arranged in the fifth wiring layer (selected wiring layer).

  The generating unit 122 extends in a vertical connection mode (first mode) for generating an interlayer connection so as to extend in a direction perpendicular to the main surface PF of the multilayer substrate 1 and in an oblique direction with respect to the main surface PF. As described above, an oblique connection mode (second mode) for generating an interlayer connection portion is provided. The start point SP may be an end portion of the wiring pattern P3, or may be a portion other than the end portion.

  The vertical connection mode (first mode) will be described with reference to FIGS. 3 and 4, a part of the wiring pattern P3 arranged in the fifth wiring layer (selected wiring layer) is used as a starting point SP, and the eighth wiring layer (other wiring layers) It is exemplarily shown that the interlayer connection IC is arranged with the position having the same coordinates as the start point SP as the end point EP. In the first mode, the interlayer connection IC is generated so as to extend in a direction perpendicular to the main surface PF. Accordingly, the eighth wiring layer is designated as the wiring layer in which the end point EP is to be arranged after the designation of the starting point SP in the wiring pattern P3 arranged in the fifth wiring layer. An end point EP having coordinates is arranged in the eighth wiring layer. The start point SP is the start point of the interlayer connection IC, and the end point EP is the end point of the interlayer connection IC, in other words, the connection position of the interlayer connection IC in the eighth wiring layer.

  The oblique connection mode (second mode) will be described with reference to FIGS. In FIGS. 5 and 6, a part of the wiring pattern P3 arranged in the fifth wiring layer (selected wiring layer) is used as a starting point SP, and the eighth wiring layer (other wiring layers) It is exemplarily shown that the interlayer connection IC is arranged with the position having coordinates different from the start point SP as the end point EP. In the second mode, the interlayer connection IC is generated so as to extend in an oblique direction with respect to the main surface PF. Therefore, a position having coordinates different from the start point SP is designated as the end point EP. The start point SP is the start point of the interlayer connection part IC, and the end point EP is the end point of the interlayer connection part IC.

  At least one of the vertical connection mode (first mode) and the diagonal connection mode (second mode) may have a curved connection mode and a straight connection mode as sub-modes. Hereinafter, the curved connection mode in the oblique connection mode will be exemplified, but also in the curved connection mode in the vertical connection mode, the generation unit 122 is curved in a cross section in which the connection portion between the wiring pattern and the interlayer connection portion is perpendicular to the main surface PF. An interlayer connection portion is generated so as to be configured as follows.

  In the curved connection mode in the oblique connection mode, as illustrated in FIG. 6, the generation unit 122 has a connection part between the wiring pattern P3 of the fifth wiring layer and the interlayer connection part IC perpendicular to the main surface PF. The interlayer connection IC is generated so as to have a curve in the cross section. The curve is preferably, for example, an arc. Here, the connection part with the interlayer connection part IC in the wiring pattern P3 may also be modified so as to be configured with a curve in the cross section. In this way, by generating the interlayer connection portion so that the connection portion between the wiring pattern of the wiring layer and the interlayer connection portion is configured with a curve in the cross section, compared to the case where the connection portion is connected in a polygonal line shape , Noise emission from the connection portion can be reduced.

  The curved connection mode is advantageous when the multilayer substrate 1 is manufactured by a 3D printer. On the other hand, when the multilayer substrate 1 is manufactured by a normal manufacturing method (lamination of a wiring layer and an insulating layer), it is preferable that the linear connection mode is adopted because the interlayer connection portion is formed through drilling. Although not shown, in the straight line connection mode, the interlayer connection IC is configured with a straight line.

  The oblique connection mode (second mode) will be further described with reference to FIGS. 7 and 8, a part of the wiring pattern P3 arranged in the fifth wiring layer (selected wiring layer) is set as the starting point SP, and arranged in the eighth wiring layer (other wiring layers). It is exemplarily shown that the interlayer connection portion IC is arranged with a part of the wiring pattern P3 ′ as an end point EP. Here, the wiring pattern P3 and the wiring pattern P3 'are wiring patterns constituting the same node in the electrical circuit design corresponding to the multilayer substrate 1 (that is, wiring patterns to be connected to each other). The start point SP is the start point of the interlayer connection part IC, and the end point EP is the end point of the interlayer connection part IC. When the curve connection mode is applied to such an example, the generation unit 122 generates the wiring pattern P3 of the fifth wiring layer and the connection portion between the interlayer connection IC and the wiring pattern P3 ′ of the eighth wiring layer. Interlayer connection portion IC is generated such that both of the connection portions with the interlayer connection portion IC are configured by curves in a cross section perpendicular to main surface PF.

  In addition, when the wiring pattern P3 of the eighth wiring layer is disposed after the generation of the interlayer connection IC, the generation unit 122 connects the wiring pattern P3 ′ of the eighth wiring layer to the interlayer connection IC. The interlayer connection IC may be deformed so that the portion is configured with a curve in a cross section perpendicular to the main surface PF.

  FIG. 9 illustrates a setting screen 901 that can be displayed on the display 140 by the generation unit 122. The setting screen 901 is a screen for the user to set the generation condition of the interlayer connection unit 11. The setting screen 901 can include setting units 911 and 912. The setting unit 911 determines whether the generation unit 122 selects a presentation mode in which the generation unit 122 presents a candidate guaranteed not to generate an error to the user or a non-presentation mode in which such a presentation is not performed. Can be used to let the user decide. When “present” is checked, the presentation mode is selected, and when “not present” is checked, the non-presentation mode is selected.

  The setting unit 912 can be used by the generating unit 122 to determine whether to select the vertical connection mode or the diagonal connection mode. When “vertical” is checked, the vertical connection mode is selected, and when “diagonal” is checked, the diagonal connection mode is selected. FIG. 9A illustrates a state where the presentation mode and the vertical connection mode are selected. FIG. 9B illustrates a state where the presentation mode and the oblique connection mode are selected.

  FIG. 10 illustrates a setting screen 920 that can be displayed on the display 140 by the generation unit 122. The setting screen 920 is a screen for the user to set the generation conditions of the interlayer connection unit 11. More specifically, the setting screen 920 is a screen for allowing the user to determine which of the curved connection mode and the straight connection mode is selected as a sub mode of the vertical connection mode and the oblique connection mode. When “Yes” is checked, the curve connection mode is selected, and when “No” is checked, the straight line connection mode is selected.

  FIG. 11 illustrates a screen 1001 in which the generation unit 122 provides the user with candidates that can be specified as conditions for generating the interlayer connection IC in the vertical connection mode. The screen 1001 can be displayed on the display 140 in a state where the start point SP is designated in the fifth wiring layer. O is a wiring layer in which the end point of the interlayer connection IC can be arranged, in other words, a wiring layer (candidate) that is guaranteed not to generate an error. X is a wiring layer in which the end point of the interlayer connection IC cannot be arranged, in other words, a wiring layer that is not guaranteed not to generate an error. The user can select a wiring layer marked with ○.

  FIG. 12 illustrates a screen 1002 in which the generation unit 122 provides the user with candidates (candidates for wiring layers on which the end point EP can be placed) that can be specified as conditions for generating the interlayer connection IC in the oblique connection mode. ing. The screen 1002 can be displayed on the display 140 in a state where the start point SP is designated in the fifth wiring layer. O is a wiring layer in which the end point of the interlayer connection IC can be arranged, in other words, a wiring layer (candidate) that is guaranteed not to generate an error. X is a wiring layer in which the end point of the interlayer connection IC cannot be arranged, in other words, a wiring layer that is not guaranteed not to generate an error. The user can select a wiring layer marked with ○.

  FIG. 13 illustrates a screen 1010 in which the generation unit 122 provides the user with candidates (candidate positions where the end point EP can be placed) that can be specified as conditions for generating the interlayer connection IC in the oblique connection mode. Yes. The screen 1010 can arrange the end point EP (connection position) of the interlayer connection IC when the wiring layer (other wiring layer) designated as the connection destination of the interlayer connection IC is the eighth wiring layer. An area (that is, a plurality of position candidates that can be the end point EP) is presented to the user. In the example shown in FIG. 13, the region where the end point EP (connection position) of the interlayer connection IC can be arranged is shown as a region surrounded by a dotted line.

  FIG. 14 illustrates a screen 1020 in which the generation unit 122 provides the user with candidates (candidate positions where the end point EP can be arranged) that can be specified as conditions for generating the interlayer connection IC in the oblique connection mode. Yes. The screen 1020 can arrange the end point EP (connection position) of the interlayer connection IC when the wiring layer (other wiring layer) designated as the connection destination of the interlayer connection IC is the sixth wiring layer. An area (that is, a plurality of position candidates that can be the end point EP) is presented to the user. In the example shown in FIG. 14, the region where the end point EP (connection position) of the interlayer connection IC can be arranged is shown as a region surrounded by a dotted line.

  As illustrated in FIGS. 13 and 14, generally, a wiring layer far from the wiring layer where the starting point SP of the interlayer connection part IC is arranged is selected as the wiring layer where the end point EP of the interlayer connection part IC is to be arranged. The area where the end point EP can be arranged becomes narrower as the distance is increased. This is because the wiring pattern arranged in the wiring layer between the wiring layer where the start point SP is arranged and the wiring layer where the end point EP is to be arranged restricts the arrangement of the interlayer connection IC.

  FIG. 15 illustrates the generation process of the interlayer connection unit executed by the generation unit 122. The generation process of the interlayer connection portion shown in FIG. 15 is started in response to the generation unit 122 receiving a request for generation of the interlayer connection portion from the user in the design of the multilayer substrate 1. The generation request for the interlayer connection portion can be generated, for example, by selecting a command for requesting the generation of the interlayer connection portion from the edit command menu displayed on the display 140. The start point SP can be, for example, the position of the cursor (position pointed by the pointing device) in the wiring layer that is to be edited when the command is generated. The various modes described with reference to FIGS. 9 and 10 are set in advance by the user or as default settings.

  In step S102, the generation unit 122 determines whether the presentation mode is set or the non-presentation mode is set. If the presentation mode is set, the process proceeds to step S103, where the non-presentation mode is set. If yes, the process proceeds to step S109.

  In step S <b> 103, the generation unit 122 presents to the user candidates that are guaranteed not to cause an error as a condition for generating the interlayer connection unit according to the set mode. In step S104, the user designates a condition for generating an interlayer connection based on the presented candidates. The designation of the condition may be, for example, selecting one candidate from a plurality of candidates for the wiring layer (other wiring layer) to which the interlayer connection IC is connected. Alternatively, the specification of this condition may be an area where the end point EP (connection position) of the interlayer connection IC can be specified in the wiring layer (other wiring layer) to which the interlayer connection IC is connected (that is, the end point EP). The end point EP (connection position) in a plurality of possible position candidates) can be specified. In step S105, the generation unit 122 determines whether there is a lower-layer candidate, that is, whether there is a condition that should be further specified as a condition for generating the interlayer connection unit. If there is a lower layer candidate, the process returns to step S103, and steps S103 and S104 are further executed. On the other hand, if there is no lower layer candidate, the process proceeds to step S106.

  One example of steps S103 to S105 will be described with reference to FIG. Here, it is assumed that the generation request of the interlayer connection portion IC connected to the wiring pattern P3 arranged in the fifth wiring layer is made in step S101 in the state where the presentation mode and the vertical connection mode are selected. . In step S103, as illustrated in FIG. 11, the generation unit 122 generates a wiring layer candidate (error) as a connection destination of the interlayer connection IC having a part SP of the wiring pattern P3 of the fifth wiring layer as a starting point SP. Information indicating the fourth, sixth, seventh, and eighth wiring layers is presented as a candidate that is guaranteed not to generate the above. Here, the fifth wiring layer is a wiring layer in which the starting point SP of the interlayer connection IC is disposed.

  In step S104, the user selects a wiring layer that is a connection destination of the interlayer connection part IC starting from a part of the wiring pattern P3 of the fifth wiring layer from among the one or more candidates presented. be able to. In step S104, the generation unit 122 selects the wiring layer selected by the user as a wiring layer that is a connection destination of the interlayer connection part IC that starts from a part of the wiring pattern P3 of the fifth wiring layer. In this example, since it is the vertical connection mode, there is no lower layer candidate. Therefore, in step S105, the generation unit 122 determines that there is no lower layer candidate and proceeds to step S106.

  With reference to FIG. 12, FIG. 13, the other example of process S103-S105 is demonstrated. Here, it is assumed that the generation request of the interlayer connection portion IC connected to the wiring pattern P3 arranged in the fifth wiring layer is made in step S101 in the state where the presentation mode and the oblique connection mode are selected. . In step S103, as illustrated in FIG. 12, the generation unit 122 generates a wiring layer candidate (error) that is a connection destination of the interlayer connection IC having a part SP of the wiring pattern P3 of the fifth wiring layer as a starting point SP. Information indicating the third, fourth, sixth, seventh, eighth, and ninth wiring layers is presented as a candidate that is guaranteed not to generate the Here, the fifth wiring layer is a wiring layer in which the starting point SP of the interlayer connection IC is disposed. In the oblique connection mode, the end point EP (connection position) of the interlayer connection part IC is arranged even in a wiring layer in which a wiring pattern (wiring pattern constituting another node) is already arranged at the same coordinates as the start point SP. There are cases where it is possible. Therefore, in the oblique connection mode, there are more wiring layers as candidates for the connection destination of the interlayer connection portion IC than in the vertical connection mode.

  In step S104, the user selects a wiring layer that is a connection destination of the interlayer connection part IC starting from a part of the wiring pattern P3 of the fifth wiring layer from among the one or more candidates presented. be able to. Here, as an example, it is assumed that the eighth wiring layer is selected by the user. In step S104, the generation unit 122 connects the interlayer connection IC with the wiring layer (eighth wiring layer) selected by the user as a starting point SP that is a part of the wiring pattern P3 of the fifth wiring layer. Select as the previous wiring layer. In this example, since it is in the oblique connection mode, there is a lower-layer candidate, and the process proceeds from step S105 to step S103.

  In the second step S103, the generation unit 122 displays the screen 1010 illustrated in FIG. The screen 1010 is an area in which the end point EP (connection position) of the interlayer connection IC can be specified in the eighth wiring layer that is the wiring layer (other wiring layer) specified as the connection destination of the interlayer connection IC (that is, , A plurality of position candidates that can be the end point EP) are presented to the user. In the example shown in FIG. 13, the region where the end point EP (connection position) of the interlayer connection IC can be specified is shown as a region surrounded by a dotted line.

  In the second step S <b> 104, the user specifies an arbitrary position in the area surrounded by the dotted line with the input unit 160 (for example, a pointing device). In the second step S104, the generation unit 122 specifies the position specified by the user as the end point EP (connection position) of the interlayer connection IC in the eighth wiring layer. Next, in the second step S105, the generation unit 122 determines that there is no lower layer candidate, and proceeds to step S106.

  In step S106, the generation unit 122 determines whether the curve connection mode is set or the straight line connection mode is set. If the curve connection mode is set, the process proceeds to step S107. If the straight line connection mode is set, the process proceeds to step S108. In step S107, the generation unit 122 generates the interlayer connection IC in the curve connection mode, and in step S08, the generation unit 122 generates the interlayer connection IC in the straight line connection mode. In step S109, the generation unit 122 generates an interlayer connection unit in accordance with an instruction from the user.

  Hereinafter, modifications of the above embodiment will be described. FIG. 16 illustrates a setting screen 902 that can be displayed on the display 140 by the generation unit 122. The setting screen 902 is a screen for the user to set the generation condition of the interlayer connection unit 11. The setting screen 902 can include setting units 911 and 913. The setting unit 911 determines whether the generation unit 122 selects a presentation mode in which the generation unit 122 presents a candidate guaranteed not to generate an error to the user or a non-presentation mode in which such a presentation is not performed. Can be used to let the user decide. When “present” is checked, the presentation mode is selected, and when “not present” is checked, the non-presentation mode is selected.

  The setting unit 913 can be used by the generation unit 122 to determine whether the user selects the vertical connection mode, the diagonal connection mode, or the vertical or diagonal connection mode. When “vertical” is checked, the vertical connection mode is selected, and when “diagonal” is checked, the diagonal connection mode is selected. When “Vertical or diagonal” is checked, the vertical or diagonal connection mode is selected. In the vertical or oblique connection mode, the generation unit 122 selects an interlayer connection portion extending in a direction perpendicular to the main surface PF of the multilayer substrate 1 or an interlayer connection portion extending in a direction oblique to the main surface PF according to selection by the user. generate.

  FIG. 17 illustrates a screen 1030 in which the generation unit 122 provides the user with candidates (candidate positions where the end point EP can be placed) that can be specified as conditions for generating the interlayer connection IC in the vertical or oblique connection mode. Has been. The screen 1030 can arrange the end point EP (connection position) of the interlayer connection IC when the wiring layer (other wiring layer) designated as the connection destination of the interlayer connection IC is the eighth wiring layer. An area (that is, a plurality of position candidates that can be the end point EP) is presented to the user. In the example shown in FIG. 17, the region where the end point EP (connection position) of the interlayer connection IC can be arranged is shown as a region surrounded by a dotted line.

  It can be seen that the dispositionable area shown in FIG. 17 is wider than the dispositionable area shown in FIG. In the vertical or oblique connection mode, the interlayer connection portion can be generated so as to extend in a direction perpendicular to the main surface PF of the multilayer substrate 1 or extend in a direction oblique to the main surface PF. This is because an interlayer connection can also be generated.

1: multilayer substrate, PF: main surface, P1 to P8: wiring pattern, SP: start point, EP: end point, IC: interlayer connection

Claims (14)

A design support apparatus for supporting the design of a multilayer board having a plurality of wiring layers,
A generator for generating an interlayer connection for connecting to a wiring pattern in the plurality of wiring layers from a wiring pattern in a wiring layer selected from the plurality of wiring layers;
The generation unit presents to the user a candidate that is guaranteed not to generate an error as a condition for generating the interlayer connection unit, and determines the interlayer connection unit according to a condition specified by the user based on the candidate. Occur,
A design support apparatus characterized by that. The generation unit presents information indicating a wiring layer that can be designated as the other wiring layer among the plurality of wiring layers as the candidate, and uses the wiring layer designated by the user as the other wiring layer. Determining and generating the interlayer connection to connect the wiring pattern and the other wiring layer,
The design support apparatus according to claim 1, wherein: The generation section generates the interlayer connection portion so as to extend in a direction perpendicular to the main surface of the multilayer substrate, and the interlayer connection extends in an oblique direction with respect to the main surface. Having a plurality of modes including a second mode for generating a part, generating the candidate to follow a mode selected by the user among the plurality of modes, and presenting the candidate to the user
The design support apparatus according to claim 1 or 2, characterized in that When the second mode is selected, the generation unit presents, as the candidate, an area that can be designated as the connection position of the interlayer connection part in the other wiring layer, and is designated by the user in the area. The interlayer connection portion is generated so as to connect the wiring pattern and the connection position, with the made position as the connection position.
The design support apparatus according to claim 3. When the second mode is designated, the generation unit generates the interlayer connection portion so that a connection portion between the wiring pattern and the interlayer connection portion is configured by a curve in a cross section perpendicular to the main surface. To
The design support apparatus according to claim 4. When the second mode is designated, the generation unit is configured such that the connection part between the wiring pattern of the other wiring layer and the interlayer connection part is configured with a curve in a cross section perpendicular to the main surface. Generate interlayer connection,
The design support apparatus according to claim 5. The generation unit generates the interlayer connection portion such that a connection portion between the wiring pattern of the other wiring layer and the interlayer connection portion is configured by a curve in a cross section perpendicular to the main surface of the multilayer substrate.
The design support apparatus according to claim 1 or 2, characterized in that The generating unit generates a wiring pattern of each of the plurality of wiring layers, and generates design data obtained by synthesizing data of the wiring patterns of the interlayer connection unit and the plurality of wiring layers.
The design support apparatus according to any one of claims 1 to 6, wherein the design support apparatus includes:   The design support apparatus according to claim 8, further comprising a data generation unit that generates manufacturing data for manufacturing the multilayer substrate based on the design data. The manufacturing data includes data for manufacturing the multilayer substrate by a 3D printer.
The design support apparatus according to claim 9. A design support apparatus for designing a multilayer substrate having a plurality of wiring layers,
A generator for generating an interlayer connection for connecting to a wiring pattern in the plurality of wiring layers from a wiring pattern in a wiring layer selected from the plurality of wiring layers;
The generation unit generates the interlayer connection portion such that a connection portion between the wiring pattern and the interlayer connection portion is configured with a curve in a cross section perpendicular to the main surface of the multilayer substrate.
A design support apparatus characterized by that.   A program for operating a computer as the design support apparatus according to any one of claims 1 to 11. A design support method for supporting the design of a multilayer substrate having a plurality of wiring layers,
Including a step of generating an interlayer connection portion for performing connection from a wiring pattern in the selected wiring layer among the plurality of wiring layers to another wiring layer among the plurality of wiring layers,
In the step, as a condition for generating the interlayer connection, a candidate guaranteed not to generate an error is presented to the user, and the interlayer connection is generated according to a condition designated by the user based on the candidate To
A design support method characterized by that. A design support method for supporting the design of a multilayer substrate having a plurality of wiring layers,
Including a step of generating an interlayer connection portion for performing connection from a wiring pattern in the selected wiring layer among the plurality of wiring layers to another wiring layer among the plurality of wiring layers,
In the step, as a condition for generating the interlayer connection, a candidate guaranteed not to generate an error is presented to the user, and the interlayer connection is generated according to a condition designated by the user based on the candidate To
A design support method characterized by that.

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