JP2018110231A - IGBT semiconductor structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IGBT semiconductor structure.SOLUTION: An IGBT semiconductor structure comprises: a psubstrate; a nlayer; at least one p region contacting with the nlayer; at least one nregion contacting with the p region; a dielectric layer; and three terminal contacts. The psubstrate, the nlayer, the p region, and the nregion respectively contains GaAs compound or are respectively made from the GaAs compound. A first pn junction is formed by the p region and the nlayer. A second pn junction is formed by nlayer and at least one p region. The dielectric layer covers the first pn junction and the second junction. The second terminal contact is formed on the dielectric layer as a field plate. An interlayer is arranged between the psubstrate and the nlayer in which a layer thickness (D3) is 1 μm-50 μm and dopant concentration is 10-10cm, and the interlayer is doped. The interlayer is connected by the material bonding with at least the psubstrate.SELECTED DRAWING: Figure 1

Description

The present invention relates to an IGBT semiconductor structure comprising a p ⁺ substrate, an n ⁻ layer, a p region, an n ⁺ region, a dielectric layer and three terminal contacts.

  Various embodiments of IGBTs are known from Josef Lutz et al. "Semiconductor Power Devices" Springer Verlag, 2011, ISBN 978-3-642-11124-2, Chapter 10, pages 322, 323, and 330. is there. Such power devices are manufactured on the basis of silicon or SiC.

Has a GaAs-based semiconductor diode p ⁺ -n-n ⁺ is to have a p-n-i-p transistor and high withstand voltage and a high pressure resistance, the German Ashkinazi "GaAs Power Devices" , ISBN 965-7094-19-4, Chapter 5, page 97 to Chapter 7.8, page 225.

  The deposition of oxide layers based on GaAs, for example using the Atomic Layer Deposition (ALD) method, is described in M.C. Xu et al., “New Insight into Fermi-Level Unpinning on GaAs: Impact of Different Surface Orientations”, Electron Device Meeting (IEDM), pp. 9-65, IE68, pp. 9-65. K. Dalapati et al., “Impact of Buffer Layer on Atomic Layer Deposited TiAlO Alloy Dielectric Quality for Epitaxy ElectonElectric Application 60, no. 1, 2013.

  Based on this background, the object of the present invention is to provide a device which is a further development of the prior art.

  This problem is solved by an IGBT semiconductor structure having the features of claim 1. Advantageous configurations of the invention are the subject matter of the dependent claims.

  In accordance with the subject of the present invention, there is provided an IGBT semiconductor structure comprising an upper surface and a lower surface.

The IGBT semiconductor structure has a p ⁺ substrate formed on the lower surface of the IGBT semiconductor structure, and an n ⁻ layer placed on the p ⁺ substrate.

The n ⁻ layer has a p region that is in contact with it, and at least one n ⁺ region that is in contact with the p region.

  In particular, it has a dielectric layer of deposited oxide, a first terminal contact, a second terminal contact, and a third terminal contact that are conductively connected to the lower surface of the IGBT semiconductor structure.

The p ⁺ substrate has a dopant concentration of 5 × 10 ^{18 to} 5 × 10 ²⁰ cm ⁻³ and a layer thickness of 50 to 500 μm.

The n ⁻ layer has a dopant concentration of 10 ¹² to 10 ¹⁷ cm ⁻³ and a layer thickness of 10 to 300 μm.

At least one p-region has a dopant concentration of 10 ¹⁴ to 10 ¹⁸ cm ⁻³ and at least one n ⁺ region has a dopant concentration of at least 10 ¹⁹ cm ⁻³ , wherein at least One p region forms a first pn junction with the n ⁻ layer.

The n ⁺ region forms a second pn junction with the p region.

The p ⁺ substrate, the n ⁻ layer, the p region, and the n ⁺ region each contain a GaAs compound or are each made of a GaAs compound.

  The first terminal contact, the second terminal contact, and the third terminal contact each contain a metal or a metal compound, or each consist of a metal or a metal compound, wherein the second terminal contact is a field plate Are formed on the dielectric layer.

The third terminal contact is conductively connected to at least one p region and at least one n ⁺ region.

  In particular, the terminal contacts are each arranged on the surface of the semiconductor structure.

The dielectric layer covers at least the first pn junction and the second pn junction and is coupled to the n ⁻ layer, p region, and n ⁺ region by material bonding.

In addition, a doped intermediate layer is disposed between the p ⁺ substrate and the n ⁻ layer, having a layer thickness of 1 μm to 50 μm and a dopant concentration of 10 ¹² to 10 ¹⁷ cm ^−3. In this case, the intermediate layer is bonded to at least the p ⁺ substrate by material bonding.

  Note that the second terminal contact is referred to as the gate. The first terminal contact is typically referred to as the collector or anode, while the third terminal contact is referred to as the emitter or cathode.

  It is understood that the terminal contact is formed as a layer. Each terminal contact is electrically conductive and has metallic properties and includes, among other things, a metallic and conductive semiconductor layer or metal layer or a combination of the two layers, or such Consists of layers. The terminal contact forms an electrically low resistance contact with the doped semiconductor layer that is in direct contact.

  Furthermore, it is understood that the terminal contacts are connected to contact fingers, so-called pins, in particular using bonding wires.

  Furthermore, it is understood that the intermediate layer has at least a different dopant concentration as compared to the layer in contact therewith.

  Advantageously, the GaAs semiconductor structure has an effective mass with less charge compared to silicon. Further, as compared with Si, a higher temperature can be achieved at the pn junction without destroying the element. Thereby, using a GaAs semiconductor structure, a high switching frequency and a low loss can be achieved compared to an equivalent Si semiconductor structure.

  A further advantage is that the III-IV IGBT semiconductor structure can be manufactured cheaper than an equivalent semiconductor structure made of SiC.

  Another advantage of the III-V IGBT semiconductor structure according to the present invention is high temperature resistance up to 300 ° C. In other words, the III-V group semiconductor diode can be used even in a high temperature environment.

In the first embodiment, the intermediate layer is formed by p-type doping and, according to an alternative development, contains zinc and / or silicon as a dopant. The dopant concentration of the intermediate layer is preferably lower than the dopant concentration of the p ⁺ substrate. Particularly preferably, the dopant concentration is in the range between a factor up to a factor of less than 2-5.

In one alternative embodiment, the intermediate layer is formed n-type doped and contains, among other things, silicon and / or tin as dopants. The dopant concentration of the intermediate layer is preferably lower than the dopant concentration of the n ⁺ substrate. Particularly preferably, the dopant concentration is lower by a factor of 100 than the dopant concentration of the n ⁻ layer.

According to one alternative embodiment, the IGBT semiconductor structure has an n-type doped buffer layer, which is arranged between the intermediate layer and the n ⁻ layer. ^{It has} a dopant concentration of ¹² to 10 ¹⁶ cm ⁻³ and a layer thickness of 1 μm to 50 μm and contains or consists of a GaAs compound.

  In one alternative embodiment, the IGBT semiconductor structure is formed as a trench IGBT semiconductor structure, where the dielectric layer extends perpendicular to the top surface of the IGBT semiconductor structure.

The p ⁺ substrate preferably contains zinc. The n ⁻ layer and / or the n ⁺ region preferably contain silicon and / or chromium and / or palladium and / or tin, in which case the IGBT semiconductor structure is particularly preferably formed monolithically. ing.

  According to one alternative embodiment, the overall height of the IGBT semiconductor structure is at most 150-500 μm and / or the side length or diameter of the IGBT semiconductor structure is between 1 mm and 15 mm.

  In one alternative embodiment, the p region and / or the n region are formed in a circle on the top surface of the IGBT semiconductor structure or in a semicircle disposed respectively on the end face of the structure. .

  According to one development, the dielectric layer contains the deposited oxide and has a layer thickness from 10 nm to 1 μm.

In one alternative embodiment, the stacked layer structure has a semiconductor bond formed between the n ⁻ layer and the p ⁺ substrate.

  It is noted that the term “semiconductor bonding” is used synonymously with the term “wafer bonding”.

In one embodiment, the layer structure consisting of a p ⁺ substrate forms a first partial stack, and the layer structure consisting of n ⁺ and n ⁻ layers and possibly a buffer layer is 2 partial stacks are formed.

In one development, the stacked layer structure has an intermediate layer disposed between the p ⁺ substrate and the n ⁻ layer. Here, the first partial stack includes an intermediate layer. The semiconductor bonding is arranged between the intermediate layer and the n ⁻ layer or between the intermediate layer and the buffer layer.

  In one development, the first partial stack and the second partial stack are each formed monolithically.

In one further development, the first partial stack is formed by forming an intermediate layer using epitaxy starting from a p ⁺ substrate. In particular, the intermediate layer formed as a p ⁻ layer has a dopant of less than 10 ¹³ N / cm ⁻³ , that is, the intermediate layer is intrinsically doped or 10 ¹³ N / cm ⁻³ to It has a dopant between 10 ¹⁵ N / cm ⁻³ . In one embodiment, the p ⁺ substrate is thinned to a thickness between 200 μm and 500 μm by a polishing process before or after bonding.

In one alternative embodiment, n ^- starting from the substrate, n ^- substrate by being bonded to the second stack by a wafer bonding process, i.e. the n ⁺ layer, the second stack is formed The In one embodiment, the n ⁺ layer is formed as an n ⁺ substrate.

In a further process step, the n ⁻ substrate is thinned to the desired thickness.

In one development, the buffer layer is formed by an epitaxy process after the n ⁻ substrate or n ⁻ layer has been thinned.

In particular, the thickness of the n ⁻ substrate or n ⁻ layer is in the range between 50 μm and 250 μm. In particular, the dopant of the n ⁻ substrate is in the range between 10 ¹³ N / cm ⁻³ to 10 ¹⁵ N / cm ⁻³ . One advantage of wafer bonding is that a thick n ⁻ layer can be easily formed. This eliminates the long deposition process during epitaxy. In addition, the number of stacking faults can be reduced by wafer bonding.

In one alternative embodiment, the n ⁻ substrate has a dopant greater than 10 ¹⁰ N / cm ⁻³ and less than 10 ¹³ N / cm ⁻³ . By making the dopant extremely low, the n ⁻ substrate can also be interpreted as an intrinsic layer.

In one development, the surface of the n ⁻ substrate or buffer layer is bonded directly to the first stack by a semiconductor bonding process step. Subsequently, the back surface of the n ⁻ substrate is thinned to the desired thickness of the n ⁻ layer. n ^- to no substrate the n ^- after thinning the layer, by epitaxy or high dose implantation, the n ⁺ layer with ^{10 18 N / cm -3 ~5 ×} 10 19 N / cm -3 underrange between the dopant It is formed.

It is understood that thinning the n ⁻ substrate is performed using, inter alia, a CMP step, ie using chemical mechanical polishing.

  Hereinafter, the present invention will be described in detail with reference to the drawings. In the figure, the same reference numerals are assigned to the same types of parts. The illustrated embodiment is shown very schematically. That is, the spacing, the horizontal and vertical dimensions are not to scale and do not have a reciprocal geometric relationship that can be derived unless otherwise stated.

1 shows a schematic diagram of a first embodiment of an IGBT according to the invention. FIG. 1 shows a schematic plan view of a first embodiment of an IGBT according to the present invention. FIG. FIG. 3 shows a schematic diagram of a second embodiment of the IGBT according to the invention. FIG. 4 shows a schematic diagram of a third embodiment of an IGBT according to the invention. FIG. 6 shows a schematic plan view of a third embodiment of an IGBT according to the present invention. FIG. 6 shows a schematic view of a fourth embodiment of the IGBT according to the invention.

  FIG. 1 shows a cross-sectional view of a first embodiment of an IGBT semiconductor structure 10 comprising three terminal contacts 14, 16, 18 and a dielectric layer 20. In the following, the IGBT semiconductor structure 10, also referred to as the semiconductor structure 10, is formed in a stack so as to have an upper surface 12 and a lower surface 22. doing.

  The first terminal contact 14 is formed as a metal layer, and this metal layer is bonded to the lower surface 22 of the semiconductor structure 10 by material bonding.

The bottom layer of the IGBT semiconductor structure forms a p ⁺ substrate 24. The p ⁺ substrate thus forms the lower surface 22 of the semiconductor structure 10 and has a layer thickness D1. The p ⁺ substrate is followed by a light intermediate layer 26 of layer thickness D3 and an n ⁻ layer 28 of layer thickness D2, which are weakly n-doped or weakly p-doped, in the order described. .

In the illustrated embodiment, the n ⁻ layer 28 forms at least a portion of the top surface 12 of the semiconductor structure 10. Another portion of the top surface 12 of the semiconductor structure 10 is formed by a p region 32, where the p region 32 extends from the top surface 12 of the IGBT semiconductor structure 10 to a depth T 1 in the n ⁻ layer.

Another portion of the top surface 12 of the semiconductor structure 10 is formed by an n ⁺ region 34, where the n ⁺ region extends from the top surface 12 of the semiconductor structure 10 into a p region to a depth T2 shallower than T1. Yes.

That is, in contact with the upper surface 12 of the semiconductor structure 10, a first pn junction 36 between the p region and the n ⁻ layer, and a second pn junction 38 between the n ⁺ region and the p region, Here, the dielectric layer 20 covers at least the first pn junction 36 and the second pn junction 38, and the upper surface 12 of the semiconductor structure 10, particularly the n ⁺ region, p It is bonded to the region and the n ⁻ layer by material bonding and has a layer thickness D5.

  The second terminal contact 16 is formed as a field plate on the surface of the dielectric layer 20 opposite to the semiconductor structure 10.

Similarly, the third terminal contact 18 is formed as a metal layer, and this metal layer is bonded to the portion formed from the p region and the n ⁺ region of the upper surface 12 of the semiconductor structure 10 by material bonding. Yes.

The n ⁺ region 34, the p region 32 and the n ⁻ layer 28 together with the dielectric layer 20 and the three terminal contacts 14, 16, 18 form a MOS transistor or bipolar module, while the p substrate 24, The intermediate layer 26 and the n ⁻ layer 28 represent pin diodes.

In FIG. 2, a plan view of the top surface 12 of the IGBT semiconductor structure 10 is shown. Both the p region 32 and the n ⁺ region 34 are formed in a circular shape. The IGBT semiconductor structure 10 has a rectangular upper surface 12 having a first side length K1 and a second side length K2.

  In FIG. 3, another embodiment of an IGBT semiconductor structure 10 is shown. Only the differences from FIG. 1 will be described below. The semiconductor structure 10 is formed as a so-called punch-through type IGBT, and is weakly n-type doped or weakly p-type doped between the intermediate layer 26 and the n layer 28 and has a layer thickness D4. A buffer layer 40 is disposed.

  In FIG. 4, another embodiment of an IGBT semiconductor structure 10 is shown. Only the differences from FIGS. 1 and 3 will be described below. The semiconductor structure 10 is formed as a so-called trench type IGBT.

The p region 32 is formed as a layer on the n ⁻ layer and the n ⁺ region 34 is formed as a layer on the p region 32. The semiconductor structure 10 includes a layered n region and a layered p region from the upper surface 12. It has a groove 42 that penetrates to reach the n ⁻ layer, a so-called trench.

The first pn junction 36 and the second pn junction 38 extend perpendicular to the side surface 44 of the groove 42. The side surface 44 and the bottom 48 of the groove are covered with the dielectric layer 20. A second terminal contact 16, which is formed as a field plate, extends correspondingly on the dielectric layer 20. The third terminal contact 18 is disposed on the side surface 50 of the semiconductor structure 10, which is located on the opposite side of the side surface 44 of the groove 42, and is electrically connected to the layered n ⁺ region 34 and the layered p region 32. Connected.

  In one alternative embodiment shown in FIG. 6, a third terminal contact 18 is disposed on the top surface 12. In other words, the second pn junction 38 is also formed on the surface according to the embodiment shown in FIG.

  A schematic plan view of the trench IGBT according to FIG. 4 is shown in FIG. The groove 42 has an oval shape, and the IGBT semiconductor structure 10 has a diameter A1.

In FIG. 6, another embodiment of an IGBT semiconductor structure 10 is shown. Only the differences from FIG. 4 will be described below. Similarly, the semiconductor structure 10 formed as a trench IGBT has a buffer layer 40 between the intermediate layer 26 and the n ⁻ layer 28.

Claims (16)

In an IGBT semiconductor structure (10) comprising an upper surface (12) and a lower surface (22),
Formed on the lower surface (22) of the IGBT semiconductor structure (10), having a dopant concentration of 5 × 10 ^{18 to} 5 × 10 ²⁰ cm ⁻³ and a layer thickness (D1) of 50 to 500 μm; And a p ⁺ substrate (24) containing or consisting of a GaAs compound;
An n ⁻ layer (28) having a dopant concentration of 10 ¹² to 10 ¹⁷ cm ⁻³ and a layer thickness (D2) of 10 to 300 μm and containing or consisting of a GaAs compound;
At least one p-region (32) in contact with said n ⁻ layer (28) comprising a dopant concentration of 10 ¹⁴ to 10 ¹⁸ cm ⁻³ and containing or consisting of a GaAs compound When,
At least one n ⁺ region (34) in contact with said p region (32), having a dopant concentration of at least 10 ¹⁹ cm ⁻³ and containing or consisting of a GaAs compound;
A dielectric layer (20);
A first terminal contact (14) electrically conductively connected to the lower surface (22) of the IGBT semiconductor structure (10) and containing or consisting of a metal or metal compound; ,
A second terminal contact (16) and a third terminal contact (18), each containing or consisting of a metal or metal compound;
Have
The at least one p region (32), together with the n ⁻ layer (28), forms a first pn junction (36);
The at least one n ⁺ region (34), together with the at least one p region (32), forms a second pn junction (38);
The dielectric layer (20) covers at least the first pn junction (36) and the second pn junction (38), and the n ⁻ layer (28) and the p region (32). ) And the n ⁺ region (34) by a material bond,
The second terminal contact (16) is formed on the dielectric layer (20) as a field plate,
The third terminal contact (18) is conductively connected to the at least one p region (32) and the at least one n ⁺ region (34);
In the IGBT semiconductor structure (10),
Between the p ⁺ substrate (24) and the n ⁻ layer (28), having a layer thickness (D3) of 1 μm to 50 μm and a dopant concentration of 10 ¹² to 10 ¹⁷ cm ⁻³ and being doped Intermediate layer (26) is disposed,
The IGBT semiconductor structure (10), wherein the intermediate layer (26) is bonded to at least the p ⁺ substrate (24) by material bonding. The intermediate layer (26) is formed by p-type doping,
An IGBT semiconductor structure (10) according to claim 1. The intermediate layer (26) has a dopant concentration lower than that of the p ⁺ substrate (24), or the intermediate layer (26) has a dopant concentration of the p ⁺ substrate (24). , Characterized in that it is in the range between the coefficients up to a coefficient less than 2-5,
An IGBT semiconductor structure (10) according to claim 2. The intermediate layer (26) contains zinc and / or silicon,
An IGBT semiconductor structure (10) according to claim 2 or 3. The intermediate layer (26) is formed by n-type doping,
An IGBT semiconductor structure (10) according to claim 1. The intermediate layer (26) contains silicon and / or tin,
An IGBT semiconductor structure (10) according to claim 5. The dopant concentration of the intermediate layer (26) is approximately lower than the dopant concentration of the n ⁻ layer (28) by a factor of 100,
An IGBT semiconductor structure (10) according to claim 5 or 6. The IGBT semiconductor structure (10) has an n-type doped buffer layer (40), which is between the intermediate layer (26) and the n ⁻ layer (28). Characterized in that it has a dopant concentration of 10 ¹² to 10 ¹⁷ cm ⁻³ and a layer thickness (D4) of 1 μm to 50 μm and contains or consists of a GaAs compound And
An IGBT semiconductor structure (10) according to any one of the preceding claims. The IGBT semiconductor structure (10) is formed as a trench type IGBT semiconductor structure (10), and the dielectric layer (20) is perpendicular to the upper surface (12) of the IGBT semiconductor structure (10). It is characterized by extending,
An IGBT semiconductor structure (10) according to any one of the preceding claims. The p + substrate (24) contains zinc,
An IGBT semiconductor structure (10) according to any one of the preceding claims. The n ⁻ layer (28) and / or the n ⁺ region (34) contain silicon and / or chromium and / or palladium and / or tin,
IGBT semiconductor structure (10) according to any one of the preceding claims. The IGBT semiconductor structure (10) is monolithically formed,
An IGBT semiconductor structure (10) according to any one of the preceding claims. The total height (H1) of the IGBT semiconductor structure (10) is 150 to 500 μm at the maximum,
IGBT semiconductor structure (10) according to any one of the preceding claims. The p region (32) and / or the n ⁺ region (34) is formed in an elliptical shape or a true circular shape in the upper surface (12) of the IGBT semiconductor structure (10),
IGBT semiconductor structure (10) according to any one of the preceding claims. The IGBT semiconductor structure (10) has a side length (K1, K2) or diameter (A1) of 1 mm to 15 mm,
IGBT semiconductor structure (10) according to any one of the preceding claims. The dielectric layer (20) contains a deposited oxide and has a layer thickness (D5) from 10 nm to 1 μm,
IGBT semiconductor structure (10) according to any one of the preceding claims.

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