JP2018181398A - Ferroelectric substance memory and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric substance memory and a control method thereof to prevent degradation of data readout accuracy of the ferroelectric memory, while preventing reliability of the ferroelectric memory.SOLUTION: A ferroelectric memory (1) includes a plurality of word lines (18), a plurality of bit lines (16, 17), a plurality of memory cells (10), a plate line (19), and a sense amplifier (40). The plurality of memory cells (10) include ferroelectric capacitors (12, 14) and cell transistors (11, 13) which connect a first electrode of the ferroelectric capacitors (12, 14) to a plurality of bit lines (16, 17). The sense amplifier (40) amplifies an electric quantity indicating the data read from the plurality of memory cells (10) with a first voltage (VII). When reading data stored in any of the plurality of memory cells (10), a second voltage (SVII) higher than the first voltage (VII) is applied in a pulse form to a plate line (19) connected to the second electrode of the memory cell (10) from which data is read.SELECTED DRAWING: Figure 10

Description

  The present invention relates to a ferroelectric memory and a control method thereof.

  In a ferroelectric memory (Ferroelectric Random Access Memory, FRAM (registered trademark), FeRAM), a ferroelectric capacitor is used as a storage element, and information can be held even when the power is off. Therefore, the storage medium of the IC card It is used as etc.

  Various techniques are known to improve the structure of ferroelectric memories. For example, there is known a technology that enables accurate reading of memory cell data even when the amount of electricity stored in a ferroelectric capacitor decreases due to relaxation or polarization fatigue (see, for example, Patent Document 1). ). There is also known a technology for extending the time for which a ferroelectric memory holds data (see, for example, Patent Document 2). There is also known a technique of reducing the power consumption of a ferroelectric memory and increasing the voltage margin between bit lines at the time of sensing (see, for example, Patent Document 3).

JP-A-11-238387 JP-A-8-273375 Unexamined-Japanese-Patent No. 11-273361 gazette

  With the recent progress of miniaturization of the ferroelectric memory, the area of the ferroelectric capacitor is reduced and the amount of chargeable electricity is reduced, so that the potential difference when reading data from the ferroelectric capacitor is reduced. If the potential difference when reading data from the ferroelectric capacitor becomes smaller, the accuracy of reading data from the ferroelectric capacitor may be lowered. Further, with the progress of miniaturization of the ferroelectric memory, the power supply voltage supplied to the ferroelectric memory is lowered, so that not only the potential difference at the time of reading the data but also the voltage at the time of writing the data becomes low. If the voltage at the time of writing data becomes low, there is a possibility that the writing accuracy of the data may be lowered.

  Reduction in channel length of the cell transistor connected to the ferroelectric capacitor, reduction in thickness of the gate oxide film, and reduction in thickness of the ferroelectric capacitor prevent deterioration in data read accuracy and write accuracy of the ferroelectric memory Be done. However, the reduction of the channel length of the cell transistor and the reduction of the thickness of the gate oxide film may lead to a decrease in the withstand voltage of the cell transistor and a deterioration in Time Dependent Dielectric Breakdown (TDDB) characteristics. Further, thinning of the ferroelectric capacitor may lower the reliability of the ferroelectric capacitor.

  In one embodiment, it is an object of the present invention to provide a technology capable of preventing a decrease in data read accuracy of a ferroelectric memory while securing the reliability of the ferroelectric memory.

  In one embodiment, the ferroelectric memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a plate line, and a sense amplifier. The plurality of memory cells have ferroelectric capacitors and cell transistors connecting the first electrodes of the ferroelectric capacitors to the plurality of bit lines depending on the selection of the word line. The plate line is connected to the second electrode of the ferroelectric capacitor. The sense amplifier amplifies an electrical quantity indicating data read from the plurality of memory cells at a first voltage. When reading data stored in any of the plurality of memory cells, a second voltage higher than the first voltage is applied in a pulsed manner to the plate line connected to the second electrode of the memory cell from which the data is read Ru.

  In one embodiment, it is possible to prevent the decrease in the data read accuracy of the ferroelectric memory while securing the reliability of the ferroelectric memory.

FIG. 2 is a circuit diagram of a 2T2C ferroelectric memory cell mounted in a ferroelectric memory. (A) is a timing chart which shows the operation | movement at the time of read-out operation | movement, (b)-(e) is a figure which shows the relationship of the applied voltage and polarization amount in the operation | movement shown to (a). FIG. 2 is a block diagram of a ferroelectric memory associated with the ferroelectric memory according to the embodiment. FIG. 4 is a circuit diagram of the ferroelectric memory shown in FIG. 3; It is a timing chart which shows operation | movement of the ferroelectric memory shown in FIG. FIG. 2 is a functional block diagram of a ferroelectric memory according to the first embodiment. (A) is a figure which shows an example of the 1st voltage generation circuit shown in FIG. 6, (b) is a figure which shows an example of the 2nd voltage generation circuit shown in FIG. (A) is a figure which shows an example of the relationship between reference voltage VBGR, 1st voltage VII, 2nd voltage SVII and 3rd voltage VPP, and the external voltage VDD, (b) is reference voltage VBGR, 1st voltage VII, It is a figure which shows the other example of the relationship between 2nd voltage SVII and 3rd voltage VPP, and the external voltage VDD. FIG. 7 is a block diagram of a ferroelectric memory shown in FIG. FIG. 7 is a circuit diagram of the ferroelectric memory shown in FIG. 7 is a timing chart showing the operation of the ferroelectric memory shown in FIG. FIG. 6 is a block diagram of a ferroelectric memory according to a second embodiment. It is a circuit diagram of the ferroelectric memory shown in FIG. FIG. 13 is a circuit diagram of a booster circuit shown in FIG. 12; It is a timing chart which shows operation | movement of the ferroelectric memory shown in FIG.

  The ferroelectric memory and its control method according to the present invention will be described below with reference to the drawings. However, it should be noted that the technical scope of the present invention is not limited to those embodiments, but extends to equivalents to the invention described in the claims.

(Operation of ferroelectric memory cell)
Before describing the ferroelectric memory according to the embodiment, the operation of the ferroelectric memory will be described with reference to FIG. FIG. 1 is a circuit diagram of a 2T2C ferroelectric memory cell mounted in a ferroelectric memory.

  The memory cell 10 is a 2T2C (two-transistor two-capacitor) type ferroelectric memory cell, and includes a first cell transistor 11, a first ferroelectric capacitor 12, a second cell transistor 13, and a second ferroelectric material. And a capacitor 14.

  Each of the first cell transistor 11 and the second cell transistor 13 is an n-type MOSFET (metal-oxide-semiconductor field-effect transistor). The source of the first cell transistor 11 is connected to the first bit line 16, the gate of the first cell transistor 11 is connected to the word line 18, and the drain of the first cell transistor 11 is the first of the first ferroelectric capacitor 12. Connected to the electrode. The source of the second cell transistor 13 is connected to the second bit line 17, the gate of the second cell transistor 13 is connected to the word line 18, and the drain of the second cell transistor 13 is the first of the second ferroelectric capacitor 14. Connected to the electrode.

  Each of the first ferroelectric capacitor 12 and the second ferroelectric capacitor 14 is disposed between the first electrode which is an IrOx film, the second electrode which is a Pt film, and the first electrode and the second electrode. And a ferroelectric which is a PZT (lead zirconate titanate) film. The second electrodes of the first ferroelectric capacitor 12 and the second ferroelectric capacitor 14 are connected to the plate line 19.

  2 (a) is a timing chart showing the read operation of the ferroelectric memory shown in FIG. 1, and FIGS. 2 (b) to 2 (e) are applied voltages in the operation shown in FIG. 2 (a). It is a figure which shows the relationship between and the polarization amount. In FIG. 2 (b) to 2 (e), black circles indicate the operation of the first ferroelectric capacitor 12, and white circles indicate the operation of the second ferroelectric capacitor 14. Moreover, in FIG.2 (b)-2 (e), a horizontal axis shows the voltage applied to the 1st ferroelectric capacitor 12 and the 2nd ferroelectric capacitor 14, and a vertical axis | shaft shows polarization amount. In FIGS. 2A to 2E, “1” is stored in the first ferroelectric capacitor 12, and “0” is stored in the second ferroelectric capacitor 14. That is, the remanent polarization of the first ferroelectric capacitor 12 is a P term that causes polarization inversion, and the remanent polarization of the second ferroelectric capacitor 14 is a U term that does not cause polarization inversion.

  In the read operation, first, the word line signal WL1 is transitioned to rise to make the word line 18 in a selected state, and the first cell transistor 11 and the second cell transistor 13 are turned on. At this time, since no charge is stored in the first ferroelectric capacitor 12 and the second ferroelectric capacitor 14, as shown in (1) and (b) of FIG. The potentials of the bit line signal BL1 and the second bit line signal / BL1 do not change.

  Next, as shown in (2) and (c) of FIG. 2A, the plate line signal CP1 is raised and transitioned to be set to the power supply voltage VDD. At this time, the first bit line signal BL1 and the second bit line signal / BL1 are maintained at approximately 0 V, and a positive voltage is applied to the first ferroelectric capacitor 12 and the second ferroelectric capacitor 14.

  Since the data value “1” is stored in the first ferroelectric capacitor 12, the voltage applied to the first ferroelectric capacitor 12 has the opposite polarity to that at the time of writing, so that polarization inversion occurs, A large amount of inverted charge flows to the first bit line 16. On the other hand, since the data value "0" is stored in the second ferroelectric capacitor 14, the voltage applied to the second ferroelectric capacitor 14 has the same polarity as that at the time of writing, so the polarization inversion is reversed. Does not occur, and a relatively small amount of charge flows to the second bit line 17. The amount of electricity flowing through the first bit line 16 and the second bit line 17 is converted into a voltage by a sense amplifier (not shown), and the difference between the voltages applied to the first bit line 16 and the second bit line 17 is It is amplified to the power supply voltage VDD.

  Next, as shown in (3) of FIG. 2 (a) and FIG. 2 (d), the plate line CP1 is set to 0V. When the plate line CP1 is set to 0 V, since the voltage of the first bit line signal BL1 is the power supply voltage VDD, an inverted voltage of the power supply voltage VDD is applied to the first ferroelectric capacitor 12. On the other hand, since the voltage of the second bit line signal / BL1 is 0V, the voltage applied to the second ferroelectric capacitor 14 is 0V.

  Then, when the voltage of the first bit line signal BL1 is set to 0 V as shown in (4) and (e) of FIG. 2A, the voltage applied to the first ferroelectric capacitor 12 is also 0 V. Return to

  In the example described with reference to FIG. 2, although the first bit line signal BL1, the second bit line signal / BL1 and the plate line signal CP1 are set to the power supply voltage VDD, they are set to a high voltage indicating a data value "1". A step-down voltage obtained by stepping down the power supply voltage VDD may be used. On the other hand, a voltage of 0 V, ie, a ground level may be used as the low voltage indicating the data value “0”. In the memory cell 10, in order to allow charges of sufficient electric quantity to flow when reading data, it is sufficient to store charges when writing data in the first ferroelectric capacitor 12 and the second ferroelectric capacitor 14. It is preferable that a certain degree of potential be applied. For example, when the memory cell 10 is designed according to a design rule of 180 nm, it is preferable to write data at a voltage of about 1.8 [V]. That is, each of the first bit line signal BL1, the second bit line signal / BL1 and the plate line signal CP1 is set to either 0 [V] or 1.8 [V].

  On the other hand, in order to apply a sufficient voltage to both ends of the first ferroelectric capacitor 12 and the second ferroelectric capacitor 14, the operation threshold of the first cell transistor 11 and the second cell transistor 13 is applied to the word line signal WL1. Preferably, the voltage is set to a voltage larger than the value voltage. For example, the word line signal WL1 is set to a voltage of about 3 [V].

(Configuration and Operation of Ferroelectric Memory Related to Ferroelectric Memory According to Embodiment)
FIG. 3 is a block diagram of a ferroelectric memory associated with the ferroelectric memory according to the embodiment, and FIG. 4 is a circuit diagram of the ferroelectric memory shown in FIG.

  The ferroelectric memory 900 has memory cells 10 arranged in an array of n rows and m columns, n sense amplifiers 20, and n pairs of precharge transistors 31 and 32. The configuration and operation of the memory cell 10 have been described with reference to FIGS. 1 and 2, so detailed description will be omitted here.

  The sense amplifier 20 has a first sense transistor 21 to a sixth sense transistor 26. When the data value is “1”, the sense amplifier 20 boosts the voltages of the first bit line 16 and the second bit line 17 to a first voltage VII. Further, when the data value is “0”, the sense amplifier 20 steps down the first bit line 16 and the second bit line 17 to the ground voltage VSS. For example, when the data value of the first bit line 16 is “1”, the voltage of the first bit line 16 is boosted to the first voltage VII, and the data value of the second bit line 17 is “0”. The voltage of the second bit line 17 is stepped down to the ground voltage VSS.

  The n pairs of precharge transistors 31 and 32 are n-type MOSFETs, and the precharge signal φPRn is input to the gate, the source is grounded, and the drain is connected to each of the first bit line 16 and the second bit line 17 Be done. The n pairs of precharge transistors 31 and 32 ground each of the first bit line 16 and the second bit line 17 when turned on.

  FIG. 5 is a timing chart showing the operation of the ferroelectric memory 900. In FIG. 5, a waveform 501 indicates a chip enable signal CEB, a waveform 502 indicates a precharge signal φPRn, a waveform 503 indicates a first sense amplifier signal φ / SA, and a waveform 504 indicates a second sense amplifier signal φSA. The waveform 505 shows the word line signal WL1, the waveform 506 shows the plate line signal CP1, the waveform 507 shows the first bit line signal BL1, and the waveform 508 shows the second bit line signal / BL1.

  In the timing chart shown in FIG. 5, the data value “1” stored in the first ferroelectric capacitor 12 and the data value “0” stored in the second ferroelectric capacitor 14 are read out. Then, the data value “0” is written to the first ferroelectric capacitor 12, and the data value “1” is written to the second ferroelectric capacitor 14.

  At time t0, in response to the falling transition of the chip enable signal CEB, the ferroelectric memory 900 is activated. Next, at time t1, in response to the falling transition of the precharge signal φPRn, the precharge of the first bit line 16 and the second bit line 17 to the ground voltage VSS is stopped. Next, at time t2, the word line signal WL1 is boosted to the first voltage VII according to the selection of the word line, and at time t3, the word line signal WL1 is further boosted to the boosted voltage VPP. In response to the word line signal WL1 being further boosted to the boosted voltage VPP, the first cell transistor 11 and the second cell transistor 13 are turned on.

  Then, at time t4, in response to the rising transition of the plate line signal CP1 to the first voltage VII, the ferroelectric memory 900 starts the read operation. The first bit line signal BL1 indicating the data value "1" is higher in voltage than the second bit line signal / BL1 indicating the data value "0". Next, at time t5, the first bit line signal BL1 is boosted to the first voltage VII in response to the falling transition of the first sense amplifier signal φ / SA and the rising transition of the second sense amplifier signal φSA. . On the other hand, the second bit line signal / BL1 is stepped down to the ground voltage VSS.

  Next, at time t6, in response to the rising transition of the chip enable signal CEB, the ferroelectric memory 900 ends the activation state. Next, at time t7, the first bit line signal BL1 makes a falling transition, and the second bit line signal / BL1 makes a rising transition. The falling transition of the first bit line signal BL 1 causes the data value “0” to be written to the first ferroelectric capacitor 12. Next, at time t8, the data value "1" is written to the second ferroelectric capacitor 14 in response to the falling transition of the plate line signal CP1 to the ground voltage VSS.

  Next, at time t9, the second bit line signal / BL1 is stepped down to the ground voltage VSS in response to the rising transition of the first sense amplifier signal φ / SA and the falling transition of the second sense amplifier signal φSA. . Next, at time t10, in response to the rising transition of the precharge signal φPRn, precharging of the first bit line 16 and the second bit line 17 to the ground voltage VSS is resumed. Then, at time t11, in response to the completion of the word line selection, the word line signal WL1 makes a falling transition.

(Problems of Ferroelectric Memory Related to Ferroelectric Memory According to Embodiment)
In the ferroelectric memory 900, with the progress of miniaturization, the area of the ferroelectric capacitor decreases and the amount of chargeable electricity decreases, so that the potential difference at the time of reading data becomes small, and the data from the ferroelectric capacitor There is a possibility that the reading accuracy may be reduced. Further, in the ferroelectric memory 900, the power supply voltage supplied to the ferroelectric memory 900 is lowered, so that not only the potential difference at the time of reading data but also the voltage at the time of writing data is lowered and the writing accuracy of the data is improved. It may decrease.

  In the ferroelectric memory 900, by raising the voltages applied to the first bit line 16, the second bit line 17, and the plate line 19, the lowering of the reading accuracy and the writing accuracy is prevented. However, when the voltages applied to the first bit line 16, the second bit line 17, and the plate line 19 are increased, the first and second cell transistors 11 and 13 and the first and second ferroelectric capacitors 12 and 14 are The reliability of the components of the memory cell may be reduced.

(Overview of Ferroelectric Memory According to Embodiment)
In the ferroelectric memory according to the embodiment, when reading data stored in any of the plurality of memory cells, a second voltage higher than the first voltage applied to the sense amplifier is applied in a pulsed manner to the plate line Be done. In the ferroelectric memory according to the embodiment, the second voltage higher than the first voltage applied to the sense amplifier when data is read is applied to the plate line to prevent the data reading accuracy from being lowered. Do. In the ferroelectric memory according to the embodiment, a high second voltage is applied to the plate line in a pulse shape when reading data, thereby minimizing the time during which the high voltage is applied to the memory cell. The reliability of the cell transistor included in the memory cell is prevented from being lowered.

(Configuration and Function of Ferroelectric Memory According to First Embodiment)
FIG. 6 is a functional block diagram of the ferroelectric memory according to the first embodiment.

  The ferroelectric memory 1 is a memory having a memory cell array 100, a row decoder 101, a column decoder 102, an address latch circuit 103, and a control circuit 104 and performing a write operation and a read operation according to a Hi-z system. The ferroelectric memory further includes a reference voltage generation circuit 105, a first voltage generation circuit 106, a second voltage generation circuit 107, a third voltage generation circuit 108, and a multiplexer 109. Column decoder 102 includes a sense amplifier and a write amplifier.

  Memory cell array 100 has memory cells 10 arranged in an array of n rows and m columns. Row decoder 101 selects a row of memory cells arranged in memory cell array 100 based on a row selection signal RS input from address latch circuit 103. Column decoder 102 selects a row of memory cells arranged in memory cell array 100 based on a column selection signal CS input from address latch circuit 103, and amplifies write data Din and read data Dout. Address latch circuit 103 latches externally applied address signal ADD, and outputs row selection signal RS generated from the latched address signal ADD to row decoder 101, and outputs column selection signal CS to column decoder 102. Do. The control circuit 104 receives the chip enable signal CEB, the write enable signal WEB, the output enable signal OEB, the lower byte select signal LBB, and the upper byte select signal UBB, and controls the column decoder 102 according to the input signals. The control circuit 104 is, for example, a logic circuit.

  The circuit configurations of the memory cell array 100, the row decoder 101, the column decoder 102, and the address latch circuit 103 are widely known, so the detailed description thereof is omitted here.

  The reference voltage generation circuit 105 is, for example, a band gap reference, and generates VBGR from the external power supply VDD. The first voltage generation circuit 106 is a circuit that steps down the first voltage VII from the external power supply VDD to a constant voltage using the reference VBGR generated by the reference voltage generation circuit 105. The second voltage generation circuit 107 is a pumping circuit that uses the second voltage SVII higher than the first voltage VII as the reference potential VBGR to boost the external power supply VDD to a constant voltage. The third voltage generation circuit 108 self-boosts the second voltage VII input from the second voltage generation circuit 107 to generate a third voltage VPP. The first voltage VII, the second voltage SVII, and the third voltage VPP are constant regardless of fluctuations in the operation guarantee range of the external power supply VDD.

  The multiplexer 109 selects one of the first voltage VII, the second voltage SVII, and the third voltage VPP based on the control signal input from the control circuit 104, and selects one of the row decoder 101 and the column decoder 102 as the power supply signal SVIIm. Output. The multiplexer 109 may output the power supply signal SVIIm having the same voltage to the row decoder 101 and the column decoder 102, and may output the power supply signal SVIIm having a different voltage to the row decoder 101 and the column decoder 102. Further, the multiplexer 109 may output a plurality of power supply signals SVIIm having different voltages to the row decoder 101 and the column decoder 102, respectively.

  FIG. 7A is a view showing an example of the first voltage generation circuit 106, and FIG. 7B is a view showing an example of the second voltage generation circuit 107. As shown in FIG.

The first voltage generation circuit 106 includes a first resistance element 161, a second resistance element 162, a comparator 163, and a transistor 164. The first voltage generation circuit 106 steps down the external voltage VDD to generate a first voltage VII. The first voltage VII is obtained from the resistance value R1 of the first resistance element 161, the resistance value R2 of the second resistance element 162, and the reference voltage VBGR.
VII = (R1 + R2) / R2 x VBGR
It is indicated by.

The second voltage generation circuit 107 includes a first resistance element 171, a second resistance element 172, a comparator 173, an oscillator circuit 174, and a pump circuit 175, and boosts the external voltage VDD to obtain a second voltage SVII. Generate The second voltage SVII is obtained from the resistance value R1 ′ of the first resistance element 171, the resistance value R2 ′ of the second resistance element 172, and the reference voltage VBGR.
SVII = (R1 '+ R2') / R2 '× VBGR
It is indicated by.

  FIG. 8A shows an example of the relationship between the reference voltage VBGR, the first voltage VII, the second voltage SVII, the third voltage VPP, and the external voltage VDD. FIG. 8B shows another example of the relationship between reference voltage VBGR, first voltage VII, second voltage SVII and third voltage VPP, and external voltage VDD. 8A and 8B, the horizontal axis indicates the external voltage, and the vertical axis indicates the reference voltage VBGR, the first voltage VII, the second voltage SVII, and the third voltage VPP. The figure shown in FIG. 8A shows an example in which the peripheral circuit is formed according to the design rule of 180 nm, and the figure shown in FIG. 8B forms the peripheral circuit according to the design rule of 110 to 130 nm An example is shown.

  In the example shown in FIG. 8A, the reference voltage VBGR, the first voltage VII, the second voltage SVII, and the third voltage VPP are in the range where the external voltage VDD is in the range of 1.8 V to 3.6 V. The voltage becomes constant and the operation of the ferroelectric memory 1 is secured. On the other hand, in the example shown in FIG. 8B, the reference voltage VBGR, the first voltage VII, the second voltage SVII, and the third voltage in the range where the external voltage VDD is in the range of 1.5V to 3.6V. VPP becomes a constant voltage, and the operation of the ferroelectric memory 1 is secured. In the example shown in FIG. 8B, in a product requiring high reliability, the operation of the ferroelectric memory 1 is performed when the external voltage VDD is in the range of 1.8 V to 3.6 V. Guaranteed.

  FIG. 9 is a block diagram of the ferroelectric memory 1 and FIG. 10 is a circuit diagram of the ferroelectric memory 1.

  Memory cell array 100 includes memory cells 10 arranged in an array of n rows and m columns, and includes n pairs of precharge transistors 31 and 32, n sense amplifiers 40, and n pairs of transfer transistors 41 and 42. Connected to The configurations and operations of the memory cell 10 and the n pairs of precharge transistors 31 and 32 have already been described with reference to FIGS. 1 and 4 and the like, and thus the detailed description will be omitted here.

  The sense amplifier 40 includes first to sixth sense transistors 21 to 26, and a voltage corresponding to the voltage signal SVIIm input from the multiplexer is supplied as a power supply voltage. When the data value is "1", the sense amplifier 40 boosts the voltages of the first bit line 16 and the second bit line 17 to a voltage corresponding to the voltage signal SVIIm. Further, when the data value is “0”, the sense amplifier 20 steps down the first bit line 16 and the second bit line 17 to the ground voltage VSS. For example, when the data value of the first bit line 16 is "1", the voltage of the first bit line 16 is boosted to a voltage corresponding to the voltage signal SVIIm, and the data value of the second bit line 17 is "0". At this time, the voltage of the second bit line 17 is stepped down to the ground voltage VSS.

  The n pairs of transfer transistors 41 and 42 are n-type MOSFETs, the bit transfer signal φBT is input to the gates, the source is connected to the sense amplifier 40, and the drains are of the first bit line 16 and the second bit line 17. Connected to each. The n pairs of transfer transistors 41 and 42 connect the first bit line 16 and the second bit line 17 to the sense amplifier 40 when turned on, and the first bit line 16 and the second bit line when turned off. Disconnect the connection between the sense amplifier 40 and the sense amplifier 40;

  FIG. 11 is a timing chart showing the operation of the ferroelectric memory 1. In FIG. 11, a waveform 1101 indicates a chip enable signal CEB, a waveform 1102 indicates a precharge signal φPRn, and a waveform 1103 indicates a bit transfer signal φBTn. A waveform 1104 indicates the first sense amplifier signal φ / SA, a waveform 1105 indicates the second sense amplifier signal φSA, and a waveform 1106 indicates the word line signal WL1. A waveform 1107 indicates a plate line signal CP1, a waveform 1108 indicates a first bit line signal BL1, and a waveform 1109 indicates a second bit line signal / BL1. A waveform 1110 indicates unselected bit line signals BL 'and / BL', a waveform 1111 indicates a first sense amplifier data signal SAD, a waveform 1112 indicates a second sense amplifier data signal SA / D, and a waveform 1113 is unselected The capacitor signal n is shown.

  In the timing chart shown in FIG. 11, the data value “1” stored in the first ferroelectric capacitor 12 and the data value “0” stored in the second ferroelectric capacitor 14 are read out. Then, the data value “0” is written to the first ferroelectric capacitor 12, and the data value “1” is written to the second ferroelectric capacitor 14.

  At time t0, in response to the falling transition of the chip enable signal CEB, the ferroelectric memory 1 is activated. Next, at time t1, in response to the falling transition of the precharge signal φPRn, the precharge of the first bit line 16 and the second bit line 17 to the ground voltage VSS is stopped. In addition, in response to the rising transition of bit transfer signal φBTn to the second voltage SVII, n pairs of transfer transistors 41 and 42 are turned on and applied to first bit line 16 and second bit line 17, respectively. Can be transmitted to the sense amplifier 40. Furthermore, at time t1, the bit transfer signal φBTn is boosted to the second voltage SVII. However, if the threshold voltage of transfer transistors 41 and 42 is lower than first voltage VII, bit transfer signal φBTn may be maintained at first voltage VII.

  Next, at time t2, when the word line signal WL1 is boosted to the second voltage SVII according to the selection of the word line, the first cell transistor 11 and the second cell transistor 13 are turned on. When the first cell transistor 11 and the second cell transistor 13 are turned on, between the first bit line 16 and the first ferroelectric capacitor 12, and between the second bit line 17 and the second ferroelectric capacitor 14. There is an electrical connection between them.

  Next, at time t3, in response to the rising transition of the plate line signal CP1 to the second voltage SVII, the ferroelectric memory 1 starts the read operation. The first bit line signal BL1 indicating the data value “1” has a large amount of inverted charges flowing therethrough, and has a voltage higher than that of the second bit line signal / BL1 indicating the data value “0”.

  Then, at time t4, in response to the falling transition of bit transfer signal .phi.BTn, n pairs of transfer transistors 41 and 42 are turned off to couple first bit line 16 and second bit line 17 with sense amplifier 40. Electrical connection between them is cut off.

  Next, at time t5, in response to rising transition of precharge signal φPRn, precharging to ground voltage VSS of first bit line 16 and second bit line 17 is resumed, and first bit line 16 and the The voltage of the 2 bit line 17 becomes the ground voltage. Since the first cell transistor 11 and the second cell transistor 13 are turned on, the first bit line 16 and the second bit line 17 and the first electrodes of the first ferroelectric capacitor 12 and the second ferroelectric capacitor 14 are used. Becomes the ground voltage VSS. On the other hand, the voltage of the second electrodes of the first ferroelectric capacitor 12 and the second ferroelectric capacitor 14 becomes the second voltage SVII because the plate line signal CP1 is the second voltage SVII. The first ferroelectric capacitor 12 and the second ferroelectric capacitor 14 have the ground voltage VSS applied to the first electrode and the second voltage SVII applied to the second electrode, so that the data value "0" is written. .

  Next, at time t6, in response to the falling transition of the first sense amplifier signal φ / SA and the rising transition of the second sense amplifier signal φSA, the first sense amplifier data signal SAD is boosted to the first voltage VII. Be done. On the other hand, the second sense amplifier data signal SA / D is stepped down to the ground voltage VSS. At time t4, the electrical connection between first bit line 16 and second bit line 17 and sense amplifier 40 is cut off, so the voltage amplified by sense amplifier 40 is the first ferroelectric capacitor. It is not applied to the 12 and the second ferroelectric capacitors 14.

  Next, at time t7, in response to the falling transition of the plate line signal CP1 to the ground voltage VSS, the ferroelectric memory 1 ends the read operation. In the period from time t3 to time t7 in which the second voltage SVII is applied to the plate line signal CP1, the voltage of the non-selected ferroelectric memory is boosted by the coupling of the ferroelectrics. The period during which the second voltage SVII is applied between the first and second electrodes of the first and second ferroelectric capacitors 12 and 14 is preferably about 20 [ns]. That is, it is preferable that a period between the time t5 when the precharge signal φPRn makes a rising transition and the time t7 when the plate line signal CP1 makes a falling transition is about 20 [ns].

  Next, at time t8, in response to the rising transition of the chip enable signal CEB, the ferroelectric memory 1 ends the activation state. At time t9, in response to the falling transition of the precharge signal φPRn, precharging of the first bit line 16 and the second bit line 17 to the ground voltage VSS is stopped again.

  Next, at time t10, the second voltage SVII is applied to the source of the fifth sense transistor 25 of the sense amplifier 40. Further, the first sense amplifier data signal SAD indicating the ground potential VSS is input from an external device (not shown), and the second sense amplifier data signal SA / D indicating the second potential SVII is input from an external device (not shown). Ru.

  Next, at time t11, the bit transfer signal φBTn is boosted to the third voltage VPP, and the n pairs of transfer transistors 41 and 42 are turned on to make the first bit line 16, the second bit line 17, the sense amplifier 40 and so on. Are electrically connected. At the same time, the word line signal WL1 is boosted to the third voltage VPP, and the data value "1" is written to the second ferroelectric capacitor 14 through the second cell transistor 13.

  Next, at time t12, the first sense amplifier signal φ / SA makes a rising transition, and the second sense amplifier signal φSA makes a falling transition. Next, at time t13, in response to the falling transition of precharge signal φPRn, precharging to ground voltage VSS of first bit line 16 and second bit line 17 is resumed, and first bit line 16 and The voltage of the second bit line 17 becomes the ground voltage. Then, at time t14, in response to the completion of the selection of the word line, the word line signal WL1 makes a falling transition. The period from time t11 to time t14 when the third voltage VPP is applied to the word line 18 is preferably about 20 [ns] similarly to the period when the second voltage SVII is applied to the plate line 19.

(Operation and Effect of Ferroelectric Memory According to First Embodiment)
In the ferroelectric memory 1, when reading data stored in the memory cell, the plate line connected to the second electrode of the memory cell from which the data is read is higher than the first voltage for amplifying the signal of the bit line A second voltage is applied in a pulsed manner. The ferroelectric memory 1 applies the second voltage higher than the first voltage for amplifying the signal of the bit line to the plate line in a pulse shape to read out the data stored in the memory cell. While maintaining the reliability, it is possible to prevent the decrease in the data read accuracy of the ferroelectric memory.

  Further, in the ferroelectric memory 1, when data is written to the memory cell, a second voltage higher than the first voltage for amplifying the signal of the bit line is applied in a pulse shape to the memory cell to which the data is written. The ferroelectric memory 1 applies the second voltage higher than the first voltage for amplifying the bit line signal to the memory cell in a pulsed manner to write data in the memory cell, thereby achieving the reliability of the ferroelectric memory. While ensuring, it prevents deterioration of data write accuracy of the ferroelectric memory.

  Further, in the ferroelectric memory 1, the period in which the high voltage is applied to the cell transistor and the ferroelectric capacitor can be set to about 20 [ns] when the data value "1" is written to the memory cell.

  The ferroelectric memory 1 can increase the operation margin of the read / write operation of the ferroelectric capacitor by applying the second voltage to the plate line to read / write data, so the coercive voltage of the ferroelectric capacitor at low temperature etc. It is possible to prevent the accuracy of the read / write operation from being lowered when Vc is high.

  Further, in the ferroelectric memory 1, a period in which a high voltage is applied to the ferroelectric capacitor through the plate line and the bit line is a pulse-shaped predetermined period which is 20 ns in one example. During a period in which a high voltage is applied to the ferroelectric capacitor, there is little variation due to the external power supply voltage and temperature, and it is not influenced by the control timing of a device disposed outside the ferroelectric memory 1. In the ferroelectric memory 1, since a period in which a high voltage is applied to the ferroelectric capacitor is constant, voltage stress applied to the gate oxide film of the ferroelectric capacitor and the cell transistor is constant.

  For example, when the second voltage SVII is 2 [V] and the film thickness of the ferroelectric capacitor is 500 [Å], the electric field strength of the electric field applied to the ferroelectric capacitor is 0.4 as in the conventional case. It will be about [MeV / cm]. In addition, when the gate oxide film thickness of the MOSFET used in the cell transistor is 40 Å and the third voltage VPP applied to the word line signal is 3.0 V, the gate oxidation is applied to the gate oxidation. The field strength of the applied electric field is about 7.5 [MeV / cm].

  An electric field strength of about 7.5 [MeV / cm] is applied to the cell transistor at the time of data writing, but the time for which the third voltage VPP is applied to the word line signal is limited to about 20 [ns]. Therefore, the withstand voltage characteristics of the transistor can have a margin.

  Further, in the ferroelectric memory 1, after reading data stored in the memory cell, the transfer transistor is turned off and the precharge transistor is turned on, whereby the memory cell from which the data is read has the data value "0". Data is written. The ferroelectric memory 1 writes the data value "0" in the ferroelectric capacitor by writing the data value "0" in both ferroelectric capacitors when data is read in the 2T2C type memory cell. The process of applying the second voltage to the plate line can be omitted. Since the ferroelectric memory 1 can omit the process of applying the second voltage to the plate line in order to write the data value "0" in the ferroelectric capacitor, a period for applying the second voltage to the plate line is taken. It can be shortened.

  As shown in FIG. 5, in the ferroelectric memory 900, a high voltage is applied to the plate line over the period from time t4 to time t8. On the other hand, as shown in FIG. 11, in the ferroelectric memory 1, a high voltage is applied to the plate line over the period from time t3 to time t7. When the time per read / write cycle in the ferroelectric memory 900 is 200 ns, the period from time t4 to time t8 is approximately 100 ns. Since the ferroelectric memory 1 can apply a high voltage to the plate line as described above, the time for applying the high voltage to the plate line with respect to the ferroelectric memory 900 can be reduced to about 1⁄5. The ferroelectric memory 1 can reduce the time for applying a high voltage to the plate line to the ferroelectric memory 900 to about 1/5, and therefore the withstand voltage tolerance such as leak current of the memory cell is 1/5. The cumulative time of voltage stress can be reduced by about five times.

(Configuration and Function of Ferroelectric Memory According to Second Embodiment)
FIG. 12 is a block diagram of a ferroelectric memory according to the second embodiment, and FIG. 13 is a circuit diagram of the ferroelectric memory shown in FIG.

  The ferroelectric memory 2 according to the second embodiment is different from the ferroelectric memory according to the first embodiment in that booster circuits 51 and 52 are arranged in parallel with n pairs of transfer transistors 41 and 42, respectively. . The ferroelectric memory 2 is different from the ferroelectric memory according to the first embodiment in that the sense amplifier 20 is disposed instead of the sense amplifier 40. The ferroelectric memory 2 has the same configuration and function as the ferroelectric memory according to the first embodiment except that the sense amplifier 20 and the booster circuits 51 and 52 are arranged, so the entire functional block diagram is omitted. Do.

  FIG. 14 is a circuit diagram of the booster circuit 51. As shown in FIG.

  The booster circuit 51 includes first to sixth transistors 61 to 66 and an inverter 67. The supply voltage SVIIm is generated when the activation signal / φ WAn becomes the ground voltage and the first transistor 61 and the second transistor 62 are turned on. Is supplied to the first bit line 16. Booster circuit 52 has a circuit configuration similar to that of booster circuit 51, and when the activation signal / φWAn becomes the ground voltage and the first transistor 61 and the second transistor 62 turn on the second voltage SVII as the second bit line Supply to 17.

  FIG. 15 is a timing chart showing the operation of the ferroelectric memory 2. In FIG. 15, a waveform 1501 indicates a chip enable signal CEB, a waveform 1502 indicates a precharge signal φPRn, and a waveform 1503 indicates a bit transfer signal φBTn. A waveform 1504 indicates the first sense amplifier signal φ / SA, a waveform 1505 indicates the second sense amplifier signal φSA, and a waveform 1506 indicates the word line signal WL1. A waveform 1507 shows a plate line signal CP1, a waveform 1508 shows a first bit line signal BL1, a waveform 1509 shows a second bit line signal / BL1, and a waveform 1510 shows an activation signal / φ WAn. A waveform 1511 indicates unselected bit line signals BL 'and / BL', a waveform 1512 indicates a first sense amplifier data signal SAD, a waveform 1513 indicates a second sense amplifier data signal SA / D, and a waveform 1514 indicates a boost power supply SVIIm is shown and waveform 1515 shows the non-selected capacitor signal n.

  The operation of time t0 to t7 is the same as that of ferroelectric memory 1 described with reference to FIG. 11 except that bit transfer signal .phi.BTn is maintained at first voltage VII without rising transition to second voltage SVII at t1. It is the same as the operation, so the detailed description is omitted here.

  At time t8, in response to the rising transition of the chip enable signal CEB, the ferroelectric memory 2 ends the activation state. At time t9, bit transfer signal φBTn is boosted to first voltage VII. At the same time, in response to the falling transition of the precharge signal φPRn, precharging of the first bit line 16 and the second bit line 17 to the ground voltage VSS is stopped again.

  Next, at time t10, the booster circuit 52 boosts the supply voltage SVIIm supplied to the second bit line 17 from the first voltage VII to the second voltage SVII. Next, at time t11, the activation signal / φ WAn becomes the ground voltage, and the second voltage SVII is supplied from the booster circuit 52 to the second bit line 17.

  Next, at time t12, the word line signal WL1 is boosted to the third voltage VPP, and the data value “1” is written to the second ferroelectric capacitor 14 via the second cell transistor 13.

  Next, at time t13, the first sense amplifier signal φ / SA makes a rising transition, and the second sense amplifier signal φSA makes a falling transition. Next, at time t14, in response to rising transition of precharge signal φPRn, precharging to ground voltage VSS of first bit line 16 and second bit line 17 is resumed, and first bit line 16 and the first bit line 16 The voltage of the 2 bit line 17 becomes the ground voltage. Then, at time t15, in response to the completion of the word line selection, the word line signal WL1 makes a falling transition. The period from time t12 to time t15 when the third voltage VPP is applied to the word line 18 is preferably about 20 [ns] similarly to the period when the second voltage SVII is applied to the plate line 19.

(Operation and Effect of Ferroelectric Memory According to Second Embodiment)
In the ferroelectric memory 2, when writing the data value “1”, the second circuit, which is a high voltage, is supplied from the booster circuit to the bit line without passing through the sense amplifier and the transfer transistor. Can be reduced. In addition, by reducing the number of elements to which the second voltage and the third voltage are supplied that are higher than the first voltage, the charge / discharge path to the element to which the high voltage is supplied is reduced, thereby reducing power consumption. Ru.

(Modification of Ferroelectric Memory According to Embodiment)
The ferroelectric memories 1 and 2 are memories that perform the write operation and the read operation according to the Hi-z method, but the ferroelectric memory according to the embodiment is based on another method such as the bit line GND sense method (BGS method) The memory may be a write operation and a read operation.

(Modification of Ferroelectric Memory According to Embodiment)
Further, in the ferroelectric memories 1 and 2, the bit lines are not hierarchized, but in the ferroelectric memory according to the embodiment, the bit lines may be hierarchized.

1, 2 Ferroelectric Memory 10 Memory Cell 11 First Cell Transistor 12 First Ferroelectric Capacitor 13 Second Cell Transistor 14 Second Ferroelectric Capacitor 16 First Bit Line 17 Second Bit Line 18 Word Line 19 Plate Line 20, 40 sense amplifiers

Claims (5)

With multiple word lines,
With multiple bit lines,
A plurality of memory cells each having a ferroelectric capacitor, and a cell transistor connecting a first electrode of the ferroelectric capacitor to the plurality of bit lines depending on selection of the word line;
A plate line connected to the second electrode of the ferroelectric capacitor;
A sense amplifier for amplifying, with a first voltage, an electrical quantity indicating data read from each of the plurality of memory cells;
When reading data stored in any of the plurality of memory cells, the plate line connected to the second electrode of the memory cell from which data is read is pulsed with a second voltage higher than the first voltage. -Like, ferroelectric memory.   When writing data in any of the plurality of memory cells, the memory cell to which data is written is applied with the second voltage in a pulse shape via the bit line connected via the cell transistor. The ferroelectric memory according to claim 1. A plurality of transfer transistors that connect between the plurality of bit lines and the sense amplifier when turned on, and cut off connections between the plurality of bit lines and the sense amplifier when turned off;
And a plurality of precharge transistors that ground each of the plurality of bit lines when turned on.
After the data stored in any of the plurality of memory cells is read, the plurality of transfer transistors are turned off and the plurality of precharge transistors are turned on. The ferroelectric memory according to claim 1, wherein data indicating a value “0” is written.   The period during which the second voltage is applied to the plate line is a period from when data is read from the memory cell to when data indicating a data value "0" is written to the memory cell. Ferroelectric memory as described in. With multiple word lines,
With multiple bit lines,
A plurality of memory cells each having a ferroelectric capacitor, and a cell transistor connecting a first electrode of the ferroelectric capacitor to the plurality of bit lines depending on selection of the word line;
A plate line connected to the second electrode of the ferroelectric capacitor;
A control method of a ferroelectric memory including: a sense amplifier amplifying at a first voltage an electrical quantity indicating data read from each of a plurality of memory cells,
Applying a second voltage higher than the first voltage in a pulse shape to the plate line connected to the second electrode of the memory cell from which data is read;
Turning on the cell transistor to supply an electric quantity indicating data from the ferroelectric capacitor to the sense amplifier through any of the plurality of bit lines;
The sense amplifier amplifies the voltage corresponding to the supplied amount of electricity to the first voltage,
Outputting the amplified voltage;
Control methods for ferroelectric memories, including:

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